-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 -- ldbanno -n VHDL -o RAM2GS_LCMXO2_640HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd -- Netlist created on Tue Aug 15 22:56:31 2023 -- Netlist written on Tue Aug 15 22:56:33 2023 -- Design is for device LCMXO2-640HC -- Design is for package TQFP100 -- Design is for performance grade 4 -- entity vmuxregsre library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity vmuxregsre is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; end vmuxregsre; architecture Structure of vmuxregsre is begin INST01: FL1P3DX generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); end Structure; -- entity vcc library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity vcc is port (PWR1: out Std_logic); ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; end vcc; architecture Structure of vcc is begin INST1: VHI port map (Z=>PWR1); end Structure; -- entity gnd library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity gnd is port (PWR0: out Std_logic); ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; end gnd; architecture Structure of gnd is begin INST1: VLO port map (Z=>PWR0); end Structure; -- entity ccu2B0 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity ccu2B0 is port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; end ccu2B0; architecture Structure of ccu2B0 is begin inst1: CCU2D generic map (INIT0 => X"000A", INIT1 => X"300A", INJECT1_0 => "NO", INJECT1_1 => "NO") port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); end Structure; -- entity SLICE_0 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_0 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_0"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; end SLICE_0; architecture Structure of SLICE_0 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu2B0 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_0: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_cry_0_0: ccu2B0 port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, DI1_dly, CLK_dly, F1_out, Q1_out, FCO_out) VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity ccu20001 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity ccu20001 is port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; end ccu20001; architecture Structure of ccu20001 is begin inst1: CCU2D generic map (INIT0 => X"5002", INIT1 => X"300A", INJECT1_0 => "NO", INJECT1_1 => "NO") port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); end Structure; -- entity SLICE_1 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_1 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_1"; tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; end SLICE_1; architecture Structure of SLICE_1 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20001 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_17: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_s_0_17: ccu20001 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, CO1=>open); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity ccu20002 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity ccu20002 is port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; end ccu20002; architecture Structure of ccu20002 is begin inst1: CCU2D generic map (INIT0 => X"300A", INIT1 => X"300A", INJECT1_0 => "NO", INJECT1_1 => "NO") port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); end Structure; -- entity SLICE_2 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_2 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_2"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; end SLICE_2; architecture Structure of SLICE_2 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_16: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_15: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_15: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_3 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_3 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_3"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; end SLICE_3; architecture Structure of SLICE_3 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_14: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_13: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_13: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_4 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_4 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_4"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; end SLICE_4; architecture Structure of SLICE_4 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_12: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_11: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_11: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_5 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_5 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_5"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; end SLICE_5; architecture Structure of SLICE_5 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_10: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_9: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_9: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_6 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_6 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_6"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; end SLICE_6; architecture Structure of SLICE_6 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_8: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_7: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_7: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_7 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_7 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_7"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; end SLICE_7; architecture Structure of SLICE_7 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_6: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_5: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_5: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_8 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_8 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_8"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; end SLICE_8; architecture Structure of SLICE_8 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_4: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_3: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_3: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_9 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_9 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_9"; tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; end SLICE_9; architecture Structure of SLICE_9 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal FCI_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal FCO_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component ccu20002 port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); end component; begin FS_2: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); FS_1: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); FS_cry_0_1: ccu20002 port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, CO1=>FCO_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); VitalWireDelay(FCI_ipd, FCI, tipd_FCI); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE FCO_zd : std_logic := 'X'; VARIABLE FCO_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; FCO_zd := FCO_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE), 1 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F1, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, Paths => (0 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_FCO, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_FCO, PathCondition => TRUE), 2 => (InputChangeTime => FCI_ipd'last_event, PathDelay => tpd_FCI_FCO, PathCondition => TRUE)), GlitchData => FCO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut4 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut4 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; end lut4; architecture Structure of lut4 is begin INST10: ROM16X1A generic map (initval => X"8080") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40003 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40003 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; end lut40003; architecture Structure of lut40003 is begin INST10: ROM16X1A generic map (initval => X"00F2") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity inverter library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity inverter is port (I: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; end inverter; architecture Structure of inverter is begin INST1: INV port map (A=>I, Z=>Z); end Structure; -- entity SLICE_10 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_10 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_10"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; end SLICE_10; architecture Structure of SLICE_10 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut4 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40003 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; begin CmdEnable17: lut4 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); ADSubmitted_r: lut40003 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); ADSubmitted: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40004 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40004 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; end lut40004; architecture Structure of lut40004 is begin INST10: ROM16X1A generic map (initval => X"8000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40005 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40005 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; end lut40005; architecture Structure of lut40005 is begin INST10: ROM16X1A generic map (initval => X"F2F2") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_13 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_13 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_13"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_13 : ENTITY IS TRUE; end SLICE_13; architecture Structure of SLICE_13 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40005 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdEnable16: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); C1Submitted_s: lut40005 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); C1Submitted: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40006 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40006 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; end lut40006; architecture Structure of lut40006 is begin INST10: ROM16X1A generic map (initval => X"EEEE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40007 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40007 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; end lut40007; architecture Structure of lut40007 is begin INST10: ROM16X1A generic map (initval => X"5555") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_14 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_14 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_14"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; end SLICE_14; architecture Structure of SLICE_14 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40007 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nCCAS_pad_RNI01SJ: lut40006 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); nCCAS_pad_RNISUR8: lut40007 port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); CASr2: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CASr: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40008 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40008 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; end lut40008; architecture Structure of lut40008 is begin INST10: ROM16X1A generic map (initval => X"0800") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40009 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40009 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; end lut40009; architecture Structure of lut40009 is begin INST10: ROM16X1A generic map (initval => X"DDDD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity vmuxregsre0010 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity vmuxregsre0010 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre0010 : ENTITY IS TRUE; end vmuxregsre0010; architecture Structure of vmuxregsre0010 is begin INST01: FL1P3IY generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); end Structure; -- entity SLICE_17 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_17 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_17"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_LSR : VitalDelayType := 0 ns; tpw_LSR_posedge : VitalDelayType := 0 ns; tpw_LSR_negedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_17 : ENTITY IS TRUE; end SLICE_17; architecture Structure of SLICE_17 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40009 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0010 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin Ready_0_sqmuxa_0_a3_2: lut40008 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); S_RNO_0: lut40009 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); S_0: vmuxregsre0010 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_LSR : x01 := '0'; VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => LSR_ipd, TestSignalName => "LSR", Period => tperiod_LSR, PulseWidthHigh => tpw_LSR_posedge, PulseWidthLow => tpw_LSR_negedge, PeriodData => periodcheckinfo_LSR, Violation => tviol_LSR_LSR, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40011 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40011 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; end lut40011; architecture Structure of lut40011 is begin INST10: ROM16X1A generic map (initval => X"EEEE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40012 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40012 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; end lut40012; architecture Structure of lut40012 is begin INST10: ROM16X1A generic map (initval => X"AC8C") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity selmux2 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity selmux2 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; end selmux2; architecture Structure of selmux2 is begin INST1: MUX21 port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); end Structure; -- entity SLICE_18 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_18 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_18"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; end SLICE_18; architecture Structure of SLICE_18 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal GNDI: Std_logic; signal SLICE_18_SLICE_18_K1_H1: Std_logic; signal SLICE_18_CmdEnable_s_GATE_H0: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40011 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40012 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; begin SLICE_18_K1: lut40011 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>SLICE_18_SLICE_18_K1_H1); DRIVEGND: gnd port map (PWR0=>GNDI); CmdEnable_s_GATE: lut40012 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>SLICE_18_CmdEnable_s_GATE_H0); CmdEnable: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); SLICE_18_K0K1MUX: selmux2 port map (D0=>SLICE_18_CmdEnable_s_GATE_H0, D1=>SLICE_18_SLICE_18_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; OFX0_zd := OFX0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40013 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40013 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; end lut40013; architecture Structure of lut40013 is begin INST10: ROM16X1A generic map (initval => X"0101") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40014 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40014 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; end lut40014; architecture Structure of lut40014 is begin INST10: ROM16X1A generic map (initval => X"0203") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_19 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_19 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_19"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; end SLICE_19; architecture Structure of SLICE_19 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40013 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40014 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdLEDEN_4_u_i_a2_0: lut40013 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); CmdLEDEN_RNO: lut40014 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CmdLEDEN: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40015 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40015 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; end lut40015; architecture Structure of lut40015 is begin INST10: ROM16X1A generic map (initval => X"2000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_20 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_20 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_20"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; end SLICE_20; architecture Structure of SLICE_20 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40015 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdUFMCLK_1_sqmuxa_0_a2: lut40015 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); CmdSubmitted_RNO: lut40006 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); CmdSubmitted: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40016 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40016 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; end lut40016; architecture Structure of lut40016 is begin INST10: ROM16X1A generic map (initval => X"0808") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40017 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40017 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; end lut40017; architecture Structure of lut40017 is begin INST10: ROM16X1A generic map (initval => X"5151") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_21 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_21 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_21"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE; end SLICE_21; architecture Structure of SLICE_21 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40016 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40017 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin Cmdn8MEGEN_4_u_i_a2_2: lut40016 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); Cmdn8MEGEN_RNO: lut40017 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); Cmdn8MEGEN: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40018 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40018 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; end lut40018; architecture Structure of lut40018 is begin INST10: ROM16X1A generic map (initval => X"0008") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_22 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_22 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_22"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE; end SLICE_22; architecture Structure of SLICE_22 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40007 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40018 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CMDWR_2: lut40018 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); FWEr_RNO: lut40007 port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); FWEr: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40019 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40019 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; end lut40019; architecture Structure of lut40019 is begin INST10: ROM16X1A generic map (initval => X"FFF7") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40020 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40020 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; end lut40020; architecture Structure of lut40020 is begin INST10: ROM16X1A generic map (initval => X"A9A9") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_23 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_23 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_23"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; end SLICE_23; architecture Structure of SLICE_23 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40019 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40020 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RA10_0io_RNO: lut40019 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); IS_RNO_0: lut40020 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); IS_0: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40021 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40021 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; end lut40021; architecture Structure of lut40021 is begin INST10: ROM16X1A generic map (initval => X"7878") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40022 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40022 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; end lut40022; architecture Structure of lut40022 is begin INST10: ROM16X1A generic map (initval => X"6666") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_24 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_24 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_24"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; end SLICE_24; architecture Structure of SLICE_24 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40021 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40022 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin IS_RNO_2: lut40021 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); IS_n1_0_x2: lut40022 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); IS_2: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); IS_1: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_posedge, SetupLow => tsetup_DI1_CLK_noedge_posedge, HoldHigh => thold_DI1_CLK_noedge_posedge, HoldLow => thold_DI1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40023 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40023 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; end lut40023; architecture Structure of lut40023 is begin INST10: ROM16X1A generic map (initval => X"6AAA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_25 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_25 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_25"; tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; end SLICE_25; architecture Structure of SLICE_25 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40023 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin IS_RNO_3: lut40023 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); IS_3: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_26 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_26 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_26"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; end SLICE_26; architecture Structure of SLICE_26 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin InitReady3_0_a2: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); InitReady_RNO: lut40006 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); InitReady: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40024 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40024 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; end lut40024; architecture Structure of lut40024 is begin INST10: ROM16X1A generic map (initval => X"BBBB") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_27 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_27 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_27"; tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; end SLICE_27; architecture Structure of SLICE_27 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40024 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin LEDEN_RNO: lut40024 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); LEDEN: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40025 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40025 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; end lut40025; architecture Structure of lut40025 is begin INST10: ROM16X1A generic map (initval => X"FBFB") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_29 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_29 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_29"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE; end SLICE_29; architecture Structure of SLICE_29 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40007 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40025 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin LED_pad_RNO: lut40025 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RASr_RNO: lut40007 port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); RASr2: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); RASr: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40026 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40026 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; end lut40026; architecture Structure of lut40026 is begin INST10: ROM16X1A generic map (initval => X"5072") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40027 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40027 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; end lut40027; architecture Structure of lut40027 is begin INST10: ROM16X1A generic map (initval => X"DCCC") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_31 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_31 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_31"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; end SLICE_31; architecture Structure of SLICE_31 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40026 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40027 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RCKEEN_8_u_RNO: lut40026 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); RCKEEN_8_u: lut40027 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RCKEEN: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40028 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40028 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; end lut40028; architecture Structure of lut40028 is begin INST10: ROM16X1A generic map (initval => X"8888") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40029 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40029 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; end lut40029; architecture Structure of lut40029 is begin INST10: ROM16X1A generic map (initval => X"FE30") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_32 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_32 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_32"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; end SLICE_32; architecture Structure of SLICE_32 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40029 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RBAd_1: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RCKE_2_0: lut40029 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); RASr3: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); RCKE: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40030 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40030 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; end lut40030; architecture Structure of lut40030 is begin INST10: ROM16X1A generic map (initval => X"7F7F") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40031 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40031 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; end lut40031; architecture Structure of lut40031 is begin INST10: ROM16X1A generic map (initval => X"AEAA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_33 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_33 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_33"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; end SLICE_33; architecture Structure of SLICE_33 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40030 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40031 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin Ready_0_sqmuxa_0_o2: lut40030 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); Ready_RNO: lut40031 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); Ready: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40032 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40032 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; end lut40032; architecture Structure of lut40032 is begin INST10: ROM16X1A generic map (initval => X"0200") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_34 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_34 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_34"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; end SLICE_34; architecture Structure of SLICE_34 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40032 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin Ready_0_sqmuxa_0_a3: lut40032 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); Ready_fast_RNO: lut40006 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); Ready_fast: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_35 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_35 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_35"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; end SLICE_35; architecture Structure of SLICE_35 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RowAd_1: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowAd_0: lut40028 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); RowA_1: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); RowA_0: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_negedge, SetupLow => tsetup_DI1_CLK_noedge_negedge, HoldHigh => thold_DI1_CLK_noedge_negedge, HoldLow => thold_DI1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_36 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_36 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_36"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; end SLICE_36; architecture Structure of SLICE_36 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RowAd_3: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowAd_2: lut40028 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); RowA_3: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); RowA_2: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_negedge, SetupLow => tsetup_DI1_CLK_noedge_negedge, HoldHigh => thold_DI1_CLK_noedge_negedge, HoldLow => thold_DI1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_37 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_37 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_37"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; end SLICE_37; architecture Structure of SLICE_37 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40024 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RowAd_5: lut40024 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowAd_4: lut40028 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); RowA_5: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); RowA_4: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_negedge, SetupLow => tsetup_DI1_CLK_noedge_negedge, HoldHigh => thold_DI1_CLK_noedge_negedge, HoldLow => thold_DI1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_38 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_38 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_38"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_38 : ENTITY IS TRUE; end SLICE_38; architecture Structure of SLICE_38 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RowAd_7: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowAd_6: lut40028 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); RowA_7: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); RowA_6: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_negedge, SetupLow => tsetup_DI1_CLK_noedge_negedge, HoldHigh => thold_DI1_CLK_noedge_negedge, HoldLow => thold_DI1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_39 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_39 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_39"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI1_CLK : VitalDelayType := 0 ns; tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE; end SLICE_39; architecture Structure of SLICE_39 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI1_ipd : std_logic := 'X'; signal DI1_dly : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40024 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RowAd_9: lut40024 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RowAd_8: lut40028 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); RowA_9: vmuxregsre port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); RowA_8: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI1_ipd, DI1, tipd_DI1); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI1_CLK : x01 := '0'; VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI1_dly, TestSignalName => "DI1", TestDelay => tisd_DI1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI1_CLK_noedge_negedge, SetupLow => tsetup_DI1_CLK_noedge_negedge, HoldHigh => thold_DI1_CLK_noedge_negedge, HoldLow => thold_DI1_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI1_CLK_TimingDatash, Violation => tviol_DI1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_40 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_40 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_40"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_LSR : VitalDelayType := 0 ns; tpw_LSR_posedge : VitalDelayType := 0 ns; tpw_LSR_negedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_40 : ENTITY IS TRUE; end SLICE_40; architecture Structure of SLICE_40 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; signal LSR_NOTIN: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0010 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40015 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRCAS_0_sqmuxa_1_0_a3: lut40015 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); S_0_i_o2_1: lut40006 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); S_1: vmuxregsre0010 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_NOTIN, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); LSR_INVERTERIN: inverter port map (I=>LSR_dly, Z=>LSR_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_LSR : x01 := '0'; VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => LSR_ipd, TestSignalName => "LSR", Period => tperiod_LSR, PulseWidthHigh => tpw_LSR_posedge, PulseWidthLow => tpw_LSR_negedge, PeriodData => periodcheckinfo_LSR, Violation => tviol_LSR_LSR, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40033 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40033 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; end lut40033; architecture Structure of lut40033 is begin INST10: ROM16X1A generic map (initval => X"1110") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40034 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40034 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; end lut40034; architecture Structure of lut40034 is begin INST10: ROM16X1A generic map (initval => X"2222") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_41 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_41 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_41"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE; end SLICE_41; architecture Structure of SLICE_41 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal OFX0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal SLICE_41_SLICE_41_K1_H1: Std_logic; signal GNDI: Std_logic; signal SLICE_41_UFMSDI_RNO_GATE_H0: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component selmux2 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; Z: out Std_logic); end component; component lut40033 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40034 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin SLICE_41_K1: lut40033 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>SLICE_41_SLICE_41_K1_H1); UFMSDI_RNO_GATE: lut40034 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>SLICE_41_UFMSDI_RNO_GATE_H0); DRIVEGND: gnd port map (PWR0=>GNDI); UFMSDI: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); SLICE_41_K0K1MUX: selmux2 port map (D0=>SLICE_41_UFMSDI_RNO_GATE_H0, D1=>SLICE_41_SLICE_41_K1_H1, SD=>M0_ipd, Z=>OFX0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) VARIABLE OFX0_zd : std_logic := 'X'; VARIABLE OFX0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; OFX0_zd := OFX0_out; Q0_zd := Q0_out; VitalPathDelay01 ( OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_OFX0, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_OFX0, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_OFX0, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_OFX0, PathCondition => TRUE), 4 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_OFX0, PathCondition => TRUE), 5 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_OFX0, PathCondition => TRUE), 6 => (InputChangeTime => M0_ipd'last_event, PathDelay => tpd_M0_OFX0, PathCondition => TRUE)), GlitchData => OFX0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40035 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40035 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; end lut40035; architecture Structure of lut40035 is begin INST10: ROM16X1A generic map (initval => X"0001") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40036 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40036 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; end lut40036; architecture Structure of lut40036 is begin INST10: ROM16X1A generic map (initval => X"A0CC") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_42 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_42 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_42"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE; end SLICE_42; architecture Structure of SLICE_42 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40035 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40036 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_Din_3: lut40035 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); XOR8MEG_3_u: lut40036 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); XOR8MEG: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_negedge, SetupLow => tsetup_DI0_CLK_noedge_negedge, HoldHigh => thold_DI0_CLK_noedge_negedge, HoldLow => thold_DI0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40037 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40037 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; end lut40037; architecture Structure of lut40037 is begin INST10: ROM16X1A generic map (initval => X"8B8B") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_43 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_43 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_43"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; end SLICE_43; architecture Structure of SLICE_43 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40037 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_Bank_1_4: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); n8MEGEN_5_i_m2: lut40037 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); n8MEGEN: vmuxregsre port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40038 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40038 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; end lut40038; architecture Structure of lut40038 is begin INST10: ROM16X1A generic map (initval => X"1000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40039 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40039 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; end lut40039; architecture Structure of lut40039 is begin INST10: ROM16X1A generic map (initval => X"DCEC") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_44 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_44 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_44"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_LSR : VitalDelayType := 0 ns; tpw_LSR_posedge : VitalDelayType := 0 ns; tpw_LSR_negedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; end SLICE_44; architecture Structure of SLICE_44 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component vmuxregsre0010 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component lut40038 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40039 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRowColSel_0_0_a3_0: lut40038 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); nRowColSel_0_0: lut40039 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); nRowColSel: vmuxregsre0010 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_LSR : x01 := '0'; VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => LSR_ipd, TestSignalName => "LSR", Period => tperiod_LSR, PulseWidthHigh => tpw_LSR_posedge, PulseWidthLow => tpw_LSR_negedge, PeriodData => periodcheckinfo_LSR, Violation => tviol_LSR_LSR, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40040 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40040 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; end lut40040; architecture Structure of lut40040 is begin INST10: ROM16X1A generic map (initval => X"000B") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40041 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40041 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; end lut40041; architecture Structure of lut40041 is begin INST10: ROM16X1A generic map (initval => X"5F4E") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity vmuxregsre0042 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity vmuxregsre0042 is port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF vmuxregsre0042 : ENTITY IS TRUE; end vmuxregsre0042; architecture Structure of vmuxregsre0042 is begin INST01: FL1P3BX generic map (GSR => "DISABLED") port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); end Structure; -- entity SLICE_45 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_45 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_45"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI0_CLK : VitalDelayType := 0 ns; tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; end SLICE_45; architecture Structure of SLICE_45 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal DI0_ipd : std_logic := 'X'; signal DI0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40040 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40041 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component vmuxregsre0042 port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin nUFMCS_s_0_m4_yy: lut40040 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); nUFMCS_s_0_N_5_i: lut40041 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); nUFMCS: vmuxregsre0042 port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(DI0_ipd, DI0, tipd_DI0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI0_CLK : x01 := '0'; VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI0_dly, TestSignalName => "DI0", TestDelay => tisd_DI0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI0_CLK_noedge_posedge, SetupLow => tsetup_DI0_CLK_noedge_posedge, HoldHigh => thold_DI0_CLK_noedge_posedge, HoldLow => thold_DI0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI0_CLK_TimingDatash, Violation => tviol_DI0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40043 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40043 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; end lut40043; architecture Structure of lut40043 is begin INST10: ROM16X1A generic map (initval => X"EAAA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40044 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40044 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; end lut40044; architecture Structure of lut40044 is begin INST10: ROM16X1A generic map (initval => X"FF80") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_46 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_46 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_46"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_46 : ENTITY IS TRUE; end SLICE_46; architecture Structure of SLICE_46 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40043 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40044 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_ADWR: lut40043 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); un1_CMDWR: lut40044 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40045 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40045 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; end lut40045; architecture Structure of lut40045 is begin INST10: ROM16X1A generic map (initval => X"0B00") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_47 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_47 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_47"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_47 : ENTITY IS TRUE; end SLICE_47; architecture Structure of SLICE_47 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40035 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40045 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nUFMCS15_0_a2: lut40035 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); UFMCLK_0io_RNO: lut40045 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40046 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40046 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; end lut40046; architecture Structure of lut40046 is begin INST10: ROM16X1A generic map (initval => X"0E0E") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_48 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_48 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_48"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_48 : ENTITY IS TRUE; end SLICE_48; architecture Structure of SLICE_48 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40015 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40046 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin UFMCLK_r_i_a2_2_2: lut40015 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); UFMCLK_0io_RNO_1: lut40046 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40047 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40047 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; end lut40047; architecture Structure of lut40047 is begin INST10: ROM16X1A generic map (initval => X"0BFB") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_49 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_49 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_49"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; end SLICE_49; architecture Structure of SLICE_49 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40019 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40047 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin IS_0_sqmuxa_0_o2_0: lut40019 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); un1_nRCAS_6_sqmuxa_i_0: lut40047 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40048 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40048 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; end lut40048; architecture Structure of lut40048 is begin INST10: ROM16X1A generic map (initval => X"2722") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40049 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40049 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; end lut40049; architecture Structure of lut40049 is begin INST10: ROM16X1A generic map (initval => X"F4F4") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_50 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_50 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_50"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; end SLICE_50; architecture Structure of SLICE_50 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40048 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40049 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin Cmdn8MEGEN_4_u_i_0: lut40048 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); Cmdn8MEGEN_4_u_i_o2: lut40049 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40050 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40050 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; end lut40050; architecture Structure of lut40050 is begin INST10: ROM16X1A generic map (initval => X"1313") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40051 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40051 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; end lut40051; architecture Structure of lut40051 is begin INST10: ROM16X1A generic map (initval => X"1303") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_51 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_51 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_51"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE; end SLICE_51; architecture Structure of SLICE_51 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40050 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40051 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRCAS_0io_RNO_0: lut40050 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); nRCAS_0io_RNO: lut40051 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40052 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40052 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; end lut40052; architecture Structure of lut40052 is begin INST10: ROM16X1A generic map (initval => X"FEFE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40053 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40053 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; end lut40053; architecture Structure of lut40053 is begin INST10: ROM16X1A generic map (initval => X"5051") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_52 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_52 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_52"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE; end SLICE_52; architecture Structure of SLICE_52 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40052 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40053 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_nRCAS_6_sqmuxa_i_o2: lut40052 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); nRRAS_5_u_i_0_RNILD5I: lut40053 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40054 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40054 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; end lut40054; architecture Structure of lut40054 is begin INST10: ROM16X1A generic map (initval => X"FF40") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40055 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40055 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; end lut40055; architecture Structure of lut40055 is begin INST10: ROM16X1A generic map (initval => X"0202") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_53 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_53 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_53"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_53 : ENTITY IS TRUE; end SLICE_53; architecture Structure of SLICE_53 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40054 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40055 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRWE_s_i_tz_0: lut40054 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); S_RNICVV51_0: lut40055 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40056 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40056 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; end lut40056; architecture Structure of lut40056 is begin INST10: ROM16X1A generic map (initval => X"4444") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40057 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40057 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; end lut40057; architecture Structure of lut40057 is begin INST10: ROM16X1A generic map (initval => X"F8F0") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_54 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_54 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_54"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_54 : ENTITY IS TRUE; end SLICE_54; architecture Structure of SLICE_54 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40056 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40057 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_PHI2r3_0: lut40056 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un1_FS_13_i_0: lut40057 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_55 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_55 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_55"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE; end SLICE_55; architecture Structure of SLICE_55 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut4 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40057 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_FS_14_i_a2_0: lut4 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un1_FS_14_i_0: lut40057 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40058 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40058 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; end lut40058; architecture Structure of lut40058 is begin INST10: ROM16X1A generic map (initval => X"0100") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_56 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_56 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_56"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; end SLICE_56; architecture Structure of SLICE_56 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut4 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40058 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_FS_13_i_a2_1: lut40058 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); un1_FS_13_i_a2: lut4 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40059 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40059 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; end lut40059; architecture Structure of lut40059 is begin INST10: ROM16X1A generic map (initval => X"2202") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_57 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_57 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_57"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; end SLICE_57; architecture Structure of SLICE_57 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40059 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdSubmitted_1_sqmuxa_0_a2: lut40059 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); XOR8MEG18: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40060 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40060 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; end lut40060; architecture Structure of lut40060 is begin INST10: ROM16X1A generic map (initval => X"5155") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_58 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_58 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_58"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; end SLICE_58; architecture Structure of SLICE_58 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40032 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40060 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin UFMSDI_ens2_i_a2_4_2: lut40032 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); UFMSDI_ens2_i_a0: lut40060 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_59 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_59 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_59"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; end SLICE_59; architecture Structure of SLICE_59 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40013 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40015 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin UFMSDI_en_ss0_0_a2_0: lut40013 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un1_FS_13_i_a2_8: lut40015 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_60 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_60 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_60"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; end SLICE_60; architecture Structure of SLICE_60 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin ADWR_3: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); ADWR: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40061 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40061 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; end lut40061; architecture Structure of lut40061 is begin INST10: ROM16X1A generic map (initval => X"1010") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40062 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40062 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; end lut40062; architecture Structure of lut40062 is begin INST10: ROM16X1A generic map (initval => X"FF32") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_61 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_61 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_61"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; end SLICE_61; architecture Structure of SLICE_61 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40061 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40062 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRCS_0io_RNO_0: lut40061 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); nRRAS_5_u_i: lut40062 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40063 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40063 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; end lut40063; architecture Structure of lut40063 is begin INST10: ROM16X1A generic map (initval => X"0002") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_62 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_62 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_62"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; end SLICE_62; architecture Structure of SLICE_62 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40063 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RA10_2_sqmuxa_0_o2: lut40006 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); nRWE_s_i_a3_1_0: lut40063 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40064 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40064 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; end lut40064; architecture Structure of lut40064 is begin INST10: ROM16X1A generic map (initval => X"2222") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_63 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_63 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_63"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; end SLICE_63; architecture Structure of SLICE_63 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40064 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin C1WR_1: lut40064 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); C1WR_3: lut40008 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); Bank_0io_1: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); Bank_0io_0: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40065 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40065 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; end lut40065; architecture Structure of lut40065 is begin INST10: ROM16X1A generic map (initval => X"AAC0") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_64 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_64 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_64"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; end SLICE_64; architecture Structure of SLICE_64 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40052 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40065 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin UFMSDI_ens2_i_o2_0: lut40052 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); UFMCLK_r_i_m2: lut40065 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40066 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40066 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; end lut40066; architecture Structure of lut40066 is begin INST10: ROM16X1A generic map (initval => X"3B33") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_65 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_65 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_65"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M1_CLK : VitalDelayType := 0 ns; tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; end SLICE_65; architecture Structure of SLICE_65 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M1_ipd : std_logic := 'X'; signal M1_dly : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal Q1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40006 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40066 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin UFMCLK_0io_RNO_0: lut40006 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); PHI2r3_RNITCN41: lut40066 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); PHI2r3: vmuxregsre port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); DRIVEVCC: vcc port map (PWR1=>VCCI); PHI2r2: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M1_ipd, M1, tipd_M1); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE Q1_zd : std_logic := 'X'; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M1_CLK : x01 := '0'; VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M1_dly, TestSignalName => "M1", TestDelay => tisd_M1_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M1_CLK_noedge_posedge, SetupLow => tsetup_M1_CLK_noedge_posedge, HoldHigh => thold_M1_CLK_noedge_posedge, HoldLow => thold_M1_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M1_CLK_TimingDatash, Violation => tviol_M1_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; Q1_zd := Q1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q1, PathCondition => TRUE)), GlitchData => Q1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40067 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40067 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; end lut40067; architecture Structure of lut40067 is begin INST10: ROM16X1A generic map (initval => X"3AFA") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40068 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40068 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; end lut40068; architecture Structure of lut40068 is begin INST10: ROM16X1A generic map (initval => X"200F") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_66 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_66 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_66"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; end SLICE_66; architecture Structure of SLICE_66 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40067 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40068 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRCS_0io_RNO: lut40067 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); nRCAS_r_i_a3_1_1_tz: lut40068 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_67 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_67 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_67"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; end SLICE_67; architecture Structure of SLICE_67 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40016 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin ADWR_6: lut40004 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); ADWR_2: lut40016 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_68 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_68 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_68"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; end SLICE_68; architecture Structure of SLICE_68 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; signal VCCI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40008 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40064 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdEnable16_3: lut40064 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); CmdEnable16_5: lut40008 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); Bank_0io_2: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_69 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_69 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_69"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; end SLICE_69; architecture Structure of SLICE_69 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40056 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_Bank_1_3: lut40056 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un1_Bank_1: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40069 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40069 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; end lut40069; architecture Structure of lut40069 is begin INST10: ROM16X1A generic map (initval => X"4454") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40070 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40070 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; end lut40070; architecture Structure of lut40070 is begin INST10: ROM16X1A generic map (initval => X"FDFD") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_70 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_70 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_70"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; end SLICE_70; architecture Structure of SLICE_70 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40069 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40070 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdLEDEN_4_u_i_a2: lut40069 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); Cmdn8MEGEN_4_u_i_o2_0: lut40070 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40071 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40071 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; end lut40071; architecture Structure of lut40071 is begin INST10: ROM16X1A generic map (initval => X"2020") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40072 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40072 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; end lut40072; architecture Structure of lut40072 is begin INST10: ROM16X1A generic map (initval => X"AABF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_71 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_71 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_71"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE; end SLICE_71; architecture Structure of SLICE_71 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40071 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40072 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRWE_0io_RNO_0: lut40071 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); nRWE_0io_RNO: lut40072 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40073 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40073 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; end lut40073; architecture Structure of lut40073 is begin INST10: ROM16X1A generic map (initval => X"FFFE") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_72 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_72 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_72"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; end SLICE_72; architecture Structure of SLICE_72 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40004 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40073 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin UFMSDI_ens2_i_o2_0_3: lut40073 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); InitReady3_0_a2_5: lut40004 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_73 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_73 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_73"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; end SLICE_73; architecture Structure of SLICE_73 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component lut40038 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40058 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin CmdEnable16_4: lut40058 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); CmdEnable17_5: lut40038 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CASr3: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_posedge, SetupLow => tsetup_M0_CLK_noedge_posedge, HoldHigh => thold_M0_CLK_noedge_posedge, HoldLow => thold_M0_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40074 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40074 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; end lut40074; architecture Structure of lut40074 is begin INST10: ROM16X1A generic map (initval => X"040C") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40075 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40075 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; end lut40075; architecture Structure of lut40075 is begin INST10: ROM16X1A generic map (initval => X"0080") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_74 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_74 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_74"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_M0_CLK : VitalDelayType := 0 ns; tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; end SLICE_74; architecture Structure of SLICE_74 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal M0_ipd : std_logic := 'X'; signal M0_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal Q0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; signal CLK_NOTIN: Std_logic; component vmuxregsre port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component lut40074 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40075 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin XOR8MEG_3_u_1: lut40074 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); CmdEnable17_4: lut40075 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); CBR: vmuxregsre port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>Q0_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); VitalWireDelay(M0_ipd, M0, tipd_M0); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE Q0_zd : std_logic := 'X'; VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; VARIABLE tviol_M0_CLK : x01 := '0'; VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => M0_dly, TestSignalName => "M0", TestDelay => tisd_M0_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_M0_CLK_noedge_negedge, SetupLow => tsetup_M0_CLK_noedge_negedge, HoldHigh => thold_M0_CLK_noedge_negedge, HoldLow => thold_M0_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => M0_CLK_TimingDatash, Violation => tviol_M0_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; F0_zd := F0_out; Q0_zd := Q0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_Q0, PathCondition => TRUE)), GlitchData => Q0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40076 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40076 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE; end lut40076; architecture Structure of lut40076 is begin INST10: ROM16X1A generic map (initval => X"7777") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40077 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40077 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE; end lut40077; architecture Structure of lut40077 is begin INST10: ROM16X1A generic map (initval => X"ACAC") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_75 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_75 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_75"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; end SLICE_75; architecture Structure of SLICE_75 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40076 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40077 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RDQML: lut40076 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un9_RA_9: lut40077 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40078 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40078 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE; end lut40078; architecture Structure of lut40078 is begin INST10: ROM16X1A generic map (initval => X"4000") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40079 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40079 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE; end lut40079; architecture Structure of lut40079 is begin INST10: ROM16X1A generic map (initval => X"70CF") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_76 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_76 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_76"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; end SLICE_76; architecture Structure of SLICE_76 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; component lut40078 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40079 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRWE_0io_RNO_1: lut40078 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); RCKEEN_8_u_1_0: lut40079 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40080 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40080 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE; end lut40080; architecture Structure of lut40080 is begin INST10: ROM16X1A generic map (initval => X"5400") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity lut40081 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40081 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE; end lut40081; architecture Structure of lut40081 is begin INST10: ROM16X1A generic map (initval => X"1111") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_77 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_77 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_77"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; end SLICE_77; architecture Structure of SLICE_77 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40080 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40081 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin nRRAS_5_u_i_0: lut40080 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40082 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40082 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE; end lut40082; architecture Structure of lut40082 is begin INST10: ROM16X1A generic map (initval => X"2C2C") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_78 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_78 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_78"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; end SLICE_78; architecture Structure of SLICE_78 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40035 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40082 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_FS_14_i_a2_0_1: lut40035 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); UFMSDI_ens2_i_o2: lut40082 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_79 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_79 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_79"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; end SLICE_79; architecture Structure of SLICE_79 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40024 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40077 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RDQMH: lut40024 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un9_RA_8: lut40077 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_80 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_80 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_80"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; end SLICE_80; architecture Structure of SLICE_80 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40077 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un9_RA_7: lut40077 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un9_RA_0: lut40077 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_81 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_81 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_81"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; end SLICE_81; architecture Structure of SLICE_81 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40077 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un9_RA_6: lut40077 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un9_RA_1: lut40077 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_82 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_82 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_82"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; end SLICE_82; architecture Structure of SLICE_82 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40077 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un9_RA_5: lut40077 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un9_RA_2: lut40077 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_83 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_83 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_83"; tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; end SLICE_83; architecture Structure of SLICE_83 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40077 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un9_RA_4: lut40077 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); un9_RA_3: lut40077 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 1 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 2 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 1 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 2 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity lut40083 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity lut40083 is port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE; end lut40083; architecture Structure of lut40083 is begin INST10: ROM16X1A generic map (initval => X"C048") port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); end Structure; -- entity SLICE_84 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_84 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_84"; tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; end SLICE_84; architecture Structure of SLICE_84 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal D0_ipd : std_logic := 'X'; signal C0_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40083 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin RBAd_0: lut40028 port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); DRIVEGND: gnd port map (PWR0=>GNDI); RA11d: lut40083 port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(D0_ipd, D0, tipd_D0); VitalWireDelay(C0_ipd, C0, tipd_C0); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => D0_ipd'last_event, PathDelay => tpd_D0_F0, PathCondition => TRUE), 1 => (InputChangeTime => C0_ipd'last_event, PathDelay => tpd_C0_F0, PathCondition => TRUE), 2 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 3 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 1 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity SLICE_85 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity SLICE_85 is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "SLICE_85"; tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; end SLICE_85; architecture Structure of SLICE_85 is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal D1_ipd : std_logic := 'X'; signal C1_ipd : std_logic := 'X'; signal B1_ipd : std_logic := 'X'; signal A1_ipd : std_logic := 'X'; signal B0_ipd : std_logic := 'X'; signal A0_ipd : std_logic := 'X'; signal F0_out : std_logic := 'X'; signal F1_out : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component lut40028 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; component lut40058 port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; Z: out Std_logic); end component; begin un1_FS_13_i_a2_6: lut40058 port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); InitReady3_0_a2_3: lut40028 port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(D1_ipd, D1, tipd_D1); VitalWireDelay(C1_ipd, C1, tipd_C1); VitalWireDelay(B1_ipd, B1, tipd_B1); VitalWireDelay(A1_ipd, A1, tipd_A1); VitalWireDelay(B0_ipd, B0, tipd_B0); VitalWireDelay(A0_ipd, A0, tipd_A0); END BLOCK; VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, F0_out, F1_out) VARIABLE F0_zd : std_logic := 'X'; VARIABLE F0_GlitchData : VitalGlitchDataType; VARIABLE F1_zd : std_logic := 'X'; VARIABLE F1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; F0_zd := F0_out; F1_zd := F1_out; VitalPathDelay01 ( OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, Paths => (0 => (InputChangeTime => B0_ipd'last_event, PathDelay => tpd_B0_F0, PathCondition => TRUE), 1 => (InputChangeTime => A0_ipd'last_event, PathDelay => tpd_A0_F0, PathCondition => TRUE)), GlitchData => F0_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); VitalPathDelay01 ( OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, Paths => (0 => (InputChangeTime => D1_ipd'last_event, PathDelay => tpd_D1_F1, PathCondition => TRUE), 1 => (InputChangeTime => C1_ipd'last_event, PathDelay => tpd_C1_F1, PathCondition => TRUE), 2 => (InputChangeTime => B1_ipd'last_event, PathDelay => tpd_B1_F1, PathCondition => TRUE), 3 => (InputChangeTime => A1_ipd'last_event, PathDelay => tpd_A1_F1, PathCondition => TRUE)), GlitchData => F1_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity xo2iobuf library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity xo2iobuf is port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; end xo2iobuf; architecture Structure of xo2iobuf is begin INST1: OBW port map (I=>I, T=>T, O=>PAD); end Structure; -- entity RD_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_0_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD0: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; end RD_0_B; architecture Structure of RD_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD0_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_0: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD0_out) VARIABLE RD0_zd : std_logic := 'X'; VARIABLE RD0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD0_zd := RD0_out; VitalPathDelay01Z ( OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD0, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD0, PathCondition => TRUE)), GlitchData => RD0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity mfflsre library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity mfflsre is port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE; end mfflsre; architecture Structure of mfflsre is begin INST01: FD1P3DX generic map (GSR => "DISABLED") port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q); end Structure; -- entity RD_0_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_0_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_0_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_0_MGIOL : ENTITY IS TRUE; end RD_0_MGIOL; architecture Structure of RD_0_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_0: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity xo2iobuf0084 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity xo2iobuf0084 is port (I: in Std_logic; PAD: out Std_logic); ATTRIBUTE Vital_Level0 OF xo2iobuf0084 : ENTITY IS TRUE; end xo2iobuf0084; architecture Structure of xo2iobuf0084 is begin INST5: OB port map (I=>I, O=>PAD); end Structure; -- entity Dout_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_0_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout0: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; end Dout_0_B; architecture Structure of Dout_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout0_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_0: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) VARIABLE Dout0_zd : std_logic := 'X'; VARIABLE Dout0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout0_zd := Dout0_out; VitalPathDelay01 ( OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout0, PathCondition => TRUE)), GlitchData => Dout0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity xo2iobuf0085 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity xo2iobuf0085 is port (Z: out Std_logic; PAD: in Std_logic); ATTRIBUTE Vital_Level0 OF xo2iobuf0085 : ENTITY IS TRUE; end xo2iobuf0085; architecture Structure of xo2iobuf0085 is begin INST1: IBPD port map (I=>PAD, O=>Z); end Structure; -- entity PHI2B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity PHI2B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "PHI2B"; tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_PHI2S : VitalDelayType := 0 ns; tpw_PHI2S_posedge : VitalDelayType := 0 ns; tpw_PHI2S_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; PHI2S: in Std_logic); ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; end PHI2B; architecture Structure of PHI2B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal PHI2S_ipd : std_logic := 'X'; component xo2iobuf0085 port (Z: out Std_logic; PAD: in Std_logic); end component; begin PHI2_pad: xo2iobuf0085 port map (Z=>PADDI_out, PAD=>PHI2S_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); END BLOCK; VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => PHI2S_ipd, TestSignalName => "PHI2S", Period => tperiod_PHI2S, PulseWidthHigh => tpw_PHI2S_posedge, PulseWidthLow => tpw_PHI2S_negedge, PeriodData => periodcheckinfo_PHI2S, Violation => tviol_PHI2S_PHI2S, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, PathDelay => tpd_PHI2S_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity smuxlregsre library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity smuxlregsre is port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE; end smuxlregsre; architecture Structure of smuxlregsre is begin INST01: IFS1P3DX generic map (GSR => "DISABLED") port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q); end Structure; -- entity PHI2_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity PHI2_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "PHI2_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF PHI2_MGIOL : ENTITY IS TRUE; end PHI2_MGIOL; architecture Structure of PHI2_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin PHI2r_0io: smuxlregsre port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_posedge, SetupLow => tsetup_DI_CLK_noedge_posedge, HoldHigh => thold_DI_CLK_noedge_posedge, HoldLow => thold_DI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity xo2iobuf0086 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity xo2iobuf0086 is port (Z: out Std_logic; PAD: in Std_logic); ATTRIBUTE Vital_Level0 OF xo2iobuf0086 : ENTITY IS TRUE; end xo2iobuf0086; architecture Structure of xo2iobuf0086 is begin INST1: IB port map (I=>PAD, O=>Z); end Structure; -- entity UFMSDOB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity UFMSDOB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMSDOB"; tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_UFMSDOS : VitalDelayType := 0 ns; tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; UFMSDOS: in Std_logic); ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; end UFMSDOB; architecture Structure of UFMSDOB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal UFMSDOS_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin UFMSDO_pad: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => UFMSDOS_ipd, TestSignalName => "UFMSDOS", Period => tperiod_UFMSDOS, PulseWidthHigh => tpw_UFMSDOS_posedge, PulseWidthLow => tpw_UFMSDOS_negedge, PeriodData => periodcheckinfo_UFMSDOS, Violation => tviol_UFMSDOS_UFMSDOS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, PathDelay => tpd_UFMSDOS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMSDIB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity UFMSDIB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMSDIB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; UFMSDIS: out Std_logic); ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; end UFMSDIB; architecture Structure of UFMSDIB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal UFMSDIS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin UFMSDI_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>UFMSDIS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, UFMSDIS_out) VARIABLE UFMSDIS_zd : std_logic := 'X'; VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; UFMSDIS_zd := UFMSDIS_out; VitalPathDelay01 ( OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_UFMSDIS, PathCondition => TRUE)), GlitchData => UFMSDIS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMSDI_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity UFMSDI_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMSDI_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF UFMSDI_MGIOL : ENTITY IS TRUE; end UFMSDI_MGIOL; architecture Structure of UFMSDI_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin UFMSDI_r0: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMCLKB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity UFMCLKB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMCLKB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; UFMCLKS: out Std_logic); ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; end UFMCLKB; architecture Structure of UFMCLKB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal UFMCLKS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin UFMCLK_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>UFMCLKS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, UFMCLKS_out) VARIABLE UFMCLKS_zd : std_logic := 'X'; VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; UFMCLKS_zd := UFMCLKS_out; VitalPathDelay01 ( OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_UFMCLKS, PathCondition => TRUE)), GlitchData => UFMCLKS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity UFMCLK_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity UFMCLK_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "UFMCLK_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CE: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF UFMCLK_MGIOL : ENTITY IS TRUE; end UFMCLK_MGIOL; architecture Structure of UFMCLK_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin UFMCLK_0io: mfflsre port map (D0=>OPOS_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CE_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_posedge, SetupLow => tsetup_CE_CLK_noedge_posedge, HoldHigh => thold_CE_CLK_noedge_posedge, HoldLow => thold_CE_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nUFMCSB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nUFMCSB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nUFMCSB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; nUFMCSS: out Std_logic); ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; end nUFMCSB; architecture Structure of nUFMCSB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal nUFMCSS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin nUFMCS_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>nUFMCSS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, nUFMCSS_out) VARIABLE nUFMCSS_zd : std_logic := 'X'; VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nUFMCSS_zd := nUFMCSS_out; VitalPathDelay01 ( OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_nUFMCSS, PathCondition => TRUE)), GlitchData => nUFMCSS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity mfflsre0087 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity mfflsre0087 is port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF mfflsre0087 : ENTITY IS TRUE; end mfflsre0087; architecture Structure of mfflsre0087 is begin INST01: FD1P3BX generic map (GSR => "DISABLED") port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); end Structure; -- entity nUFMCS_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nUFMCS_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nUFMCS_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF nUFMCS_MGIOL : ENTITY IS TRUE; end nUFMCS_MGIOL; architecture Structure of nUFMCS_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre0087 port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin nUFMCS_r1: mfflsre0087 port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RDQMLB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RDQMLB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RDQMLB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RDQMLS: out Std_logic); ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; end RDQMLB; architecture Structure of RDQMLB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RDQMLS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RDQML_pad: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RDQMLS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) VARIABLE RDQMLS_zd : std_logic := 'X'; VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RDQMLS_zd := RDQMLS_out; VitalPathDelay01 ( OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RDQMLS, PathCondition => TRUE)), GlitchData => RDQMLS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RDQMHB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RDQMHB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RDQMHB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RDQMHS: out Std_logic); ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; end RDQMHB; architecture Structure of RDQMHB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RDQMHS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RDQMH_pad: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RDQMHS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) VARIABLE RDQMHS_zd : std_logic := 'X'; VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RDQMHS_zd := RDQMHS_out; VitalPathDelay01 ( OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RDQMHS, PathCondition => TRUE)), GlitchData => RDQMHS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRCASB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRCASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRCASB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; nRCASS: out Std_logic); ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; end nRCASB; architecture Structure of nRCASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal nRCASS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin nRCAS_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>nRCASS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, nRCASS_out) VARIABLE nRCASS_zd : std_logic := 'X'; VARIABLE nRCASS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRCASS_zd := nRCASS_out; VitalPathDelay01 ( OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_nRCASS, PathCondition => TRUE)), GlitchData => nRCASS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRCAS_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRCAS_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRCAS_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF nRCAS_MGIOL : ENTITY IS TRUE; end nRCAS_MGIOL; architecture Structure of nRCAS_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre0087 port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin nRCAS_0io: mfflsre0087 port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRRASB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRRASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRRASB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; nRRASS: out Std_logic); ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; end nRRASB; architecture Structure of nRRASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal nRRASS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin nRRAS_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>nRRASS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, nRRASS_out) VARIABLE nRRASS_zd : std_logic := 'X'; VARIABLE nRRASS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRRASS_zd := nRRASS_out; VitalPathDelay01 ( OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_nRRASS, PathCondition => TRUE)), GlitchData => nRRASS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRRAS_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRRAS_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRRAS_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF nRRAS_MGIOL : ENTITY IS TRUE; end nRRAS_MGIOL; architecture Structure of nRRAS_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre0087 port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin nRRAS_0io: mfflsre0087 port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRWEB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRWEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRWEB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; nRWES: out Std_logic); ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; end nRWEB; architecture Structure of nRWEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal nRWES_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin nRWE_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>nRWES_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, nRWES_out) VARIABLE nRWES_zd : std_logic := 'X'; VARIABLE nRWES_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRWES_zd := nRWES_out; VitalPathDelay01 ( OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_nRWES, PathCondition => TRUE)), GlitchData => nRWES_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRWE_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRWE_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRWE_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF nRWE_MGIOL : ENTITY IS TRUE; end nRWE_MGIOL; architecture Structure of nRWE_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre0087 port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin nRWE_0io: mfflsre0087 port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RCKEB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RCKEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RCKEB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; RCKES: out Std_logic); ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; end RCKEB; architecture Structure of RCKEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal RCKES_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RCKE_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>RCKES_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, RCKES_out) VARIABLE RCKES_zd : std_logic := 'X'; VARIABLE RCKES_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RCKES_zd := RCKES_out; VitalPathDelay01 ( OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RCKES, PathCondition => TRUE)), GlitchData => RCKES_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RCKE_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RCKE_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RCKE_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RCKE_MGIOL : ENTITY IS TRUE; end RCKE_MGIOL; architecture Structure of RCKE_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin RCKE_r2: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RCLKB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RCLKB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RCLKB"; tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_RCLKS : VitalDelayType := 0 ns; tpw_RCLKS_posedge : VitalDelayType := 0 ns; tpw_RCLKS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; RCLKS: in Std_logic); ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; end RCLKB; architecture Structure of RCLKB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal RCLKS_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin RCLK_pad: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>RCLKS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => RCLKS_ipd, TestSignalName => "RCLKS", Period => tperiod_RCLKS, PulseWidthHigh => tpw_RCLKS_posedge, PulseWidthLow => tpw_RCLKS_negedge, PeriodData => periodcheckinfo_RCLKS, Violation => tviol_RCLKS_RCLKS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, PathDelay => tpd_RCLKS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRCSB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRCSB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRCSB"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; nRCSS: out Std_logic); ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; end nRCSB; architecture Structure of nRCSB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal nRCSS_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin nRCS_pad: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>nRCSS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, nRCSS_out) VARIABLE nRCSS_zd : std_logic := 'X'; VARIABLE nRCSS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; nRCSS_zd := nRCSS_out; VitalPathDelay01 ( OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_nRCSS, PathCondition => TRUE)), GlitchData => nRCSS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nRCS_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nRCS_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nRCS_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF nRCS_MGIOL : ENTITY IS TRUE; end nRCS_MGIOL; architecture Structure of nRCS_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre0087 port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin nRCS_0io: mfflsre0087 port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_7_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD7: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; end RD_7_B; architecture Structure of RD_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD7_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_7: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD7_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD7_out) VARIABLE RD7_zd : std_logic := 'X'; VARIABLE RD7_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD7_zd := RD7_out; VitalPathDelay01Z ( OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD7, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD7, PathCondition => TRUE)), GlitchData => RD7_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_7_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_7_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_7_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_7_MGIOL : ENTITY IS TRUE; end RD_7_MGIOL; architecture Structure of RD_7_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_7: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_6_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_6_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD6: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; end RD_6_B; architecture Structure of RD_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD6_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_6: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD6_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD6_out) VARIABLE RD6_zd : std_logic := 'X'; VARIABLE RD6_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD6_zd := RD6_out; VitalPathDelay01Z ( OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD6, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD6, PathCondition => TRUE)), GlitchData => RD6_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_6_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_6_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_6_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_6_MGIOL : ENTITY IS TRUE; end RD_6_MGIOL; architecture Structure of RD_6_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_6: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_5_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_5_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD5: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; end RD_5_B; architecture Structure of RD_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD5_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_5: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD5_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD5_out) VARIABLE RD5_zd : std_logic := 'X'; VARIABLE RD5_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD5_zd := RD5_out; VitalPathDelay01Z ( OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD5, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD5, PathCondition => TRUE)), GlitchData => RD5_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_5_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_5_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_5_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_5_MGIOL : ENTITY IS TRUE; end RD_5_MGIOL; architecture Structure of RD_5_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_5: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_4_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_4_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD4: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; end RD_4_B; architecture Structure of RD_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD4_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_4: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD4_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD4_out) VARIABLE RD4_zd : std_logic := 'X'; VARIABLE RD4_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD4_zd := RD4_out; VitalPathDelay01Z ( OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD4, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD4, PathCondition => TRUE)), GlitchData => RD4_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_4_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_4_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_4_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_4_MGIOL : ENTITY IS TRUE; end RD_4_MGIOL; architecture Structure of RD_4_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_4: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_3_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_3_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD3: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; end RD_3_B; architecture Structure of RD_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD3_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_3: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD3_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD3_out) VARIABLE RD3_zd : std_logic := 'X'; VARIABLE RD3_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD3_zd := RD3_out; VitalPathDelay01Z ( OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD3, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD3, PathCondition => TRUE)), GlitchData => RD3_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_3_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_3_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_3_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_3_MGIOL : ENTITY IS TRUE; end RD_3_MGIOL; architecture Structure of RD_3_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_3: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_2_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_2_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD2: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; end RD_2_B; architecture Structure of RD_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD2_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_2: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD2_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD2_out) VARIABLE RD2_zd : std_logic := 'X'; VARIABLE RD2_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD2_zd := RD2_out; VitalPathDelay01Z ( OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD2, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD2, PathCondition => TRUE)), GlitchData => RD2_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_2_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_2_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_2_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_2_MGIOL : ENTITY IS TRUE; end RD_2_MGIOL; architecture Structure of RD_2_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_2: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_1_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); port (IOLDO: in Std_logic; PADDT: in Std_logic; RD1: out Std_logic); ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; end RD_1_B; architecture Structure of RD_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal PADDT_ipd : std_logic := 'X'; signal RD1_out : std_logic := 'X'; component xo2iobuf port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); end component; begin RD_pad_1: xo2iobuf port map (I=>IOLDO_ipd, T=>PADDT_ipd, PAD=>RD1_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, PADDT_ipd, RD1_out) VARIABLE RD1_zd : std_logic := 'X'; VARIABLE RD1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RD1_zd := RD1_out; VitalPathDelay01Z ( OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RD1, PathCondition => TRUE), 1 => (InputChangeTime => PADDT_ipd'last_event, PathDelay => tpd_PADDT_RD1, PathCondition => TRUE)), GlitchData => RD1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RD_1_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RD_1_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RD_1_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RD_1_MGIOL : ENTITY IS TRUE; end RD_1_MGIOL; architecture Structure of RD_1_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin WRD_0io_1: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_11_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_11_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_11_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; RA11: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; end RA_11_B; architecture Structure of RA_11_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal RA11_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_11: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>RA11_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, RA11_out) VARIABLE RA11_zd : std_logic := 'X'; VARIABLE RA11_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA11_zd := RA11_out; VitalPathDelay01 ( OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RA11, PathCondition => TRUE)), GlitchData => RA11_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_11_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_11_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_11_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RA_11_MGIOL : ENTITY IS TRUE; end RA_11_MGIOL; architecture Structure of RA_11_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin RA11_0io: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_10_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_10_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_10_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; RA10: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; end RA_10_B; architecture Structure of RA_10_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal RA10_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_10: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>RA10_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, RA10_out) VARIABLE RA10_zd : std_logic := 'X'; VARIABLE RA10_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA10_zd := RA10_out; VitalPathDelay01 ( OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RA10, PathCondition => TRUE)), GlitchData => RA10_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity mfflsre0088 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity mfflsre0088 is port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); ATTRIBUTE Vital_Level0 OF mfflsre0088 : ENTITY IS TRUE; end mfflsre0088; architecture Structure of mfflsre0088 is begin INST01: FD1P3JX generic map (GSR => "DISABLED") port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q); end Structure; -- entity RA_10_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_10_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_10_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns; tisd_LSR_CLK : VitalDelayType := 0 ns; tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RA_10_MGIOL : ENTITY IS TRUE; end RA_10_MGIOL; architecture Structure of RA_10_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal LSR_ipd : std_logic := 'X'; signal LSR_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component mfflsre0088 port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin RA10_0io: mfflsre0088 port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(LSR_ipd, LSR, tipd_LSR); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, LSR_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_LSR_CLK : x01 := '0'; VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_posedge, SetupLow => tsetup_OPOS_CLK_noedge_posedge, HoldHigh => thold_OPOS_CLK_noedge_posedge, HoldLow => thold_OPOS_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => LSR_dly, TestSignalName => "LSR", TestDelay => tisd_LSR_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_LSR_CLK_noedge_posedge, SetupLow => tsetup_LSR_CLK_noedge_posedge, HoldHigh => thold_LSR_CLK_noedge_posedge, HoldLow => thold_LSR_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => LSR_CLK_TimingDatash, Violation => tviol_LSR_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_9_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_9_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_9_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA9: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; end RA_9_B; architecture Structure of RA_9_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA9_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_9: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA9_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA9_out) VARIABLE RA9_zd : std_logic := 'X'; VARIABLE RA9_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA9_zd := RA9_out; VitalPathDelay01 ( OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA9, PathCondition => TRUE)), GlitchData => RA9_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_8_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_8_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_8_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA8: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; end RA_8_B; architecture Structure of RA_8_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA8_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_8: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA8_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA8_out) VARIABLE RA8_zd : std_logic := 'X'; VARIABLE RA8_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA8_zd := RA8_out; VitalPathDelay01 ( OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA8, PathCondition => TRUE)), GlitchData => RA8_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_7_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA7: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; end RA_7_B; architecture Structure of RA_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA7_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_7: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA7_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA7_out) VARIABLE RA7_zd : std_logic := 'X'; VARIABLE RA7_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA7_zd := RA7_out; VitalPathDelay01 ( OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA7, PathCondition => TRUE)), GlitchData => RA7_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_6_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_6_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA6: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; end RA_6_B; architecture Structure of RA_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA6_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_6: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA6_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA6_out) VARIABLE RA6_zd : std_logic := 'X'; VARIABLE RA6_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA6_zd := RA6_out; VitalPathDelay01 ( OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA6, PathCondition => TRUE)), GlitchData => RA6_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_5_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_5_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA5: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; end RA_5_B; architecture Structure of RA_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA5_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_5: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA5_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA5_out) VARIABLE RA5_zd : std_logic := 'X'; VARIABLE RA5_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA5_zd := RA5_out; VitalPathDelay01 ( OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA5, PathCondition => TRUE)), GlitchData => RA5_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_4_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_4_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA4: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; end RA_4_B; architecture Structure of RA_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA4_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_4: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA4_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA4_out) VARIABLE RA4_zd : std_logic := 'X'; VARIABLE RA4_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA4_zd := RA4_out; VitalPathDelay01 ( OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA4, PathCondition => TRUE)), GlitchData => RA4_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_3_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_3_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA3: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; end RA_3_B; architecture Structure of RA_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA3_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_3: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA3_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA3_out) VARIABLE RA3_zd : std_logic := 'X'; VARIABLE RA3_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA3_zd := RA3_out; VitalPathDelay01 ( OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA3, PathCondition => TRUE)), GlitchData => RA3_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_2_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_2_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA2: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; end RA_2_B; architecture Structure of RA_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA2_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_2: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA2_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA2_out) VARIABLE RA2_zd : std_logic := 'X'; VARIABLE RA2_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA2_zd := RA2_out; VitalPathDelay01 ( OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA2, PathCondition => TRUE)), GlitchData => RA2_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_1_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA1: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; end RA_1_B; architecture Structure of RA_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA1_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_1: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA1_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA1_out) VARIABLE RA1_zd : std_logic := 'X'; VARIABLE RA1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA1_zd := RA1_out; VitalPathDelay01 ( OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA1, PathCondition => TRUE)), GlitchData => RA1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RA_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RA_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RA_0_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; RA0: out Std_logic); ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; end RA_0_B; architecture Structure of RA_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal RA0_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RA_pad_0: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>RA0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, RA0_out) VARIABLE RA0_zd : std_logic := 'X'; VARIABLE RA0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RA0_zd := RA0_out; VitalPathDelay01 ( OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_RA0, PathCondition => TRUE)), GlitchData => RA0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RBA_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RBA_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RBA_1_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; RBA1: out Std_logic); ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; end RBA_1_B; architecture Structure of RBA_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal RBA1_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RBA_pad_1: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>RBA1_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, RBA1_out) VARIABLE RBA1_zd : std_logic := 'X'; VARIABLE RBA1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RBA1_zd := RBA1_out; VitalPathDelay01 ( OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RBA1, PathCondition => TRUE)), GlitchData => RBA1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RBA_1_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RBA_1_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RBA_1_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RBA_1_MGIOL : ENTITY IS TRUE; end RBA_1_MGIOL; architecture Structure of RBA_1_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin RBA_0io_1: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RBA_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RBA_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RBA_0_B"; tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tpd_IOLDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); port (IOLDO: in Std_logic; RBA0: out Std_logic); ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; end RBA_0_B; architecture Structure of RBA_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_ipd : std_logic := 'X'; signal RBA0_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin RBA_pad_0: xo2iobuf0084 port map (I=>IOLDO_ipd, PAD=>RBA0_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); END BLOCK; VitalBehavior : PROCESS (IOLDO_ipd, RBA0_out) VARIABLE RBA0_zd : std_logic := 'X'; VARIABLE RBA0_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; RBA0_zd := RBA0_out; VitalPathDelay01 ( OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, PathDelay => tpd_IOLDO_RBA0, PathCondition => TRUE)), GlitchData => RBA0_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RBA_0_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RBA_0_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "RBA_0_MGIOL"; tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_OPOS_CLK : VitalDelayType := 0 ns; tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns); port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); ATTRIBUTE Vital_Level0 OF RBA_0_MGIOL : ENTITY IS TRUE; end RBA_0_MGIOL; architecture Structure of RBA_0_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal IOLDO_out : std_logic := 'X'; signal OPOS_ipd : std_logic := 'X'; signal OPOS_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal VCCI: Std_logic; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component mfflsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin RBA_0io_0: mfflsre port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out); DRIVEVCC: vcc port map (PWR1=>VCCI); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly) VARIABLE IOLDO_zd : std_logic := 'X'; VARIABLE IOLDO_GlitchData : VitalGlitchDataType; VARIABLE tviol_OPOS_CLK : x01 := '0'; VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => OPOS_dly, TestSignalName => "OPOS", TestDelay => tisd_OPOS_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_OPOS_CLK_noedge_negedge, SetupLow => tsetup_OPOS_CLK_noedge_negedge, HoldHigh => thold_OPOS_CLK_noedge_negedge, HoldLow => thold_OPOS_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => OPOS_CLK_TimingDatash, Violation => tviol_OPOS_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; IOLDO_zd := IOLDO_out; VitalPathDelay01 ( OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_IOLDO, PathCondition => TRUE)), GlitchData => IOLDO_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity xo2iobuf0089 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity xo2iobuf0089 is port (I: in Std_logic; PAD: out Std_logic); ATTRIBUTE Vital_Level0 OF xo2iobuf0089 : ENTITY IS TRUE; end xo2iobuf0089; architecture Structure of xo2iobuf0089 is begin INST5: OB port map (I=>I, O=>PAD); end Structure; -- entity LEDB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity LEDB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "LEDB"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; LEDS: out Std_logic); ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; end LEDB; architecture Structure of LEDB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal LEDS_out : std_logic := 'X'; component xo2iobuf0089 port (I: in Std_logic; PAD: out Std_logic); end component; begin LED_pad: xo2iobuf0089 port map (I=>PADDO_ipd, PAD=>LEDS_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) VARIABLE LEDS_zd : std_logic := 'X'; VARIABLE LEDS_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; LEDS_zd := LEDS_out; VitalPathDelay01 ( OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_LEDS, PathCondition => TRUE)), GlitchData => LEDS_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity xo2iobuf0090 library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity xo2iobuf0090 is port (Z: out Std_logic; PAD: in Std_logic); ATTRIBUTE Vital_Level0 OF xo2iobuf0090 : ENTITY IS TRUE; end xo2iobuf0090; architecture Structure of xo2iobuf0090 is begin INST1: IBPU port map (I=>PAD, O=>Z); end Structure; -- entity nFWEB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nFWEB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nFWEB"; tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_nFWES : VitalDelayType := 0 ns; tpw_nFWES_posedge : VitalDelayType := 0 ns; tpw_nFWES_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; nFWES: in Std_logic); ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; end nFWEB; architecture Structure of nFWEB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal nFWES_ipd : std_logic := 'X'; component xo2iobuf0090 port (Z: out Std_logic; PAD: in Std_logic); end component; begin nFWE_pad: xo2iobuf0090 port map (Z=>PADDI_out, PAD=>nFWES_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); END BLOCK; VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_nFWES_nFWES : x01 := '0'; VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => nFWES_ipd, TestSignalName => "nFWES", Period => tperiod_nFWES, PulseWidthHigh => tpw_nFWES_posedge, PulseWidthLow => tpw_nFWES_negedge, PeriodData => periodcheckinfo_nFWES, Violation => tviol_nFWES_nFWES, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, PathDelay => tpd_nFWES_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nCRASB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nCRASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nCRASB"; tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_nCRASS : VitalDelayType := 0 ns; tpw_nCRASS_posedge : VitalDelayType := 0 ns; tpw_nCRASS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; nCRASS: in Std_logic); ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; end nCRASB; architecture Structure of nCRASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal nCRASS_ipd : std_logic := 'X'; component xo2iobuf0090 port (Z: out Std_logic; PAD: in Std_logic); end component; begin nCRAS_pad: xo2iobuf0090 port map (Z=>PADDI_out, PAD=>nCRASS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => nCRASS_ipd, TestSignalName => "nCRASS", Period => tperiod_nCRASS, PulseWidthHigh => tpw_nCRASS_posedge, PulseWidthLow => tpw_nCRASS_negedge, PeriodData => periodcheckinfo_nCRASS, Violation => tviol_nCRASS_nCRASS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, PathDelay => tpd_nCRASS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity nCCASB library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity nCCASB is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "nCCASB"; tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_nCCASS : VitalDelayType := 0 ns; tpw_nCCASS_posedge : VitalDelayType := 0 ns; tpw_nCCASS_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; nCCASS: in Std_logic); ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; end nCCASB; architecture Structure of nCCASB is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal nCCASS_ipd : std_logic := 'X'; component xo2iobuf0090 port (Z: out Std_logic; PAD: in Std_logic); end component; begin nCCAS_pad: xo2iobuf0090 port map (Z=>PADDI_out, PAD=>nCCASS_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); END BLOCK; VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => nCCASS_ipd, TestSignalName => "nCCASS", Period => tperiod_nCCASS, PulseWidthHigh => tpw_nCCASS_posedge, PulseWidthLow => tpw_nCCASS_negedge, PeriodData => periodcheckinfo_nCCASS, Violation => tviol_nCCASS_nCCASS, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, PathDelay => tpd_nCCASS_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_7_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout7: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; end Dout_7_B; architecture Structure of Dout_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout7_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_7: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout7_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) VARIABLE Dout7_zd : std_logic := 'X'; VARIABLE Dout7_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout7_zd := Dout7_out; VitalPathDelay01 ( OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout7, PathCondition => TRUE)), GlitchData => Dout7_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_6_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_6_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout6: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; end Dout_6_B; architecture Structure of Dout_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout6_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_6: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout6_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) VARIABLE Dout6_zd : std_logic := 'X'; VARIABLE Dout6_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout6_zd := Dout6_out; VitalPathDelay01 ( OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout6, PathCondition => TRUE)), GlitchData => Dout6_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_5_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_5_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout5: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; end Dout_5_B; architecture Structure of Dout_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout5_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_5: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout5_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) VARIABLE Dout5_zd : std_logic := 'X'; VARIABLE Dout5_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout5_zd := Dout5_out; VitalPathDelay01 ( OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout5, PathCondition => TRUE)), GlitchData => Dout5_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_4_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_4_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout4: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; end Dout_4_B; architecture Structure of Dout_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout4_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_4: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout4_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) VARIABLE Dout4_zd : std_logic := 'X'; VARIABLE Dout4_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout4_zd := Dout4_out; VitalPathDelay01 ( OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout4, PathCondition => TRUE)), GlitchData => Dout4_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_3_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_3_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout3: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; end Dout_3_B; architecture Structure of Dout_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout3_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_3: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout3_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) VARIABLE Dout3_zd : std_logic := 'X'; VARIABLE Dout3_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout3_zd := Dout3_out; VitalPathDelay01 ( OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout3, PathCondition => TRUE)), GlitchData => Dout3_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_2_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_2_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout2: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; end Dout_2_B; architecture Structure of Dout_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout2_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_2: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout2_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) VARIABLE Dout2_zd : std_logic := 'X'; VARIABLE Dout2_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout2_zd := Dout2_out; VitalPathDelay01 ( OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout2, PathCondition => TRUE)), GlitchData => Dout2_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Dout_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Dout_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Dout_1_B"; tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); port (PADDO: in Std_logic; Dout1: out Std_logic); ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; end Dout_1_B; architecture Structure of Dout_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDO_ipd : std_logic := 'X'; signal Dout1_out : std_logic := 'X'; component xo2iobuf0084 port (I: in Std_logic; PAD: out Std_logic); end component; begin Dout_pad_1: xo2iobuf0084 port map (I=>PADDO_ipd, PAD=>Dout1_out); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); END BLOCK; VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) VARIABLE Dout1_zd : std_logic := 'X'; VARIABLE Dout1_GlitchData : VitalGlitchDataType; BEGIN IF (TimingChecksOn) THEN END IF; Dout1_zd := Dout1_out; VitalPathDelay01 ( OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, PathDelay => tpd_PADDO_Dout1, PathCondition => TRUE)), GlitchData => Dout1_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_7_B"; tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din7 : VitalDelayType := 0 ns; tpw_Din7_posedge : VitalDelayType := 0 ns; tpw_Din7_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din7: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; end Din_7_B; architecture Structure of Din_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din7_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_7: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din7_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din7_ipd, Din7, tipd_Din7); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din7_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din7_Din7 : x01 := '0'; VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din7_ipd, TestSignalName => "Din7", Period => tperiod_Din7, PulseWidthHigh => tpw_Din7_posedge, PulseWidthLow => tpw_Din7_negedge, PeriodData => periodcheckinfo_Din7, Violation => tviol_Din7_Din7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din7_ipd'last_event, PathDelay => tpd_Din7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_7_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_7_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_7_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_7_MGIOL : ENTITY IS TRUE; end Din_7_MGIOL; architecture Structure of Din_7_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin Bank_0io_7: smuxlregsre port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_posedge, SetupLow => tsetup_DI_CLK_noedge_posedge, HoldHigh => thold_DI_CLK_noedge_posedge, HoldLow => thold_DI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_6_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_6_B"; tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din6 : VitalDelayType := 0 ns; tpw_Din6_posedge : VitalDelayType := 0 ns; tpw_Din6_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din6: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; end Din_6_B; architecture Structure of Din_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din6_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_6: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din6_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din6_ipd, Din6, tipd_Din6); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din6_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din6_Din6 : x01 := '0'; VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din6_ipd, TestSignalName => "Din6", Period => tperiod_Din6, PulseWidthHigh => tpw_Din6_posedge, PulseWidthLow => tpw_Din6_negedge, PeriodData => periodcheckinfo_Din6, Violation => tviol_Din6_Din6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din6_ipd'last_event, PathDelay => tpd_Din6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_6_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_6_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_6_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_6_MGIOL : ENTITY IS TRUE; end Din_6_MGIOL; architecture Structure of Din_6_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin Bank_0io_6: smuxlregsre port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_posedge, SetupLow => tsetup_DI_CLK_noedge_posedge, HoldHigh => thold_DI_CLK_noedge_posedge, HoldLow => thold_DI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_5_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_5_B"; tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din5 : VitalDelayType := 0 ns; tpw_Din5_posedge : VitalDelayType := 0 ns; tpw_Din5_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din5: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; end Din_5_B; architecture Structure of Din_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din5_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_5: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din5_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din5_ipd, Din5, tipd_Din5); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din5_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din5_Din5 : x01 := '0'; VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din5_ipd, TestSignalName => "Din5", Period => tperiod_Din5, PulseWidthHigh => tpw_Din5_posedge, PulseWidthLow => tpw_Din5_negedge, PeriodData => periodcheckinfo_Din5, Violation => tviol_Din5_Din5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din5_ipd'last_event, PathDelay => tpd_Din5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_5_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_5_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_5_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_5_MGIOL : ENTITY IS TRUE; end Din_5_MGIOL; architecture Structure of Din_5_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin Bank_0io_5: smuxlregsre port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_posedge, SetupLow => tsetup_DI_CLK_noedge_posedge, HoldHigh => thold_DI_CLK_noedge_posedge, HoldLow => thold_DI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_4_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_4_B"; tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din4 : VitalDelayType := 0 ns; tpw_Din4_posedge : VitalDelayType := 0 ns; tpw_Din4_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din4: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; end Din_4_B; architecture Structure of Din_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din4_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_4: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din4_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din4_ipd, Din4, tipd_Din4); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din4_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din4_Din4 : x01 := '0'; VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din4_ipd, TestSignalName => "Din4", Period => tperiod_Din4, PulseWidthHigh => tpw_Din4_posedge, PulseWidthLow => tpw_Din4_negedge, PeriodData => periodcheckinfo_Din4, Violation => tviol_Din4_Din4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din4_ipd'last_event, PathDelay => tpd_Din4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_4_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_4_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_4_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_4_MGIOL : ENTITY IS TRUE; end Din_4_MGIOL; architecture Structure of Din_4_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin Bank_0io_4: smuxlregsre port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_posedge, SetupLow => tsetup_DI_CLK_noedge_posedge, HoldHigh => thold_DI_CLK_noedge_posedge, HoldLow => thold_DI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_3_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_3_B"; tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din3 : VitalDelayType := 0 ns; tpw_Din3_posedge : VitalDelayType := 0 ns; tpw_Din3_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din3: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; end Din_3_B; architecture Structure of Din_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din3_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_3: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din3_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din3_ipd, Din3, tipd_Din3); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din3_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din3_Din3 : x01 := '0'; VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din3_ipd, TestSignalName => "Din3", Period => tperiod_Din3, PulseWidthHigh => tpw_Din3_posedge, PulseWidthLow => tpw_Din3_negedge, PeriodData => periodcheckinfo_Din3, Violation => tviol_Din3_Din3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din3_ipd'last_event, PathDelay => tpd_Din3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_3_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_3_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_3_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_3_MGIOL : ENTITY IS TRUE; end Din_3_MGIOL; architecture Structure of Din_3_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal VCCI: Std_logic; signal GNDI: Std_logic; component vcc port (PWR1: out Std_logic); end component; component gnd port (PWR0: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin Bank_0io_3: smuxlregsre port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out); DRIVEVCC: vcc port map (PWR1=>VCCI); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_posedge, SetupLow => tsetup_DI_CLK_noedge_posedge, HoldHigh => thold_DI_CLK_noedge_posedge, HoldLow => thold_DI_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_2_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_2_B"; tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din2 : VitalDelayType := 0 ns; tpw_Din2_posedge : VitalDelayType := 0 ns; tpw_Din2_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din2: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; end Din_2_B; architecture Structure of Din_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din2_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_2: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din2_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din2_ipd, Din2, tipd_Din2); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din2_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din2_Din2 : x01 := '0'; VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din2_ipd, TestSignalName => "Din2", Period => tperiod_Din2, PulseWidthHigh => tpw_Din2_posedge, PulseWidthLow => tpw_Din2_negedge, PeriodData => periodcheckinfo_Din2, Violation => tviol_Din2_Din2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din2_ipd'last_event, PathDelay => tpd_Din2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_2_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_2_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_2_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_2_MGIOL : ENTITY IS TRUE; end Din_2_MGIOL; architecture Structure of Din_2_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin CmdUFMCS: smuxlregsre port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_negedge, SetupLow => tsetup_DI_CLK_noedge_negedge, HoldHigh => thold_DI_CLK_noedge_negedge, HoldLow => thold_DI_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_1_B"; tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din1 : VitalDelayType := 0 ns; tpw_Din1_posedge : VitalDelayType := 0 ns; tpw_Din1_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din1: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; end Din_1_B; architecture Structure of Din_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din1_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_1: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din1_ipd, Din1, tipd_Din1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din1_Din1 : x01 := '0'; VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din1_ipd, TestSignalName => "Din1", Period => tperiod_Din1, PulseWidthHigh => tpw_Din1_posedge, PulseWidthLow => tpw_Din1_negedge, PeriodData => periodcheckinfo_Din1, Violation => tviol_Din1_Din1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din1_ipd'last_event, PathDelay => tpd_Din1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_1_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_1_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_1_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_1_MGIOL : ENTITY IS TRUE; end Din_1_MGIOL; architecture Structure of Din_1_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin CmdUFMCLK: smuxlregsre port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_negedge, SetupLow => tsetup_DI_CLK_noedge_negedge, HoldHigh => thold_DI_CLK_noedge_negedge, HoldLow => thold_DI_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_0_B"; tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_Din0 : VitalDelayType := 0 ns; tpw_Din0_posedge : VitalDelayType := 0 ns; tpw_Din0_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; Din0: in Std_logic); ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; end Din_0_B; architecture Structure of Din_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal Din0_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin Din_pad_0: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>Din0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(Din0_ipd, Din0, tipd_Din0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, Din0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_Din0_Din0 : x01 := '0'; VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => Din0_ipd, TestSignalName => "Din0", Period => tperiod_Din0, PulseWidthHigh => tpw_Din0_posedge, PulseWidthLow => tpw_Din0_negedge, PeriodData => periodcheckinfo_Din0, Violation => tviol_Din0_Din0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => Din0_ipd'last_event, PathDelay => tpd_Din0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity Din_0_MGIOL library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity Din_0_MGIOL is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "Din_0_MGIOL"; tipd_DI : VitalDelayType01 := (0 ns, 0 ns); tipd_CE : VitalDelayType01 := (0 ns, 0 ns); tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns); tperiod_CLK : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; ticd_CLK : VitalDelayType := 0 ns; tisd_DI_CLK : VitalDelayType := 0 ns; tsetup_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_DI_CLK_noedge_negedge : VitalDelayType := 0 ns; tisd_CE_CLK : VitalDelayType := 0 ns; tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; INP: out Std_logic); ATTRIBUTE Vital_Level0 OF Din_0_MGIOL : ENTITY IS TRUE; end Din_0_MGIOL; architecture Structure of Din_0_MGIOL is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal DI_ipd : std_logic := 'X'; signal DI_dly : std_logic := 'X'; signal CE_ipd : std_logic := 'X'; signal CE_dly : std_logic := 'X'; signal CLK_ipd : std_logic := 'X'; signal CLK_dly : std_logic := 'X'; signal INP_out : std_logic := 'X'; signal CLK_NOTIN: Std_logic; signal GNDI: Std_logic; component gnd port (PWR0: out Std_logic); end component; component inverter port (I: in Std_logic; Z: out Std_logic); end component; component smuxlregsre port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; Q: out Std_logic); end component; begin CmdUFMSDI: smuxlregsre port map (D0=>DI_dly, SP=>CE_dly, CK=>CLK_NOTIN, LSR=>GNDI, Q=>INP_out); CLK_INVERTERIN: inverter port map (I=>CLK_dly, Z=>CLK_NOTIN); DRIVEGND: gnd port map (PWR0=>GNDI); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(DI_ipd, DI, tipd_DI); VitalWireDelay(CE_ipd, CE, tipd_CE); VitalWireDelay(CLK_ipd, CLK, tipd_CLK); END BLOCK; -- Setup and Hold DELAYs SignalDelay : BLOCK BEGIN VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; VitalBehavior : PROCESS (DI_dly, CE_dly, CLK_dly, INP_out) VARIABLE INP_zd : std_logic := 'X'; VARIABLE INP_GlitchData : VitalGlitchDataType; VARIABLE tviol_DI_CLK : x01 := '0'; VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CE_CLK : x01 := '0'; VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; VARIABLE tviol_CLK_CLK : x01 := '0'; VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DI_dly, TestSignalName => "DI", TestDelay => tisd_DI_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_DI_CLK_noedge_negedge, SetupLow => tsetup_DI_CLK_noedge_negedge, HoldHigh => thold_DI_CLK_noedge_negedge, HoldLow => thold_DI_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => DI_CLK_TimingDatash, Violation => tviol_DI_CLK, MsgSeverity => warning); VitalSetupHoldCheck ( TestSignal => CE_dly, TestSignalName => "CE", TestDelay => tisd_CE_CLK, RefSignal => CLK_dly, RefSignalName => "CLK", RefDelay => ticd_CLK, SetupHigh => tsetup_CE_CLK_noedge_negedge, SetupLow => tsetup_CE_CLK_noedge_negedge, HoldHigh => thold_CE_CLK_noedge_negedge, HoldLow => thold_CE_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, TimingData => CE_CLK_TimingDatash, Violation => tviol_CE_CLK, MsgSeverity => warning); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => periodcheckinfo_CLK, Violation => tviol_CLK_CLK, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; INP_zd := INP_out; VitalPathDelay01 ( OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd, Paths => (0 => (InputChangeTime => CLK_dly'last_event, PathDelay => tpd_CLK_INP, PathCondition => TRUE)), GlitchData => INP_GlitchData, Mode => ondetect, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity CROW_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity CROW_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "CROW_1_B"; tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_CROW1 : VitalDelayType := 0 ns; tpw_CROW1_posedge : VitalDelayType := 0 ns; tpw_CROW1_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; CROW1: in Std_logic); ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; end CROW_1_B; architecture Structure of CROW_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal CROW1_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin CROW_pad_1: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>CROW1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_CROW1_CROW1 : x01 := '0'; VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => CROW1_ipd, TestSignalName => "CROW1", Period => tperiod_CROW1, PulseWidthHigh => tpw_CROW1_posedge, PulseWidthLow => tpw_CROW1_negedge, PeriodData => periodcheckinfo_CROW1, Violation => tviol_CROW1_CROW1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, PathDelay => tpd_CROW1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity CROW_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity CROW_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "CROW_0_B"; tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_CROW0 : VitalDelayType := 0 ns; tpw_CROW0_posedge : VitalDelayType := 0 ns; tpw_CROW0_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; CROW0: in Std_logic); ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; end CROW_0_B; architecture Structure of CROW_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal CROW0_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin CROW_pad_0: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>CROW0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_CROW0_CROW0 : x01 := '0'; VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => CROW0_ipd, TestSignalName => "CROW0", Period => tperiod_CROW0, PulseWidthHigh => tpw_CROW0_posedge, PulseWidthLow => tpw_CROW0_negedge, PeriodData => periodcheckinfo_CROW0, Violation => tviol_CROW0_CROW0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, PathDelay => tpd_CROW0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_9_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_9_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_9_B"; tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin9 : VitalDelayType := 0 ns; tpw_MAin9_posedge : VitalDelayType := 0 ns; tpw_MAin9_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin9: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; end MAin_9_B; architecture Structure of MAin_9_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin9_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_9: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin9_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin9_MAin9 : x01 := '0'; VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin9_ipd, TestSignalName => "MAin9", Period => tperiod_MAin9, PulseWidthHigh => tpw_MAin9_posedge, PulseWidthLow => tpw_MAin9_negedge, PeriodData => periodcheckinfo_MAin9, Violation => tviol_MAin9_MAin9, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, PathDelay => tpd_MAin9_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_8_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_8_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_8_B"; tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin8 : VitalDelayType := 0 ns; tpw_MAin8_posedge : VitalDelayType := 0 ns; tpw_MAin8_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin8: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; end MAin_8_B; architecture Structure of MAin_8_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin8_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_8: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin8_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin8_MAin8 : x01 := '0'; VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin8_ipd, TestSignalName => "MAin8", Period => tperiod_MAin8, PulseWidthHigh => tpw_MAin8_posedge, PulseWidthLow => tpw_MAin8_negedge, PeriodData => periodcheckinfo_MAin8, Violation => tviol_MAin8_MAin8, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, PathDelay => tpd_MAin8_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_7_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_7_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_7_B"; tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin7 : VitalDelayType := 0 ns; tpw_MAin7_posedge : VitalDelayType := 0 ns; tpw_MAin7_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin7: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; end MAin_7_B; architecture Structure of MAin_7_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin7_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_7: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin7_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin7_MAin7 : x01 := '0'; VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin7_ipd, TestSignalName => "MAin7", Period => tperiod_MAin7, PulseWidthHigh => tpw_MAin7_posedge, PulseWidthLow => tpw_MAin7_negedge, PeriodData => periodcheckinfo_MAin7, Violation => tviol_MAin7_MAin7, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, PathDelay => tpd_MAin7_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_6_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_6_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_6_B"; tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin6 : VitalDelayType := 0 ns; tpw_MAin6_posedge : VitalDelayType := 0 ns; tpw_MAin6_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin6: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; end MAin_6_B; architecture Structure of MAin_6_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin6_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_6: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin6_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin6_MAin6 : x01 := '0'; VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin6_ipd, TestSignalName => "MAin6", Period => tperiod_MAin6, PulseWidthHigh => tpw_MAin6_posedge, PulseWidthLow => tpw_MAin6_negedge, PeriodData => periodcheckinfo_MAin6, Violation => tviol_MAin6_MAin6, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, PathDelay => tpd_MAin6_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_5_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_5_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_5_B"; tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin5 : VitalDelayType := 0 ns; tpw_MAin5_posedge : VitalDelayType := 0 ns; tpw_MAin5_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin5: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; end MAin_5_B; architecture Structure of MAin_5_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin5_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_5: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin5_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin5_MAin5 : x01 := '0'; VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin5_ipd, TestSignalName => "MAin5", Period => tperiod_MAin5, PulseWidthHigh => tpw_MAin5_posedge, PulseWidthLow => tpw_MAin5_negedge, PeriodData => periodcheckinfo_MAin5, Violation => tviol_MAin5_MAin5, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, PathDelay => tpd_MAin5_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_4_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_4_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_4_B"; tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin4 : VitalDelayType := 0 ns; tpw_MAin4_posedge : VitalDelayType := 0 ns; tpw_MAin4_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin4: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; end MAin_4_B; architecture Structure of MAin_4_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin4_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_4: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin4_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin4_MAin4 : x01 := '0'; VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin4_ipd, TestSignalName => "MAin4", Period => tperiod_MAin4, PulseWidthHigh => tpw_MAin4_posedge, PulseWidthLow => tpw_MAin4_negedge, PeriodData => periodcheckinfo_MAin4, Violation => tviol_MAin4_MAin4, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, PathDelay => tpd_MAin4_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_3_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_3_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_3_B"; tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin3 : VitalDelayType := 0 ns; tpw_MAin3_posedge : VitalDelayType := 0 ns; tpw_MAin3_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin3: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; end MAin_3_B; architecture Structure of MAin_3_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin3_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_3: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin3_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin3_MAin3 : x01 := '0'; VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin3_ipd, TestSignalName => "MAin3", Period => tperiod_MAin3, PulseWidthHigh => tpw_MAin3_posedge, PulseWidthLow => tpw_MAin3_negedge, PeriodData => periodcheckinfo_MAin3, Violation => tviol_MAin3_MAin3, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, PathDelay => tpd_MAin3_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_2_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_2_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_2_B"; tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin2 : VitalDelayType := 0 ns; tpw_MAin2_posedge : VitalDelayType := 0 ns; tpw_MAin2_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin2: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; end MAin_2_B; architecture Structure of MAin_2_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin2_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_2: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin2_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin2_MAin2 : x01 := '0'; VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin2_ipd, TestSignalName => "MAin2", Period => tperiod_MAin2, PulseWidthHigh => tpw_MAin2_posedge, PulseWidthLow => tpw_MAin2_negedge, PeriodData => periodcheckinfo_MAin2, Violation => tviol_MAin2_MAin2, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, PathDelay => tpd_MAin2_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_1_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_1_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_1_B"; tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin1 : VitalDelayType := 0 ns; tpw_MAin1_posedge : VitalDelayType := 0 ns; tpw_MAin1_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin1: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; end MAin_1_B; architecture Structure of MAin_1_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin1_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_1: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin1_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin1_MAin1 : x01 := '0'; VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin1_ipd, TestSignalName => "MAin1", Period => tperiod_MAin1, PulseWidthHigh => tpw_MAin1_posedge, PulseWidthLow => tpw_MAin1_negedge, PeriodData => periodcheckinfo_MAin1, Violation => tviol_MAin1_MAin1, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, PathDelay => tpd_MAin1_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity MAin_0_B library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity MAin_0_B is -- miscellaneous vital GENERICs GENERIC ( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "MAin_0_B"; tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); tperiod_MAin0 : VitalDelayType := 0 ns; tpw_MAin0_posedge : VitalDelayType := 0 ns; tpw_MAin0_negedge : VitalDelayType := 0 ns); port (PADDI: out Std_logic; MAin0: in Std_logic); ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; end MAin_0_B; architecture Structure of MAin_0_B is ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; signal PADDI_out : std_logic := 'X'; signal MAin0_ipd : std_logic := 'X'; component xo2iobuf0086 port (Z: out Std_logic; PAD: in Std_logic); end component; begin MAin_pad_0: xo2iobuf0086 port map (Z=>PADDI_out, PAD=>MAin0_ipd); -- INPUT PATH DELAYs WireDelay : BLOCK BEGIN VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); END BLOCK; VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) VARIABLE PADDI_zd : std_logic := 'X'; VARIABLE PADDI_GlitchData : VitalGlitchDataType; VARIABLE tviol_MAin0_MAin0 : x01 := '0'; VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; BEGIN IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => MAin0_ipd, TestSignalName => "MAin0", Period => tperiod_MAin0, PulseWidthHigh => tpw_MAin0_posedge, PulseWidthLow => tpw_MAin0_negedge, PeriodData => periodcheckinfo_MAin0, Violation => tviol_MAin0_MAin0, MsgOn => MsgOn, XOn => XOn, HeaderMsg => InstancePath, CheckEnabled => TRUE, MsgSeverity => warning); END IF; PADDI_zd := PADDI_out; VitalPathDelay01 ( OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, PathDelay => tpd_MAin0_PADDI, PathCondition => TRUE)), GlitchData => PADDI_GlitchData, Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); END PROCESS; end Structure; -- entity RAM2GS library IEEE, vital2000, MACHXO2; use IEEE.STD_LOGIC_1164.all; use vital2000.vital_timing.all; use MACHXO2.COMPONENTS.ALL; entity RAM2GS is port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); CROW: in Std_logic_vector (1 downto 0); Din: in Std_logic_vector (7 downto 0); Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; RBA: out Std_logic_vector (1 downto 0); RA: out Std_logic_vector (11 downto 0); RD: out Std_logic_vector (7 downto 0); nRCS: out Std_logic; RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; UFMSDI: out Std_logic; UFMSDO: in Std_logic); end RAM2GS; architecture Structure of RAM2GS is signal FS_0: Std_logic; signal FS_s_0: Std_logic; signal RCLK_c: Std_logic; signal FS_cry_0: Std_logic; signal FS_17: Std_logic; signal FS_s_17: Std_logic; signal FS_cry_16: Std_logic; signal FS_16: Std_logic; signal FS_15: Std_logic; signal FS_s_16: Std_logic; signal FS_s_15: Std_logic; signal FS_cry_14: Std_logic; signal FS_14: Std_logic; signal FS_13: Std_logic; signal FS_s_14: Std_logic; signal FS_s_13: Std_logic; signal FS_cry_12: Std_logic; signal FS_12: Std_logic; signal FS_11: Std_logic; signal FS_s_12: Std_logic; signal FS_s_11: Std_logic; signal FS_cry_10: Std_logic; signal FS_10: Std_logic; signal FS_9: Std_logic; signal FS_s_10: Std_logic; signal FS_s_9: Std_logic; signal FS_cry_8: Std_logic; signal FS_8: Std_logic; signal FS_7: Std_logic; signal FS_s_8: Std_logic; signal FS_s_7: Std_logic; signal FS_cry_6: Std_logic; signal FS_6: Std_logic; signal FS_5: Std_logic; signal FS_s_6: Std_logic; signal FS_s_5: Std_logic; signal FS_cry_4: Std_logic; signal FS_4: Std_logic; signal FS_3: Std_logic; signal FS_s_4: Std_logic; signal FS_s_3: Std_logic; signal FS_cry_2: Std_logic; signal FS_2: Std_logic; signal FS_1: Std_logic; signal FS_s_2: Std_logic; signal FS_s_1: Std_logic; signal CmdEnable17_5: Std_logic; signal CmdEnable17_4: Std_logic; signal ADWR: Std_logic; signal CmdEnable16: Std_logic; signal CmdEnable17: Std_logic; signal un1_ADWR: Std_logic; signal ADSubmitted: Std_logic; signal ADSubmitted_r: Std_logic; signal PHI2_c: Std_logic; signal un1_Bank_1: Std_logic; signal MAin_c_2: Std_logic; signal CmdEnable16_5: Std_logic; signal C1WR_3: Std_logic; signal C1Submitted: Std_logic; signal C1Submitted_s: Std_logic; signal nFWE_c: Std_logic; signal nCCAS_c: Std_logic; signal nCCAS_c_i: Std_logic; signal CASr: Std_logic; signal RD_1_i: Std_logic; signal CASr2: Std_logic; signal S_1: Std_logic; signal RASr2: Std_logic; signal IS_3: Std_logic; signal CO0: Std_logic; signal N_166_i: Std_logic; signal Ready_0_sqmuxa_0_a3_2: Std_logic; signal CmdEnable: Std_logic; signal un1_CMDWR: Std_logic; signal CmdEnable_s: Std_logic; signal N_36: Std_logic; signal Din_c_5: Std_logic; signal Din_c_1: Std_logic; signal N_94: Std_logic; signal N_60: Std_logic; signal N_59: Std_logic; signal LEDEN: Std_logic; signal N_14_i: Std_logic; signal XOR8MEG18: Std_logic; signal CmdLEDEN: Std_logic; signal Din_c_3: Std_logic; signal CmdSubmitted: Std_logic; signal CmdSubmitted_1_sqmuxa: Std_logic; signal N_412_0: Std_logic; signal CmdUFMCLK_1_sqmuxa: Std_logic; signal n8MEGEN: Std_logic; signal Cmdn8MEGEN_4_u_i_0: Std_logic; signal N_12_i: Std_logic; signal Cmdn8MEGEN: Std_logic; signal MAin_c_1: Std_logic; signal ADWR_6: Std_logic; signal ADWR_3: Std_logic; signal nFWE_c_i: Std_logic; signal nCRAS_c: Std_logic; signal FWEr: Std_logic; signal CMDWR_2: Std_logic; signal Ready: Std_logic; signal N_151: Std_logic; signal IS_0: Std_logic; signal N_60_i_i: Std_logic; signal RA10s_i: Std_logic; signal IS_2: Std_logic; signal IS_1: Std_logic; signal N_180_i: Std_logic; signal IS_n1_0_x2: Std_logic; signal N_48_i: Std_logic; signal N_58_i_i: Std_logic; signal N_137_5: Std_logic; signal N_137_3: Std_logic; signal InitReady: Std_logic; signal InitReady3: Std_logic; signal N_413_0: Std_logic; signal N_74_i: Std_logic; signal N_28: Std_logic; signal CBR: Std_logic; signal nCRAS_c_i_0: Std_logic; signal RASr: Std_logic; signal LED_c: Std_logic; signal S_0_i_o2_1: Std_logic; signal RCKEEN_8_u_1_0: Std_logic; signal RCKEEN_8_u_0_0: Std_logic; signal RCKEEN_8: Std_logic; signal RCKEEN: Std_logic; signal Ready_fast: Std_logic; signal CROW_c_1: Std_logic; signal RASr3: Std_logic; signal RCKE_2: Std_logic; signal RCKE_c: Std_logic; signal RBAd_0_1: Std_logic; signal N_158: Std_logic; signal N_414_0: Std_logic; signal Ready_0_sqmuxa: Std_logic; signal N_415_0: Std_logic; signal MAin_c_0: Std_logic; signal RowAd_0_1: Std_logic; signal RowAd_0_0: Std_logic; signal RowA_0: Std_logic; signal RowA_1: Std_logic; signal MAin_c_3: Std_logic; signal RowAd_0_3: Std_logic; signal RowAd_0_2: Std_logic; signal RowA_2: Std_logic; signal RowA_3: Std_logic; signal MAin_c_5: Std_logic; signal MAin_c_4: Std_logic; signal RowAd_0_5: Std_logic; signal RowAd_0_4: Std_logic; signal RowA_4: Std_logic; signal RowA_5: Std_logic; signal MAin_c_7: Std_logic; signal MAin_c_6: Std_logic; signal RowAd_0_7: Std_logic; signal RowAd_0_6: Std_logic; signal RowA_6: Std_logic; signal RowA_7: Std_logic; signal MAin_c_9: Std_logic; signal MAin_c_8: Std_logic; signal RowAd_0_9: Std_logic; signal RowAd_0_8: Std_logic; signal RowA_8: Std_logic; signal RowA_9: Std_logic; signal nRCAS_0_sqmuxa_1: Std_logic; signal CmdUFMSDI: Std_logic; signal N_145: Std_logic; signal UFMSDI_ens2_i_a0: Std_logic; signal nUFMCS15: Std_logic; signal UFMSDI_c: Std_logic; signal UFMSDI_RNO: Std_logic; signal N_141_i: Std_logic; signal Din_c_7: Std_logic; signal Din_c_6: Std_logic; signal Din_c_4: Std_logic; signal un1_Din_3: Std_logic; signal XOR8MEG_3_u_1: Std_logic; signal XOR8MEG: Std_logic; signal Din_c_0: Std_logic; signal XOR8MEG_3: Std_logic; signal Bank_4: Std_logic; signal Bank_3: Std_logic; signal Bank_1: Std_logic; signal Bank_0: Std_logic; signal UFMSDO_c: Std_logic; signal N_131: Std_logic; signal N_26: Std_logic; signal un1_Bank_1_4: Std_logic; signal CASr3: Std_logic; signal N_168: Std_logic; signal nRowColSel_0_0: Std_logic; signal nRRAS_0_sqmuxa: Std_logic; signal nRowColSel: Std_logic; signal UFMCLK_r_i_a2_2_2: Std_logic; signal CmdUFMCS: Std_logic; signal nUFMCS_c: Std_logic; signal nUFMCS_s_0_m4_yy: Std_logic; signal nUFMCS_s_0_N_5_i: Std_logic; signal N_129: Std_logic; signal d_m3_0_a2_0: Std_logic; signal CmdUFMCLK: Std_logic; signal i1_i: Std_logic; signal N_50: Std_logic; signal N_154: Std_logic; signal un1_nRCAS_6_sqmuxa_i_0: Std_logic; signal N_45: Std_logic; signal N_146_i_1: Std_logic; signal N_27_i_1: Std_logic; signal N_146_i: Std_logic; signal nRRAS_5_u_i_0: Std_logic; signal N_24_i: Std_logic; signal nRWE_s_i_a3_1_0: Std_logic; signal nRWE_s_i_tz_0: Std_logic; signal PHI2r3: Std_logic; signal PHI2r2: Std_logic; signal un1_PHI2r3_0: Std_logic; signal N_140: Std_logic; signal un1_FS_14_i_a2_0_1: Std_logic; signal N_139_8: Std_logic; signal N_139_6: Std_logic; signal N_139: Std_logic; signal un1_FS_13_i_a2_1: Std_logic; signal UFMSDI_ens2_i_a2_4_2: Std_logic; signal N_34: Std_logic; signal ADWR_2: Std_logic; signal N_24: Std_logic; signal N_27_i_sn: Std_logic; signal N_153: Std_logic; signal C1WR_1: Std_logic; signal UFMSDI_ens2_i_o2_0_3: Std_logic; signal PHI2r: Std_logic; signal i2_i: Std_logic; signal N_27_i: Std_logic; signal Din_c_2: Std_logic; signal CmdEnable16_4: Std_logic; signal CmdEnable16_3: Std_logic; signal Bank_2: Std_logic; signal Bank_7: Std_logic; signal un1_Bank_1_3: Std_logic; signal Bank_6: Std_logic; signal Bank_5: Std_logic; signal nRWE_0io_RNO_1: Std_logic; signal nRWE_0io_RNO_0: Std_logic; signal N_147_i: Std_logic; signal RA_c_9: Std_logic; signal RDQML_c: Std_logic; signal RA_c_8: Std_logic; signal RDQMH_c: Std_logic; signal RA_c_0: Std_logic; signal RA_c_7: Std_logic; signal RA_c_1: Std_logic; signal RA_c_6: Std_logic; signal RA_c_2: Std_logic; signal RA_c_5: Std_logic; signal RA_c_3: Std_logic; signal RA_c_4: Std_logic; signal CROW_c_0: Std_logic; signal RA11d_0: Std_logic; signal RBAd_0_0: Std_logic; signal WRD_0: Std_logic; signal UFMSDI_c_n0: Std_logic; signal UFMCLK_c: Std_logic; signal nUFMCS_c_n1: Std_logic; signal nRCAS_c: Std_logic; signal nRRAS_c: Std_logic; signal nRWE_c: Std_logic; signal RCKE_c_n2: Std_logic; signal nRCS_c: Std_logic; signal WRD_7: Std_logic; signal WRD_6: Std_logic; signal WRD_5: Std_logic; signal WRD_4: Std_logic; signal WRD_3: Std_logic; signal WRD_2: Std_logic; signal WRD_1: Std_logic; signal RA_c_11: Std_logic; signal RA_c_10: Std_logic; signal RBA_c_1: Std_logic; signal RBA_c_0: Std_logic; signal VCCI: Std_logic; component SLICE_0 port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_1 port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); end component; component SLICE_2 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_3 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_4 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_5 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_6 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_7 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_8 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_9 port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); end component; component SLICE_10 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_13 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_14 port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_17 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_18 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); end component; component SLICE_19 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_20 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_21 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_22 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_23 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_24 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_25 port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); end component; component SLICE_26 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_27 port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); end component; component SLICE_29 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_31 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_32 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_33 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_34 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_35 port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_36 port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_37 port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_38 port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_39 port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_40 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_41 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); end component; component SLICE_42 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_43 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_44 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_45 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_46 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_47 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_48 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_49 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_50 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_51 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_52 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_53 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_54 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_55 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_56 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_57 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_58 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_59 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_60 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_61 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_62 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_63 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_64 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_65 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); end component; component SLICE_66 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_67 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_68 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_69 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_70 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_71 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_72 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_73 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_74 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); end component; component SLICE_75 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_76 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_77 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_78 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_79 port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_80 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_81 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_82 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_83 port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_84 port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component SLICE_85 port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); end component; component RD_0_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD0: out Std_logic); end component; component RD_0_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component Dout_0_B port (PADDO: in Std_logic; Dout0: out Std_logic); end component; component PHI2B port (PADDI: out Std_logic; PHI2S: in Std_logic); end component; component PHI2_MGIOL port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component UFMSDOB port (PADDI: out Std_logic; UFMSDOS: in Std_logic); end component; component UFMSDIB port (IOLDO: in Std_logic; UFMSDIS: out Std_logic); end component; component UFMSDI_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component UFMCLKB port (IOLDO: in Std_logic; UFMCLKS: out Std_logic); end component; component UFMCLK_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CE: in Std_logic; CLK: in Std_logic); end component; component nUFMCSB port (IOLDO: in Std_logic; nUFMCSS: out Std_logic); end component; component nUFMCS_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RDQMLB port (PADDO: in Std_logic; RDQMLS: out Std_logic); end component; component RDQMHB port (PADDO: in Std_logic; RDQMHS: out Std_logic); end component; component nRCASB port (IOLDO: in Std_logic; nRCASS: out Std_logic); end component; component nRCAS_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component nRRASB port (IOLDO: in Std_logic; nRRASS: out Std_logic); end component; component nRRAS_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component nRWEB port (IOLDO: in Std_logic; nRWES: out Std_logic); end component; component nRWE_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RCKEB port (IOLDO: in Std_logic; RCKES: out Std_logic); end component; component RCKE_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RCLKB port (PADDI: out Std_logic; RCLKS: in Std_logic); end component; component nRCSB port (IOLDO: in Std_logic; nRCSS: out Std_logic); end component; component nRCS_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_7_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD7: out Std_logic); end component; component RD_7_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_6_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD6: out Std_logic); end component; component RD_6_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_5_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD5: out Std_logic); end component; component RD_5_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_4_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD4: out Std_logic); end component; component RD_4_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_3_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD3: out Std_logic); end component; component RD_3_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_2_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD2: out Std_logic); end component; component RD_2_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RD_1_B port (IOLDO: in Std_logic; PADDT: in Std_logic; RD1: out Std_logic); end component; component RD_1_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RA_11_B port (IOLDO: in Std_logic; RA11: out Std_logic); end component; component RA_11_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RA_10_B port (IOLDO: in Std_logic; RA10: out Std_logic); end component; component RA_10_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic; CLK: in Std_logic); end component; component RA_9_B port (PADDO: in Std_logic; RA9: out Std_logic); end component; component RA_8_B port (PADDO: in Std_logic; RA8: out Std_logic); end component; component RA_7_B port (PADDO: in Std_logic; RA7: out Std_logic); end component; component RA_6_B port (PADDO: in Std_logic; RA6: out Std_logic); end component; component RA_5_B port (PADDO: in Std_logic; RA5: out Std_logic); end component; component RA_4_B port (PADDO: in Std_logic; RA4: out Std_logic); end component; component RA_3_B port (PADDO: in Std_logic; RA3: out Std_logic); end component; component RA_2_B port (PADDO: in Std_logic; RA2: out Std_logic); end component; component RA_1_B port (PADDO: in Std_logic; RA1: out Std_logic); end component; component RA_0_B port (PADDO: in Std_logic; RA0: out Std_logic); end component; component RBA_1_B port (IOLDO: in Std_logic; RBA1: out Std_logic); end component; component RBA_1_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component RBA_0_B port (IOLDO: in Std_logic; RBA0: out Std_logic); end component; component RBA_0_MGIOL port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic); end component; component LEDB port (PADDO: in Std_logic; LEDS: out Std_logic); end component; component nFWEB port (PADDI: out Std_logic; nFWES: in Std_logic); end component; component nCRASB port (PADDI: out Std_logic; nCRASS: in Std_logic); end component; component nCCASB port (PADDI: out Std_logic; nCCASS: in Std_logic); end component; component Dout_7_B port (PADDO: in Std_logic; Dout7: out Std_logic); end component; component Dout_6_B port (PADDO: in Std_logic; Dout6: out Std_logic); end component; component Dout_5_B port (PADDO: in Std_logic; Dout5: out Std_logic); end component; component Dout_4_B port (PADDO: in Std_logic; Dout4: out Std_logic); end component; component Dout_3_B port (PADDO: in Std_logic; Dout3: out Std_logic); end component; component Dout_2_B port (PADDO: in Std_logic; Dout2: out Std_logic); end component; component Dout_1_B port (PADDO: in Std_logic; Dout1: out Std_logic); end component; component Din_7_B port (PADDI: out Std_logic; Din7: in Std_logic); end component; component Din_7_MGIOL port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_6_B port (PADDI: out Std_logic; Din6: in Std_logic); end component; component Din_6_MGIOL port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_5_B port (PADDI: out Std_logic; Din5: in Std_logic); end component; component Din_5_MGIOL port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_4_B port (PADDI: out Std_logic; Din4: in Std_logic); end component; component Din_4_MGIOL port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_3_B port (PADDI: out Std_logic; Din3: in Std_logic); end component; component Din_3_MGIOL port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_2_B port (PADDI: out Std_logic; Din2: in Std_logic); end component; component Din_2_MGIOL port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_1_B port (PADDI: out Std_logic; Din1: in Std_logic); end component; component Din_1_MGIOL port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component Din_0_B port (PADDI: out Std_logic; Din0: in Std_logic); end component; component Din_0_MGIOL port (DI: in Std_logic; CE: in Std_logic; CLK: in Std_logic; INP: out Std_logic); end component; component CROW_1_B port (PADDI: out Std_logic; CROW1: in Std_logic); end component; component CROW_0_B port (PADDI: out Std_logic; CROW0: in Std_logic); end component; component MAin_9_B port (PADDI: out Std_logic; MAin9: in Std_logic); end component; component MAin_8_B port (PADDI: out Std_logic; MAin8: in Std_logic); end component; component MAin_7_B port (PADDI: out Std_logic; MAin7: in Std_logic); end component; component MAin_6_B port (PADDI: out Std_logic; MAin6: in Std_logic); end component; component MAin_5_B port (PADDI: out Std_logic; MAin5: in Std_logic); end component; component MAin_4_B port (PADDI: out Std_logic; MAin4: in Std_logic); end component; component MAin_3_B port (PADDI: out Std_logic; MAin3: in Std_logic); end component; component MAin_2_B port (PADDI: out Std_logic; MAin2: in Std_logic); end component; component MAin_1_B port (PADDI: out Std_logic; MAin1: in Std_logic); end component; component MAin_0_B port (PADDI: out Std_logic; MAin0: in Std_logic); end component; begin SLICE_0I: SLICE_0 port map (A1=>FS_0, DI1=>FS_s_0, CLK=>RCLK_c, F1=>FS_s_0, Q1=>FS_0, FCO=>FS_cry_0); SLICE_1I: SLICE_1 port map (A0=>FS_17, DI0=>FS_s_17, CLK=>RCLK_c, FCI=>FS_cry_16, F0=>FS_s_17, Q0=>FS_17); SLICE_2I: SLICE_2 port map (A1=>FS_16, A0=>FS_15, DI1=>FS_s_16, DI0=>FS_s_15, CLK=>RCLK_c, FCI=>FS_cry_14, F0=>FS_s_15, Q0=>FS_15, F1=>FS_s_16, Q1=>FS_16, FCO=>FS_cry_16); SLICE_3I: SLICE_3 port map (A1=>FS_14, A0=>FS_13, DI1=>FS_s_14, DI0=>FS_s_13, CLK=>RCLK_c, FCI=>FS_cry_12, F0=>FS_s_13, Q0=>FS_13, F1=>FS_s_14, Q1=>FS_14, FCO=>FS_cry_14); SLICE_4I: SLICE_4 port map (A1=>FS_12, A0=>FS_11, DI1=>FS_s_12, DI0=>FS_s_11, CLK=>RCLK_c, FCI=>FS_cry_10, F0=>FS_s_11, Q0=>FS_11, F1=>FS_s_12, Q1=>FS_12, FCO=>FS_cry_12); SLICE_5I: SLICE_5 port map (A1=>FS_10, A0=>FS_9, DI1=>FS_s_10, DI0=>FS_s_9, CLK=>RCLK_c, FCI=>FS_cry_8, F0=>FS_s_9, Q0=>FS_9, F1=>FS_s_10, Q1=>FS_10, FCO=>FS_cry_10); SLICE_6I: SLICE_6 port map (A1=>FS_8, A0=>FS_7, DI1=>FS_s_8, DI0=>FS_s_7, CLK=>RCLK_c, FCI=>FS_cry_6, F0=>FS_s_7, Q0=>FS_7, F1=>FS_s_8, Q1=>FS_8, FCO=>FS_cry_8); SLICE_7I: SLICE_7 port map (A1=>FS_6, A0=>FS_5, DI1=>FS_s_6, DI0=>FS_s_5, CLK=>RCLK_c, FCI=>FS_cry_4, F0=>FS_s_5, Q0=>FS_5, F1=>FS_s_6, Q1=>FS_6, FCO=>FS_cry_6); SLICE_8I: SLICE_8 port map (A1=>FS_4, A0=>FS_3, DI1=>FS_s_4, DI0=>FS_s_3, CLK=>RCLK_c, FCI=>FS_cry_2, F0=>FS_s_3, Q0=>FS_3, F1=>FS_s_4, Q1=>FS_4, FCO=>FS_cry_4); SLICE_9I: SLICE_9 port map (A1=>FS_2, A0=>FS_1, DI1=>FS_s_2, DI0=>FS_s_1, CLK=>RCLK_c, FCI=>FS_cry_0, F0=>FS_s_1, Q0=>FS_1, F1=>FS_s_2, Q1=>FS_2, FCO=>FS_cry_2); SLICE_10I: SLICE_10 port map (C1=>CmdEnable17_5, B1=>CmdEnable17_4, A1=>ADWR, D0=>CmdEnable16, C0=>CmdEnable17, B0=>un1_ADWR, A0=>ADSubmitted, DI0=>ADSubmitted_r, CLK=>PHI2_c, F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17); SLICE_13I: SLICE_13 port map (D1=>un1_Bank_1, C1=>MAin_c_2, B1=>CmdEnable16_5, A1=>C1WR_3, C0=>CmdEnable16, B0=>un1_ADWR, A0=>C1Submitted, DI0=>C1Submitted_s, CLK=>PHI2_c, F0=>C1Submitted_s, Q0=>C1Submitted, F1=>CmdEnable16); SLICE_14I: SLICE_14 port map (B1=>nFWE_c, A1=>nCCAS_c, A0=>nCCAS_c, DI0=>nCCAS_c_i, M1=>CASr, CLK=>RCLK_c, F0=>nCCAS_c_i, Q0=>CASr, F1=>RD_1_i, Q1=>CASr2); SLICE_17I: SLICE_17 port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0, DI0=>N_166_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_166_i, Q0=>CO0, F1=>Ready_0_sqmuxa_0_a3_2); SLICE_18I: SLICE_18 port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR, B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s, M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable); SLICE_19I: SLICE_19 port map (C1=>N_36, B1=>Din_c_5, A1=>Din_c_1, D0=>N_94, C0=>N_60, B0=>N_59, A0=>LEDEN, DI0=>N_14_i, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_14_i, Q0=>CmdLEDEN, F1=>N_60); SLICE_20I: SLICE_20 port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>XOR8MEG18, B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_412_0, CLK=>PHI2_c, F0=>N_412_0, Q0=>CmdSubmitted, F1=>CmdUFMCLK_1_sqmuxa); SLICE_21I: SLICE_21 port map (C1=>N_36, B1=>Din_c_5, A1=>Din_c_3, C0=>n8MEGEN, B0=>N_94, A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_12_i, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_12_i, Q0=>Cmdn8MEGEN, F1=>N_94); SLICE_22I: SLICE_22 port map (D1=>nFWE_c, C1=>MAin_c_1, B1=>ADWR_6, A1=>ADWR_3, A0=>nFWE_c, DI0=>nFWE_c_i, CLK=>nCRAS_c, F0=>nFWE_c_i, Q0=>FWEr, F1=>CMDWR_2); SLICE_23I: SLICE_23 port map (D1=>Ready, C1=>N_151, B1=>IS_3, A1=>IS_0, C0=>Ready, B0=>N_151, A0=>IS_0, DI0=>N_60_i_i, CLK=>RCLK_c, F0=>N_60_i_i, Q0=>IS_0, F1=>RA10s_i); SLICE_24I: SLICE_24 port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0, DI1=>N_180_i, DI0=>IS_n1_0_x2, CE=>N_48_i, CLK=>RCLK_c, F0=>IS_n1_0_x2, Q0=>IS_1, F1=>N_180_i, Q1=>IS_2); SLICE_25I: SLICE_25 port map (D0=>IS_0, C0=>IS_1, B0=>IS_2, A0=>IS_3, DI0=>N_58_i_i, CE=>N_48_i, CLK=>RCLK_c, F0=>N_58_i_i, Q0=>IS_3); SLICE_26I: SLICE_26 port map (D1=>N_137_5, C1=>N_137_3, B1=>FS_16, A1=>FS_10, B0=>InitReady, A0=>InitReady3, DI0=>N_413_0, CLK=>RCLK_c, F0=>N_413_0, Q0=>InitReady, F1=>InitReady3); SLICE_27I: SLICE_27 port map (B0=>InitReady, A0=>CmdLEDEN, DI0=>N_74_i, CE=>N_28, CLK=>RCLK_c, F0=>N_74_i, Q0=>LEDEN); SLICE_29I: SLICE_29 port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, A0=>nCRAS_c, DI0=>nCRAS_c_i_0, M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_i_0, Q0=>RASr, F1=>LED_c, Q1=>RASr2); SLICE_31I: SLICE_31 port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready, D0=>Ready, C0=>RCKEEN_8_u_1_0, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_0_0); SLICE_32I: SLICE_32 port map (B1=>Ready_fast, A1=>CROW_c_1, D0=>RCKEEN, C0=>RASr3, B0=>RASr2, A0=>RASr, DI0=>RCKE_2, M1=>RASr2, CLK=>RCLK_c, F0=>RCKE_2, Q0=>RCKE_c, F1=>RBAd_0_1, Q1=>RASr3); SLICE_33I: SLICE_33 port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>InitReady, C0=>N_158, B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, DI0=>N_414_0, CLK=>RCLK_c, F0=>N_414_0, Q0=>Ready, F1=>N_158); SLICE_34I: SLICE_34 port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_158, A1=>InitReady, B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_415_0, CLK=>RCLK_c, F0=>N_415_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa); SLICE_35I: SLICE_35 port map (B1=>Ready_fast, A1=>MAin_c_1, B0=>Ready_fast, A0=>MAin_c_0, DI1=>RowAd_0_1, DI0=>RowAd_0_0, CLK=>nCRAS_c, F0=>RowAd_0_0, Q0=>RowA_0, F1=>RowAd_0_1, Q1=>RowA_1); SLICE_36I: SLICE_36 port map (B1=>Ready_fast, A1=>MAin_c_3, B0=>Ready_fast, A0=>MAin_c_2, DI1=>RowAd_0_3, DI0=>RowAd_0_2, CLK=>nCRAS_c, F0=>RowAd_0_2, Q0=>RowA_2, F1=>RowAd_0_3, Q1=>RowA_3); SLICE_37I: SLICE_37 port map (B1=>Ready_fast, A1=>MAin_c_5, B0=>Ready_fast, A0=>MAin_c_4, DI1=>RowAd_0_5, DI0=>RowAd_0_4, CLK=>nCRAS_c, F0=>RowAd_0_4, Q0=>RowA_4, F1=>RowAd_0_5, Q1=>RowA_5); SLICE_38I: SLICE_38 port map (B1=>Ready_fast, A1=>MAin_c_7, B0=>Ready_fast, A0=>MAin_c_6, DI1=>RowAd_0_7, DI0=>RowAd_0_6, CLK=>nCRAS_c, F0=>RowAd_0_6, Q0=>RowA_6, F1=>RowAd_0_7, Q1=>RowA_7); SLICE_39I: SLICE_39 port map (B1=>Ready_fast, A1=>MAin_c_9, B0=>Ready_fast, A0=>MAin_c_8, DI1=>RowAd_0_9, DI0=>RowAd_0_8, CLK=>nCRAS_c, F0=>RowAd_0_8, Q0=>RowA_8, F1=>RowAd_0_9, Q1=>RowA_9); SLICE_40I: SLICE_40 port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR, B0=>S_1, A0=>CO0, DI0=>S_0_i_o2_1, LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1, F1=>nRCAS_0_sqmuxa_1); SLICE_41I: SLICE_41 port map (D1=>CmdUFMSDI, C1=>N_145, B1=>UFMSDI_ens2_i_a0, A1=>nUFMCS15, B0=>nUFMCS15, A0=>UFMSDI_c, DI0=>UFMSDI_RNO, M0=>N_141_i, CLK=>RCLK_c, OFX0=>UFMSDI_RNO, Q0=>UFMSDI_c); SLICE_42I: SLICE_42 port map (D1=>Din_c_7, C1=>Din_c_6, B1=>Din_c_5, A1=>Din_c_4, D0=>un1_Din_3, C0=>XOR8MEG_3_u_1, B0=>XOR8MEG, A0=>Din_c_0, DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3, Q0=>XOR8MEG, F1=>un1_Din_3); SLICE_43I: SLICE_43 port map (D1=>Bank_4, C1=>Bank_3, B1=>Bank_1, A1=>Bank_0, C0=>UFMSDO_c, B0=>InitReady, A0=>Cmdn8MEGEN, DI0=>N_131, CE=>N_26, CLK=>RCLK_c, F0=>N_131, Q0=>n8MEGEN, F1=>un1_Bank_1_4); SLICE_44I: SLICE_44 port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready, B0=>N_168, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa, CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_168); SLICE_45I: SLICE_45 port map (D1=>UFMCLK_r_i_a2_2_2, C1=>nUFMCS15, B1=>InitReady, A1=>CmdUFMCS, D0=>nUFMCS_c, C0=>nUFMCS_s_0_m4_yy, B0=>nUFMCS15, A0=>N_141_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c, F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS_s_0_m4_yy); SLICE_46I: SLICE_46 port map (D1=>un1_Bank_1, C1=>MAin_c_2, B1=>C1WR_3, A1=>ADWR, D0=>un1_ADWR, C0=>un1_Bank_1, B0=>MAin_c_2, A0=>CMDWR_2, F0=>un1_CMDWR, F1=>un1_ADWR); SLICE_47I: SLICE_47 port map (D1=>N_129, C1=>InitReady, B1=>FS_11, A1=>FS_10, D0=>d_m3_0_a2_0, C0=>nUFMCS15, B0=>InitReady, A0=>CmdUFMCLK, F0=>i1_i, F1=>nUFMCS15); SLICE_48I: SLICE_48 port map (D1=>N_137_5, C1=>N_137_3, B1=>InitReady, A1=>FS_16, C0=>UFMCLK_r_i_a2_2_2, B0=>N_50, A0=>InitReady, F0=>d_m3_0_a2_0, F1=>UFMCLK_r_i_a2_2_2); SLICE_49I: SLICE_49 port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, D0=>S_1, C0=>Ready, B0=>N_154, A0=>N_151, F0=>un1_nRCAS_6_sqmuxa_i_0, F1=>N_151); SLICE_50I: SLICE_50 port map (D1=>Din_c_0, C1=>Din_c_5, B1=>Cmdn8MEGEN, A1=>N_45, C0=>N_36, B0=>Din_c_5, A0=>Din_c_3, F0=>N_45, F1=>Cmdn8MEGEN_4_u_i_0); SLICE_51I: SLICE_51 port map (C1=>S_1, B1=>un1_nRCAS_6_sqmuxa_i_0, A1=>CBR, D0=>S_1, C0=>N_146_i_1, B0=>nRCAS_0_sqmuxa_1, A0=>N_27_i_1, F0=>N_146_i, F1=>N_146_i_1); SLICE_52I: SLICE_52 port map (C1=>IS_1, B1=>IS_2, A1=>IS_3, D0=>IS_0, C0=>N_151, B0=>N_154, A0=>nRRAS_5_u_i_0, F0=>N_24_i, F1=>N_154); SLICE_53I: SLICE_53 port map (D1=>nRWE_s_i_a3_1_0, C1=>nRRAS_0_sqmuxa, B1=>RCKE_c, A1=>RASr2, C0=>CO0, B0=>S_1, A0=>Ready, F0=>nRRAS_0_sqmuxa, F1=>nRWE_s_i_tz_0); SLICE_54I: SLICE_54 port map (B1=>PHI2r3, A1=>PHI2r2, D0=>un1_PHI2r3_0, C0=>N_140, B0=>InitReady, A0=>CmdSubmitted, F0=>N_28, F1=>un1_PHI2r3_0); SLICE_55I: SLICE_55 port map (C1=>un1_FS_14_i_a2_0_1, B1=>N_139_8, A1=>N_139_6, D0=>un1_PHI2r3_0, C0=>N_139, B0=>InitReady, A0=>CmdSubmitted, F0=>N_26, F1=>N_139); SLICE_56I: SLICE_56 port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, C0=>un1_FS_13_i_a2_1, B0=>N_139_8, A0=>N_139_6, F0=>N_140, F1=>un1_FS_13_i_a2_1); SLICE_57I: SLICE_57 port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>XOR8MEG18, D0=>un1_Bank_1, C0=>MAin_c_2, B0=>CmdEnable, A0=>CMDWR_2, F0=>XOR8MEG18, F1=>CmdSubmitted_1_sqmuxa); SLICE_58I: SLICE_58 port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, D0=>UFMSDI_ens2_i_a2_4_2, C0=>N_129, B0=>N_34, A0=>InitReady, F0=>UFMSDI_ens2_i_a0, F1=>UFMSDI_ens2_i_a2_4_2); SLICE_59I: SLICE_59 port map (C1=>N_129, B1=>InitReady, A1=>FS_8, D0=>N_145, C0=>FS_11, B0=>FS_9, A0=>FS_4, F0=>N_139_8, F1=>N_145); SLICE_60I: SLICE_60 port map (B1=>MAin_c_0, A1=>MAin_c_7, D0=>un1_Bank_1, C0=>MAin_c_1, B0=>ADWR_3, A0=>ADWR_2, F0=>ADWR, F1=>ADWR_3); SLICE_61I: SLICE_61 port map (C1=>S_1, B1=>N_24, A1=>CBR, D0=>nRRAS_5_u_i_0, C0=>N_154, B0=>N_151, A0=>IS_0, F0=>N_24, F1=>N_27_i_sn); SLICE_62I: SLICE_62 port map (B1=>IS_2, A1=>IS_1, D0=>Ready, C0=>N_153, B0=>N_151, A0=>IS_0, F0=>nRWE_s_i_a3_1_0, F1=>N_153); SLICE_63I: SLICE_63 port map (B1=>nFWE_c, A1=>MAin_c_7, D0=>MAin_c_1, C0=>MAin_c_0, B0=>C1WR_1, A0=>ADWR_6, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>C1WR_3, Q0=>Bank_0, F1=>C1WR_1, Q1=>Bank_1); SLICE_64I: SLICE_64 port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_15, D0=>N_129, C0=>FS_11, B0=>FS_4, A0=>FS_1, F0=>N_50, F1=>N_129); SLICE_65I: SLICE_65 port map (B1=>nUFMCS15, A1=>N_141_i, D0=>PHI2r3, C0=>PHI2r2, B0=>InitReady, A0=>CmdSubmitted, M1=>PHI2r2, M0=>PHI2r, CLK=>RCLK_c, F0=>N_141_i, Q0=>PHI2r2, F1=>i2_i, Q1=>PHI2r3); SLICE_66I: SLICE_66 port map (D1=>Ready, C1=>N_27_i_sn, B1=>N_27_i_1, A1=>N_24_i, D0=>FWEr, C0=>CO0, B0=>CASr3, A0=>CASr2, F0=>N_27_i_1, F1=>N_27_i); SLICE_67I: SLICE_67 port map (D1=>MAin_c_6, C1=>MAin_c_5, B1=>MAin_c_4, A1=>MAin_c_3, C0=>nFWE_c, B0=>MAin_c_2, A0=>ADWR_6, F0=>ADWR_2, F1=>ADWR_6); SLICE_68I: SLICE_68 port map (B1=>Din_c_5, A1=>Din_c_0, D0=>Din_c_6, C0=>Din_c_2, B0=>CmdEnable16_4, A0=>CmdEnable16_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>CmdEnable16_5, Q0=>Bank_2, F1=>CmdEnable16_3); SLICE_69I: SLICE_69 port map (B1=>Bank_7, A1=>Bank_2, D0=>un1_Bank_1_4, C0=>un1_Bank_1_3, B0=>Bank_6, A0=>Bank_5, F0=>un1_Bank_1, F1=>un1_Bank_1_3); SLICE_70I: SLICE_70 port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_36, A1=>CmdLEDEN, C0=>Din_c_7, B0=>Din_c_6, A0=>Din_c_4, F0=>N_36, F1=>N_59); SLICE_71I: SLICE_71 port map (C1=>CO0, B1=>CASr3, A1=>CASr2, D0=>nRWE_s_i_tz_0, C0=>nRWE_0io_RNO_1, B0=>nRWE_0io_RNO_0, A0=>nRCAS_0_sqmuxa_1, F0=>N_147_i, F1=>nRWE_0io_RNO_0); SLICE_72I: SLICE_72 port map (D1=>FS_17, C1=>FS_14, B1=>FS_13, A1=>FS_12, D0=>FS_17, C0=>FS_15, B0=>FS_13, A0=>FS_12, F0=>N_137_5, F1=>UFMSDI_ens2_i_o2_0_3); SLICE_73I: SLICE_73 port map (D1=>Din_c_7, C1=>Din_c_4, B1=>Din_c_3, A1=>Din_c_1, D0=>Din_c_7, C0=>Din_c_5, B0=>Din_c_4, A0=>Din_c_1, M0=>CASr2, CLK=>RCLK_c, F0=>CmdEnable17_5, Q0=>CASr3, F1=>CmdEnable16_4); SLICE_74I: SLICE_74 port map (D1=>LEDEN, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_1, D0=>Din_c_6, C0=>Din_c_3, B0=>Din_c_2, A0=>Din_c_0, M0=>nCCAS_c_i, CLK=>nCRAS_c, F0=>CmdEnable17_4, Q0=>CBR, F1=>XOR8MEG_3_u_1); SLICE_75I: SLICE_75 port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9, A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c); SLICE_76I: SLICE_76 port map (D1=>S_1, C1=>Ready, B1=>FWEr, A1=>CBR, D0=>S_1, C0=>FWEr, B0=>CO0, A0=>CASr2, F0=>RCKEEN_8_u_1_0, F1=>nRWE_0io_RNO_1); SLICE_77I: SLICE_77 port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, B0=>Ready, A0=>N_151, F0=>N_48_i, F1=>nRRAS_5_u_i_0); SLICE_78I: SLICE_78 port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, C0=>FS_9, B0=>FS_7, A0=>FS_5, F0=>N_34, F1=>un1_FS_14_i_a2_0_1); SLICE_79I: SLICE_79 port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8, A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c); SLICE_80I: SLICE_80 port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel, B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>RA_c_7); SLICE_81I: SLICE_81 port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel, B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_6); SLICE_82I: SLICE_82 port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel, B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_5); SLICE_83I: SLICE_83 port map (C1=>nRowColSel, B1=>RowA_4, A1=>MAin_c_4, C0=>nRowColSel, B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_4); SLICE_84I: SLICE_84 port map (B1=>Ready_fast, A1=>CROW_c_0, D0=>n8MEGEN, C0=>XOR8MEG, B0=>Ready_fast, A0=>Din_c_6, F0=>RA11d_0, F1=>RBAd_0_0); SLICE_85I: SLICE_85 port map (D1=>FS_10, C1=>FS_7, B1=>FS_6, A1=>FS_1, B0=>FS_14, A0=>FS_11, F0=>N_137_3, F1=>N_139_6); RD_0_I: RD_0_B port map (IOLDO=>WRD_0, PADDT=>RD_1_i, RD0=>RD(0)); RD_0_MGIOLI: RD_0_MGIOL port map (IOLDO=>WRD_0, OPOS=>Din_c_0, CLK=>nCCAS_c); Dout_0_I: Dout_0_B port map (PADDO=>MAin_c_3, Dout0=>Dout(0)); PHI2I: PHI2B port map (PADDI=>PHI2_c, PHI2S=>PHI2); PHI2_MGIOLI: PHI2_MGIOL port map (DI=>PHI2_c, CLK=>RCLK_c, INP=>PHI2r); UFMSDOI: UFMSDOB port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); UFMSDII: UFMSDIB port map (IOLDO=>UFMSDI_c_n0, UFMSDIS=>UFMSDI); UFMSDI_MGIOLI: UFMSDI_MGIOL port map (IOLDO=>UFMSDI_c_n0, OPOS=>UFMSDI_RNO, CLK=>RCLK_c); UFMCLKI: UFMCLKB port map (IOLDO=>UFMCLK_c, UFMCLKS=>UFMCLK); UFMCLK_MGIOLI: UFMCLK_MGIOL port map (IOLDO=>UFMCLK_c, OPOS=>i1_i, CE=>i2_i, CLK=>RCLK_c); nUFMCSI: nUFMCSB port map (IOLDO=>nUFMCS_c_n1, nUFMCSS=>nUFMCS); nUFMCS_MGIOLI: nUFMCS_MGIOL port map (IOLDO=>nUFMCS_c_n1, OPOS=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c); RDQMLI: RDQMLB port map (PADDO=>RDQML_c, RDQMLS=>RDQML); RDQMHI: RDQMHB port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); nRCASI: nRCASB port map (IOLDO=>nRCAS_c, nRCASS=>nRCAS); nRCAS_MGIOLI: nRCAS_MGIOL port map (IOLDO=>nRCAS_c, OPOS=>N_146_i, CLK=>RCLK_c); nRRASI: nRRASB port map (IOLDO=>nRRAS_c, nRRASS=>nRRAS); nRRAS_MGIOLI: nRRAS_MGIOL port map (IOLDO=>nRRAS_c, OPOS=>N_24_i, CLK=>RCLK_c); nRWEI: nRWEB port map (IOLDO=>nRWE_c, nRWES=>nRWE); nRWE_MGIOLI: nRWE_MGIOL port map (IOLDO=>nRWE_c, OPOS=>N_147_i, CLK=>RCLK_c); RCKEI: RCKEB port map (IOLDO=>RCKE_c_n2, RCKES=>RCKE); RCKE_MGIOLI: RCKE_MGIOL port map (IOLDO=>RCKE_c_n2, OPOS=>RCKE_2, CLK=>RCLK_c); RCLKI: RCLKB port map (PADDI=>RCLK_c, RCLKS=>RCLK); nRCSI: nRCSB port map (IOLDO=>nRCS_c, nRCSS=>nRCS); nRCS_MGIOLI: nRCS_MGIOL port map (IOLDO=>nRCS_c, OPOS=>N_27_i, CLK=>RCLK_c); RD_7_I: RD_7_B port map (IOLDO=>WRD_7, PADDT=>RD_1_i, RD7=>RD(7)); RD_7_MGIOLI: RD_7_MGIOL port map (IOLDO=>WRD_7, OPOS=>Din_c_7, CLK=>nCCAS_c); RD_6_I: RD_6_B port map (IOLDO=>WRD_6, PADDT=>RD_1_i, RD6=>RD(6)); RD_6_MGIOLI: RD_6_MGIOL port map (IOLDO=>WRD_6, OPOS=>Din_c_6, CLK=>nCCAS_c); RD_5_I: RD_5_B port map (IOLDO=>WRD_5, PADDT=>RD_1_i, RD5=>RD(5)); RD_5_MGIOLI: RD_5_MGIOL port map (IOLDO=>WRD_5, OPOS=>Din_c_5, CLK=>nCCAS_c); RD_4_I: RD_4_B port map (IOLDO=>WRD_4, PADDT=>RD_1_i, RD4=>RD(4)); RD_4_MGIOLI: RD_4_MGIOL port map (IOLDO=>WRD_4, OPOS=>Din_c_4, CLK=>nCCAS_c); RD_3_I: RD_3_B port map (IOLDO=>WRD_3, PADDT=>RD_1_i, RD3=>RD(3)); RD_3_MGIOLI: RD_3_MGIOL port map (IOLDO=>WRD_3, OPOS=>Din_c_3, CLK=>nCCAS_c); RD_2_I: RD_2_B port map (IOLDO=>WRD_2, PADDT=>RD_1_i, RD2=>RD(2)); RD_2_MGIOLI: RD_2_MGIOL port map (IOLDO=>WRD_2, OPOS=>Din_c_2, CLK=>nCCAS_c); RD_1_I0: RD_1_B port map (IOLDO=>WRD_1, PADDT=>RD_1_i, RD1=>RD(1)); RD_1_MGIOLI: RD_1_MGIOL port map (IOLDO=>WRD_1, OPOS=>Din_c_1, CLK=>nCCAS_c); RA_11_I: RA_11_B port map (IOLDO=>RA_c_11, RA11=>RA(11)); RA_11_MGIOLI: RA_11_MGIOL port map (IOLDO=>RA_c_11, OPOS=>RA11d_0, CLK=>PHI2_c); RA_10_I: RA_10_B port map (IOLDO=>RA_c_10, RA10=>RA(10)); RA_10_MGIOLI: RA_10_MGIOL port map (IOLDO=>RA_c_10, OPOS=>N_153, LSR=>RA10s_i, CLK=>RCLK_c); RA_9_I: RA_9_B port map (PADDO=>RA_c_9, RA9=>RA(9)); RA_8_I: RA_8_B port map (PADDO=>RA_c_8, RA8=>RA(8)); RA_7_I: RA_7_B port map (PADDO=>RA_c_7, RA7=>RA(7)); RA_6_I: RA_6_B port map (PADDO=>RA_c_6, RA6=>RA(6)); RA_5_I: RA_5_B port map (PADDO=>RA_c_5, RA5=>RA(5)); RA_4_I: RA_4_B port map (PADDO=>RA_c_4, RA4=>RA(4)); RA_3_I: RA_3_B port map (PADDO=>RA_c_3, RA3=>RA(3)); RA_2_I: RA_2_B port map (PADDO=>RA_c_2, RA2=>RA(2)); RA_1_I: RA_1_B port map (PADDO=>RA_c_1, RA1=>RA(1)); RA_0_I: RA_0_B port map (PADDO=>RA_c_0, RA0=>RA(0)); RBA_1_I: RBA_1_B port map (IOLDO=>RBA_c_1, RBA1=>RBA(1)); RBA_1_MGIOLI: RBA_1_MGIOL port map (IOLDO=>RBA_c_1, OPOS=>RBAd_0_1, CLK=>nCRAS_c); RBA_0_I: RBA_0_B port map (IOLDO=>RBA_c_0, RBA0=>RBA(0)); RBA_0_MGIOLI: RBA_0_MGIOL port map (IOLDO=>RBA_c_0, OPOS=>RBAd_0_0, CLK=>nCRAS_c); LEDI: LEDB port map (PADDO=>LED_c, LEDS=>LED); nFWEI: nFWEB port map (PADDI=>nFWE_c, nFWES=>nFWE); nCRASI: nCRASB port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); nCCASI: nCCASB port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); Dout_7_I: Dout_7_B port map (PADDO=>nCRAS_c, Dout7=>Dout(7)); Dout_6_I: Dout_6_B port map (PADDO=>MAin_c_9, Dout6=>Dout(6)); Dout_5_I: Dout_5_B port map (PADDO=>MAin_c_8, Dout5=>Dout(5)); Dout_4_I: Dout_4_B port map (PADDO=>MAin_c_7, Dout4=>Dout(4)); Dout_3_I: Dout_3_B port map (PADDO=>MAin_c_6, Dout3=>Dout(3)); Dout_2_I: Dout_2_B port map (PADDO=>MAin_c_5, Dout2=>Dout(2)); Dout_1_I: Dout_1_B port map (PADDO=>MAin_c_4, Dout1=>Dout(1)); Din_7_I: Din_7_B port map (PADDI=>Din_c_7, Din7=>Din(7)); Din_7_MGIOLI: Din_7_MGIOL port map (DI=>Din_c_7, CLK=>PHI2_c, INP=>Bank_7); Din_6_I: Din_6_B port map (PADDI=>Din_c_6, Din6=>Din(6)); Din_6_MGIOLI: Din_6_MGIOL port map (DI=>Din_c_6, CLK=>PHI2_c, INP=>Bank_6); Din_5_I: Din_5_B port map (PADDI=>Din_c_5, Din5=>Din(5)); Din_5_MGIOLI: Din_5_MGIOL port map (DI=>Din_c_5, CLK=>PHI2_c, INP=>Bank_5); Din_4_I: Din_4_B port map (PADDI=>Din_c_4, Din4=>Din(4)); Din_4_MGIOLI: Din_4_MGIOL port map (DI=>Din_c_4, CLK=>PHI2_c, INP=>Bank_4); Din_3_I: Din_3_B port map (PADDI=>Din_c_3, Din3=>Din(3)); Din_3_MGIOLI: Din_3_MGIOL port map (DI=>Din_c_3, CLK=>PHI2_c, INP=>Bank_3); Din_2_I: Din_2_B port map (PADDI=>Din_c_2, Din2=>Din(2)); Din_2_MGIOLI: Din_2_MGIOL port map (DI=>Din_c_2, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, INP=>CmdUFMCS); Din_1_I: Din_1_B port map (PADDI=>Din_c_1, Din1=>Din(1)); Din_1_MGIOLI: Din_1_MGIOL port map (DI=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, INP=>CmdUFMCLK); Din_0_I: Din_0_B port map (PADDI=>Din_c_0, Din0=>Din(0)); Din_0_MGIOLI: Din_0_MGIOL port map (DI=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c, INP=>CmdUFMSDI); CROW_1_I: CROW_1_B port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); CROW_0_I: CROW_0_B port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); MAin_9_I: MAin_9_B port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); MAin_8_I: MAin_8_B port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); MAin_7_I: MAin_7_B port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); MAin_6_I: MAin_6_B port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); MAin_5_I: MAin_5_B port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); MAin_4_I: MAin_4_B port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); MAin_3_I: MAin_3_B port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); MAin_2_I: MAin_2_B port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); MAin_1_I: MAin_1_B port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); MAin_0_I: MAin_0_B port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); VHI_INST: VHI port map (Z=>VCCI); PUR_INST: PUR port map (PUR=>VCCI); GSR_INST: GSR port map (GSR=>VCCI); end Structure; library IEEE, vital2000, MACHXO2; configuration Structure_CON of RAM2GS is for Structure end for; end Structure_CON;