Lattice Mapping Report File for Design Module 'RAM2GS'
Design Information
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
-ioreg b RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd
-pr RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:
/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640
HC_impl1_synplify.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-
640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 08/15/23 23:30:05
Design Summary
Number of registers: 93 out of 877 (11%)
PFU registers: 64 out of 640 (10%)
PIO registers: 29 out of 237 (12%)
Number of SLICEs: 81 out of 320 (25%)
SLICEs as Logic/ROM: 81 out of 320 (25%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 159 out of 640 (25%)
Number used as logic LUTs: 139
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 4
Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 )
Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 6
Net XOR8MEG18: 3 loads, 3 LSLICEs
Net i2_i: 1 loads, 0 LSLICEs
Net N_26: 1 loads, 1 LSLICEs
Net N_28: 1 loads, 1 LSLICEs
Net N_188_i: 2 loads, 2 LSLICEs
Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs
Number of LSRs: 3
Net RA10s_i: 1 loads, 0 LSLICEs
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 17 loads
Net Ready: 15 loads
Net Ready_fast: 14 loads
Net Din_c[5]: 12 loads
Net nRowColSel: 12 loads
Net S[1]: 12 loads
Net RASr2: 10 loads
Net CO0: 9 loads
Net Din_c[3]: 9 loads
Net Din_c[4]: 9 loads
Number of warnings: 6
Number of errors: 0
Design Errors/Warnings
WARNING - map: Output register UFMSDI$r0 is replicated for UFMSDI_pad.
WARNING - map: Output register nUFMCS$r1 is replicated for nUFMCS_pad.
WARNING - map: Output register RCKE$r2 is replicated for RCKE_pad.
WARNING - map: Register Bank_0io[0] cannot be packed into IOC as intended by its
primitive type or preference due to command option or architecture
limitation. The register was packed into SLICE instead.
WARNING - map: Register Bank_0io[1] cannot be packed into IOC as intended by its
primitive type or preference due to command option or architecture
limitation. The register was packed into SLICE instead.
WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
primitive type or preference due to command option or architecture
limitation. The register was packed into SLICE instead.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI2 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| UFMSDO | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| UFMSDI | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| UFMCLK | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nUFMCS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RDQMH | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRRAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[9] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[8] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nFWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nCRAS | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nCCAS | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| CROW[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CROW[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[9] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[8] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Removed logic
Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal XOR8MEG.CN was merged into signal PHI2_c
Signal GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block XOR8MEG.CN was optimized away.
Block GND was optimized away.
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 36 MB
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Copyright (c) 2001 Agere Systems All rights reserved.
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