Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module RAM2GS
@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
Running optimization stage 2 on RAM2GS .......
Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 22:34:18 2023

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: ZANEPC

Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

@N|Running in 64-bit mode
@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 22:34:18 2023

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Aug 15 22:34:18 2023

###########################################################]