| Project Settings |
|---|
| Project Name | proj_1 | Device Name | impl1: Lattice MachXO2 : LCMXO2_640HC |
| Implementation Name | impl1 | Top Module | RAM2GS |
| Pipelining | 0 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
4 |
0 |
0 |
- |
00m:00s |
- |
8/15/2023
11:12:41 PM |
| (premap) | Complete |
27 |
1 |
0 |
0m:01s |
0m:01s |
174MB |
8/15/2023
11:12:44 PM |
| (fpga_mapper) | Complete |
19 |
6 |
0 |
0m:02s |
0m:02s |
184MB |
8/15/2023
11:12:47 PM |
| Multi-srs Generator |
Complete | | | | | | | 8/15/2023
11:12:42 PM |
| Area Summary |
|---|
|
| Register bits | 90 |
I/O cells | 67 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 135 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PHI2 | 2.9 MHz | 0.8 MHz | -2.389 |
| RCLK | 62.5 MHz | 18.4 MHz | -0.784 |
| nCCAS | 2.9 MHz | NA | NA |
| nCRAS | 2.9 MHz | 1.0 MHz | -1.821 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 4 / 0 |
| |
|