Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: 4 Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 Thu Sep 21 05:40:03 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf Design file: ram2gs_lcmxo2_1200hc_impl1.ncd Preference file: ram2gs_lcmxo2_1200hc_impl1.prf Device,speed: LCMXO2-1200HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; 147 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 160.229ns (weighted slack = 320.458ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 11.846ns (25.8% logic, 74.2% route), 6 logic levels. Constraint Details: 11.846ns physical path delay Din[0]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 160.229ns Physical Path Details: Data path Din[0]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11 ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16 CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33 ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 11.846 (25.8% logic, 74.2% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 161.365ns (weighted slack = 322.730ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) Destination: FF Data in CmdUFMData (to PHI2_c -) Delay: 10.569ns (24.2% logic, 75.8% route), 5 logic levels. Constraint Details: 10.569ns physical path delay Din[0]_MGIOL to SLICE_82 meets 172.414ns delay constraint less 0.173ns skew and 0.307ns CE_SET requirement (totaling 171.934ns) by 161.365ns Physical Path Details: Data path Din[0]_MGIOL to SLICE_82: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23 ROUTE 8 0.718 R5C10A.F1 to R5C10C.B0 XOR8MEG18 CTOF_DEL --- 0.495 R5C10C.B0 to R5C10C.F0 SLICE_82 ROUTE 1 0.653 R5C10C.F0 to R5C10C.CE CmdUFMData_1_sqmuxa (to PHI2_c) -------- 10.569 (24.2% logic, 75.8% route), 5 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_82: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C10C.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 161.468ns (weighted slack = 322.936ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[2] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 10.607ns (28.8% logic, 71.2% route), 6 logic levels. Constraint Details: 10.607ns physical path delay Din[2]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.468ns Physical Path Details: Data path Din[2]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T12A.CLK to IOL_T12A.IN Din[2]_MGIOL (from PHI2_c) ROUTE 1 1.512 IOL_T12A.IN to R4C11A.C0 Bank[2] CTOF_DEL --- 0.495 R4C11A.C0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11 ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16 CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33 ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 10.607 (28.8% logic, 71.2% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[2]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_T12A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 161.870ns (weighted slack = 323.740ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) Destination: FF Data in CmdValid (to PHI2_c -) Delay: 10.205ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 10.205ns physical path delay Din[0]_MGIOL to SLICE_22 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.870ns Physical Path Details: Data path Din[0]_MGIOL to SLICE_22: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23 ROUTE 8 1.007 R5C10A.F1 to R5C10D.A0 XOR8MEG18 CTOF_DEL --- 0.495 R5C10D.A0 to R5C10D.F0 SLICE_22 ROUTE 1 0.000 R5C10D.F0 to R5C10D.DI0 CmdValid_r (to PHI2_c) -------- 10.205 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_22: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C10D.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 161.985ns (weighted slack = 323.970ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[1] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 10.090ns (30.2% logic, 69.8% route), 6 logic levels. Constraint Details: 10.090ns physical path delay Din[1]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 161.985ns Physical Path Details: Data path Din[1]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c) ROUTE 1 1.601 IOL_T10B.IN to R2C10A.A1 Bank[1] CTOF_DEL --- 0.495 R2C10A.A1 to R2C10A.F1 SLICE_84 ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11 CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84 ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11 ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16 CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33 ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 10.090 (30.2% logic, 69.8% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[1]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 162.032ns (weighted slack = 324.064ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[5] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 10.043ns (30.4% logic, 69.6% route), 6 logic levels. Constraint Details: 10.043ns physical path delay Din[5]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.032ns Physical Path Details: Data path Din[5]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T9B.CLK to IOL_T9B.IN Din[5]_MGIOL (from PHI2_c) ROUTE 1 1.554 IOL_T9B.IN to R2C10A.B1 Bank[5] CTOF_DEL --- 0.495 R2C10A.B1 to R2C10A.F1 SLICE_84 ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11 CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84 ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11 ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16 CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33 ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 10.043 (30.4% logic, 69.6% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[5]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_T9B.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 162.097ns (weighted slack = 324.194ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 9.978ns (25.6% logic, 74.4% route), 5 logic levels. Constraint Details: 9.978ns physical path delay Din[0]_MGIOL to SLICE_10 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.097ns Physical Path Details: Data path Din[0]_MGIOL to SLICE_10: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11 ROUTE 3 0.987 R5C12C.F1 to R5C13B.A0 CmdEnable16 CTOF_DEL --- 0.495 R5C13B.A0 to R5C13B.F0 SLICE_10 ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- 9.978 (25.6% logic, 74.4% route), 5 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C13B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 162.159ns (weighted slack = 324.318ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) Destination: FF Data in CmdValid_fast (to PHI2_c -) Delay: 9.916ns (25.8% logic, 74.2% route), 5 logic levels. Constraint Details: 9.916ns physical path delay Din[0]_MGIOL to SLICE_23 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.159ns Physical Path Details: Data path Din[0]_MGIOL to SLICE_23: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23 ROUTE 8 0.718 R5C10A.F1 to R5C10A.B0 XOR8MEG18 CTOF_DEL --- 0.495 R5C10A.B0 to R5C10A.F0 SLICE_23 ROUTE 1 0.000 R5C10A.F0 to R5C10A.DI0 N_36_fast (to PHI2_c) -------- 9.916 (25.8% logic, 74.2% route), 5 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C10A.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 162.410ns (weighted slack = 324.820ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[4] (from PHI2_c +) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 9.665ns (31.6% logic, 68.4% route), 6 logic levels. Constraint Details: 9.665ns physical path delay Din[4]_MGIOL to SLICE_17 meets 172.414ns delay constraint less 0.173ns skew and 0.166ns DIN_SET requirement (totaling 172.075ns) by 162.410ns Physical Path Details: Data path Din[4]_MGIOL to SLICE_17: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_T9A.CLK to IOL_T9A.IN Din[4]_MGIOL (from PHI2_c) ROUTE 1 1.176 IOL_T9A.IN to R2C10A.D1 Bank[4] CTOF_DEL --- 0.495 R2C10A.D1 to R2C10A.F1 SLICE_84 ROUTE 1 0.693 R2C10A.F1 to R2C10A.B0 un1_CmdEnable20_0_0_o3_11 CTOF_DEL --- 0.495 R2C10A.B0 to R2C10A.F0 SLICE_84 ROUTE 6 2.384 R2C10A.F0 to R5C12C.A1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C12C.A1 to R5C12C.F1 SLICE_11 ROUTE 3 1.359 R5C12C.F1 to R5C14C.B0 CmdEnable16 CTOF_DEL --- 0.495 R5C14C.B0 to R5C14C.F0 SLICE_33 ROUTE 1 1.001 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa CTOF_DEL --- 0.495 R5C13C.B0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 9.665 (31.6% logic, 68.4% route), 6 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[4]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_T9A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C13C.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 162.515ns (weighted slack = 325.030ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Bank_0io[0] (from PHI2_c +) Destination: FF Data in CmdLEDEN (to PHI2_c -) Delay: 9.419ns (21.9% logic, 78.1% route), 4 logic levels. Constraint Details: 9.419ns physical path delay Din[0]_MGIOL to SLICE_18 meets 172.414ns delay constraint less 0.173ns skew and 0.307ns CE_SET requirement (totaling 171.934ns) by 162.515ns Physical Path Details: Data path Din[0]_MGIOL to SLICE_18: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c) ROUTE 1 2.751 IOL_L3A.IN to R4C11A.B0 Bank[0] CTOF_DEL --- 0.495 R4C11A.B0 to R4C11A.F0 SLICE_93 ROUTE 1 1.299 R4C11A.F0 to R2C10A.A0 un1_CmdEnable20_0_0_o3_10 CTOF_DEL --- 0.495 R2C10A.A0 to R2C10A.F0 SLICE_84 ROUTE 6 2.591 R2C10A.F0 to R5C10A.C1 un1_CmdEnable20_0_0_o3 CTOF_DEL --- 0.495 R5C10A.C1 to R5C10A.F1 SLICE_23 ROUTE 8 0.716 R5C10A.F1 to R5C9B.CE XOR8MEG18 (to PHI2_c) -------- 9.419 (21.9% logic, 78.1% route), 4 logic levels. Clock Skew Details: Source Clock Path PHI2 to Din[0]_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c -------- 4.369 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 21 4.196 8.PADDI to R5C9B.CLK PHI2_c -------- 4.196 (0.0% logic, 100.0% route), 0 logic levels. Report: 41.034MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 338.168ns The internal maximum frequency of the following component is 150.150 MHz Logical Details: Cell type Pin name Component name Destination: PIO PAD nCCAS Delay: 6.660ns -- based on Minimum Pulse Width Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 338.168ns The internal maximum frequency of the following component is 150.150 MHz Logical Details: Cell type Pin name Component name Destination: PIO PAD nCRAS Delay: 6.660ns -- based on Minimum Pulse Width Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; 878 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 5.578ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[5] (to RCLK_c +) Delay: 10.256ns (30.7% logic, 69.3% route), 6 logic levels. Constraint Details: 10.256ns physical path delay SLICE_2 to SLICE_54 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.578ns Physical Path Details: Data path SLICE_2 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113 ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502 CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86 ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479 CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59 ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361 CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54 ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c) -------- 10.256 (30.7% logic, 69.3% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.578ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[5] (to RCLK_c +) Delay: 10.256ns (30.7% logic, 69.3% route), 6 logic levels. Constraint Details: 10.256ns physical path delay SLICE_2 to SLICE_54 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.578ns Physical Path Details: Data path SLICE_2 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113 ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502 CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86 ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479 CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59 ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361 CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54 ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c) -------- 10.256 (30.7% logic, 69.3% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.743ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[4] (to RCLK_c +) Delay: 10.091ns (29.0% logic, 71.0% route), 6 logic levels. Constraint Details: 10.091ns physical path delay SLICE_2 to SLICE_54 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.743ns Physical Path Details: Data path SLICE_2 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214 CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113 ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576 CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85 ROUTE 2 1.392 R3C4C.F1 to R4C4B.A0 N_473 CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_86 ROUTE 1 0.315 R4C4B.F0 to R4C4C.D0 wb_dati_5_1_iv_0_1[4] CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_54 ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 wb_dati_5[4] (to RCLK_c) -------- 10.091 (29.0% logic, 71.0% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.835ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) Destination: FF Data in wb_dati[5] (to RCLK_c +) Delay: 9.999ns (31.5% logic, 68.5% route), 6 logic levels. Constraint Details: 9.999ns physical path delay SLICE_1 to SLICE_54 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.835ns Physical Path Details: Data path SLICE_1 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c) ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17] CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113 ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502 CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86 ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479 CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59 ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361 CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54 ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c) -------- 9.999 (31.5% logic, 68.5% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.835ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) Destination: FF Data in wb_dati[5] (to RCLK_c +) Delay: 9.999ns (31.5% logic, 68.5% route), 6 logic levels. Constraint Details: 9.999ns physical path delay SLICE_1 to SLICE_54 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.835ns Physical Path Details: Data path SLICE_1 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c) ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17] CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113 ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502 CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86 ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479 CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59 ROUTE 2 1.015 R4C5B.OFX0 to R4C4C.B1 N_361 CTOF_DEL --- 0.495 R4C4C.B1 to R4C4C.F1 SLICE_54 ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 wb_dati_5[5] (to RCLK_c) -------- 9.999 (31.5% logic, 68.5% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.851ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[6] (to RCLK_c +) Delay: 9.983ns (29.3% logic, 70.7% route), 6 logic levels. Constraint Details: 9.983ns physical path delay SLICE_2 to SLICE_55 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.851ns Physical Path Details: Data path SLICE_2 to SLICE_55: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214 CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113 ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576 CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85 ROUTE 2 0.976 R3C4C.F1 to R3C4C.A0 N_473 CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_85 ROUTE 1 0.623 R3C4C.F0 to R3C5D.D0 wb_dati_5_1_iv_0_1[6] CTOF_DEL --- 0.495 R3C5D.D0 to R3C5D.F0 SLICE_55 ROUTE 1 0.000 R3C5D.F0 to R3C5D.DI0 wb_dati_5[6] (to RCLK_c) -------- 9.983 (29.3% logic, 70.7% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R3C5D.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.867ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[6] (to RCLK_c +) Delay: 9.967ns (29.4% logic, 70.6% route), 6 logic levels. Constraint Details: 9.967ns physical path delay SLICE_2 to SLICE_55 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.867ns Physical Path Details: Data path SLICE_2 to SLICE_55: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.559 R2C5D.F1 to R3C5A.B1 N_214 CTOF_DEL --- 0.495 R3C5A.B1 to R3C5A.F1 SLICE_87 ROUTE 4 1.323 R3C5A.F1 to R5C4B.A0 N_579 CTOF_DEL --- 0.495 R5C4B.A0 to R5C4B.F0 SLICE_89 ROUTE 1 1.023 R5C4B.F0 to R3C4C.B0 N_472 CTOF_DEL --- 0.495 R3C4C.B0 to R3C4C.F0 SLICE_85 ROUTE 1 0.623 R3C4C.F0 to R3C5D.D0 wb_dati_5_1_iv_0_1[6] CTOF_DEL --- 0.495 R3C5D.D0 to R3C5D.F0 SLICE_55 ROUTE 1 0.000 R3C5D.F0 to R3C5D.DI0 wb_dati_5[6] (to RCLK_c) -------- 9.967 (29.4% logic, 70.6% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R3C5D.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.956ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[2] (to RCLK_c +) Delay: 9.878ns (31.9% logic, 68.1% route), 6 logic levels. Constraint Details: 9.878ns physical path delay SLICE_2 to SLICE_53 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.956ns Physical Path Details: Data path SLICE_2 to SLICE_53: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113 ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502 CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86 ROUTE 3 0.987 R4C4B.F1 to R4C5B.A1 N_479 CTOOFX_DEL --- 0.721 R4C5B.A1 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59 ROUTE 2 0.637 R4C5B.OFX0 to R4C4D.D0 N_361 CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 SLICE_53 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 wb_dati_5[2] (to RCLK_c) -------- 9.878 (31.9% logic, 68.1% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_53: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4D.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.956ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in wb_dati[2] (to RCLK_c +) Delay: 9.878ns (31.9% logic, 68.1% route), 6 logic levels. Constraint Details: 9.878ns physical path delay SLICE_2 to SLICE_53 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 5.956ns Physical Path Details: Data path SLICE_2 to SLICE_53: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 2.512 R7C8A.Q1 to R2C5D.B1 FS[16] CTOF_DEL --- 0.495 R2C5D.B1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B1 N_214 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 SLICE_113 ROUTE 3 0.987 R4C5D.F1 to R4C4B.A1 N_502 CTOF_DEL --- 0.495 R4C4B.A1 to R4C4B.F1 SLICE_86 ROUTE 3 0.987 R4C4B.F1 to R4C5B.A0 N_479 CTOOFX_DEL --- 0.721 R4C5B.A0 to R4C5B.OFX0 wb_dati_5_1_iv_0_o3[5]/SLICE_59 ROUTE 2 0.637 R4C5B.OFX0 to R4C4D.D0 N_361 CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 SLICE_53 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 wb_dati_5[2] (to RCLK_c) -------- 9.878 (31.9% logic, 68.1% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8A.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_53: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4D.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 6.000ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) Destination: FF Data in wb_dati[4] (to RCLK_c +) Delay: 9.834ns (29.8% logic, 70.2% route), 6 logic levels. Constraint Details: 9.834ns physical path delay SLICE_1 to SLICE_54 meets 16.000ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 15.834ns) by 6.000ns Physical Path Details: Data path SLICE_1 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c) ROUTE 6 2.255 R7C8B.Q0 to R2C5D.C1 FS[17] CTOF_DEL --- 0.495 R2C5D.C1 to R2C5D.F1 SLICE_66 ROUTE 13 1.602 R2C5D.F1 to R4C5D.B0 N_214 CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_113 ROUTE 2 1.343 R4C5D.F0 to R3C4C.B1 N_576 CTOF_DEL --- 0.495 R3C4C.B1 to R3C4C.F1 SLICE_85 ROUTE 2 1.392 R3C4C.F1 to R4C4B.A0 N_473 CTOF_DEL --- 0.495 R4C4B.A0 to R4C4B.F0 SLICE_86 ROUTE 1 0.315 R4C4B.F0 to R4C4C.D0 wb_dati_5_1_iv_0_1[4] CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_54 ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 wb_dati_5[4] (to RCLK_c) -------- 9.834 (29.8% logic, 70.2% route), 6 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R7C8B.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 47 2.264 63.PADDI to R4C4C.CLK RCLK_c -------- 2.264 (0.0% logic, 100.0% route), 0 logic levels. Report: 95.951MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 41.034 MHz| 6 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0 | | | FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.951 MHz| 6 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 4 clocks: Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Thu Sep 21 05:40:03 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf Design file: ram2gs_lcmxo2_1200hc_impl1.ncd Preference file: ram2gs_lcmxo2_1200hc_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ; 147 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdUFMShift (from PHI2_c -) Destination: FF Data in CmdUFMShift (to PHI2_c -) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_20 to SLICE_20 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_20 (from PHI2_c) ROUTE 2 0.132 R5C9D.Q0 to R5C9D.A0 CmdUFMShift CTOF_DEL --- 0.101 R5C9D.A0 to R5C9D.F0 SLICE_20 ROUTE 1 0.000 R5C9D.F0 to R5C9D.DI0 CmdUFMShift_3 (to PHI2_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_20: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9D.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.382ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted (from PHI2_c -) Destination: FF Data in ADSubmitted (to PHI2_c -) Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. Constraint Details: 0.369ns physical path delay SLICE_10 to SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.382ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 SLICE_10 (from PHI2_c) ROUTE 2 0.135 R5C13B.Q0 to R5C13B.D0 ADSubmitted CTOF_DEL --- 0.101 R5C13B.D0 to R5C13B.F0 SLICE_10 ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 ADSubmitted_r_0_0 (to PHI2_c) -------- 0.369 (63.4% logic, 36.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.382ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q C1Submitted (from PHI2_c -) Destination: FF Data in C1Submitted (to PHI2_c -) Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. Constraint Details: 0.369ns physical path delay SLICE_11 to SLICE_11 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.382ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 SLICE_11 (from PHI2_c) ROUTE 2 0.135 R5C12C.Q0 to R5C12C.D0 C1Submitted CTOF_DEL --- 0.101 R5C12C.D0 to R5C12C.F0 SLICE_11 ROUTE 1 0.000 R5C12C.F0 to R5C12C.DI0 C1Submitted_RNO (to PHI2_c) -------- 0.369 (63.4% logic, 36.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C12C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.382ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 0.369ns (63.4% logic, 36.6% route), 2 logic levels. Constraint Details: 0.369ns physical path delay SLICE_17 to SLICE_17 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.382ns Physical Path Details: Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_17 (from PHI2_c) ROUTE 2 0.135 R5C13C.Q0 to R5C13C.D0 CmdEnable CTOF_DEL --- 0.101 R5C13C.D0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 0.369 (63.4% logic, 36.6% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.628ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdLEDEN (from PHI2_c -) Destination: FF Data in CmdLEDEN (to PHI2_c -) Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. Constraint Details: 0.615ns physical path delay SLICE_18 to SLICE_18 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.628ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_18 (from PHI2_c) ROUTE 2 0.224 R5C9B.Q0 to R5C9B.B1 CmdLEDEN CTOF_DEL --- 0.101 R5C9B.B1 to R5C9B.F1 SLICE_18 ROUTE 1 0.056 R5C9B.F1 to R5C9B.C0 CmdLEDEN_4_u_i_0_0 CTOF_DEL --- 0.101 R5C9B.C0 to R5C9B.F0 SLICE_18 ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_40_i (to PHI2_c) -------- 0.615 (54.5% logic, 45.5% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.628ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q XOR8MEG (from PHI2_c -) Destination: FF Data in XOR8MEG (to PHI2_c -) Delay: 0.615ns (54.5% logic, 45.5% route), 3 logic levels. Constraint Details: 0.615ns physical path delay SLICE_44 to SLICE_44 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.628ns Physical Path Details: Data path SLICE_44 to SLICE_44: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_44 (from PHI2_c) ROUTE 2 0.224 R5C10B.Q0 to R5C10B.B1 XOR8MEG CTOF_DEL --- 0.101 R5C10B.B1 to R5C10B.F1 SLICE_44 ROUTE 1 0.056 R5C10B.F1 to R5C10B.C0 N_441 CTOF_DEL --- 0.101 R5C10B.C0 to R5C10B.F0 SLICE_44 ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 XOR8MEG_3 (to PHI2_c) -------- 0.615 (54.5% logic, 45.5% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_44: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_44: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.693ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Cmdn8MEGEN (from PHI2_c -) Destination: FF Data in Cmdn8MEGEN (to PHI2_c -) Delay: 0.680ns (49.3% logic, 50.7% route), 3 logic levels. Constraint Details: 0.680ns physical path delay SLICE_24 to SLICE_24 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.693ns Physical Path Details: Data path SLICE_24 to SLICE_24: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C9C.CLK to R5C9C.Q0 SLICE_24 (from PHI2_c) ROUTE 2 0.135 R5C9C.Q0 to R5C9C.D1 Cmdn8MEGEN CTOF_DEL --- 0.101 R5C9C.D1 to R5C9C.F1 SLICE_24 ROUTE 1 0.210 R5C9C.F1 to R5C9C.A0 Cmdn8MEGEN_4_u_i_0_0 CTOF_DEL --- 0.101 R5C9C.A0 to R5C9C.F0 SLICE_24 ROUTE 1 0.000 R5C9C.F0 to R5C9C.DI0 N_38_i (to PHI2_c) -------- 0.680 (49.3% logic, 50.7% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.702ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdUFMWrite (from PHI2_c -) Destination: FF Data in CmdUFMWrite (to PHI2_c -) Delay: 0.689ns (48.6% logic, 51.4% route), 3 logic levels. Constraint Details: 0.689ns physical path delay SLICE_21 to SLICE_21 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.702ns Physical Path Details: Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_21 (from PHI2_c) ROUTE 2 0.212 R5C9A.Q0 to R5C9A.A1 CmdUFMWrite CTOF_DEL --- 0.101 R5C9A.A1 to R5C9A.F1 SLICE_21 ROUTE 1 0.142 R5C9A.F1 to R5C9A.B0 N_462 CTOF_DEL --- 0.101 R5C9A.B0 to R5C9A.F0 SLICE_21 ROUTE 1 0.000 R5C9A.F0 to R5C9A.DI0 CmdUFMWrite_3 (to PHI2_c) -------- 0.689 (48.6% logic, 51.4% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.710ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ADSubmitted (from PHI2_c -) Destination: FF Data in CmdEnable (to PHI2_c -) Delay: 0.697ns (48.1% logic, 51.9% route), 3 logic levels. Constraint Details: 0.697ns physical path delay SLICE_10 to SLICE_17 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.710ns Physical Path Details: Data path SLICE_10 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 SLICE_10 (from PHI2_c) ROUTE 2 0.139 R5C13B.Q0 to R5C14C.C0 ADSubmitted CTOF_DEL --- 0.101 R5C14C.C0 to R5C14C.F0 SLICE_33 ROUTE 1 0.223 R5C14C.F0 to R5C13C.B0 CmdEnable_0_sqmuxa CTOF_DEL --- 0.101 R5C13C.B0 to R5C13C.F0 SLICE_17 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 CmdEnable_s (to PHI2_c) -------- 0.697 (48.1% logic, 51.9% route), 3 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.723ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CmdEnable (from PHI2_c -) Destination: FF Data in XOR8MEG (to PHI2_c -) Delay: 0.695ns (33.7% logic, 66.3% route), 2 logic levels. Constraint Details: 0.695ns physical path delay SLICE_17 to SLICE_44 meets -0.028ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.028ns) by 0.723ns Physical Path Details: Data path SLICE_17 to SLICE_44: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q0 SLICE_17 (from PHI2_c) ROUTE 2 0.309 R5C13C.Q0 to R5C10A.B1 CmdEnable CTOF_DEL --- 0.101 R5C10A.B1 to R5C10A.F1 SLICE_23 ROUTE 8 0.152 R5C10A.F1 to R5C10B.CE XOR8MEG18 (to PHI2_c) -------- 0.695 (33.7% logic, 66.3% route), 2 logic levels. Clock Skew Details: Source Clock Path PHI2 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C13C.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path PHI2 to SLICE_44: Name Fanout Delay (ns) Site Resource ROUTE 21 1.423 8.PADDI to R5C10B.CLK PHI2_c -------- 1.423 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ; 878 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CASr (from RCLK_c +) Destination: FF Data in CASr2 (to RCLK_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_12 to SLICE_12 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C13D.CLK to R5C13D.Q0 SLICE_12 (from RCLK_c) ROUTE 1 0.152 R5C13D.Q0 to R5C13D.M1 CASr (to RCLK_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R5C13D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R5C13D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RASr (from RCLK_c +) Destination: FF Data in RASr2 (to RCLK_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_32 to SLICE_32 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_32 to SLICE_32: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C14C.CLK to R7C14C.Q0 SLICE_32 (from RCLK_c) ROUTE 2 0.154 R7C14C.Q0 to R7C14C.M1 RASr (to RCLK_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C14C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C14C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.311ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PHI2r2 (from RCLK_c +) Destination: FF Data in PHI2r3 (to RCLK_c +) Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. Constraint Details: 0.292ns physical path delay SLICE_31 to SLICE_31 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.311ns Physical Path Details: Data path SLICE_31 to SLICE_31: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C8A.CLK to R4C8A.Q0 SLICE_31 (from RCLK_c) ROUTE 5 0.159 R4C8A.Q0 to R4C8A.M1 PHI2r2 (to RCLK_c) -------- 0.292 (45.5% logic, 54.5% route), 1 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R4C8A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R4C8A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[0] (from RCLK_c +) Destination: FF Data in FS[0] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_0 to SLICE_0 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C6A.CLK to R7C6A.Q1 SLICE_0 (from RCLK_c) ROUTE 3 0.132 R7C6A.Q1 to R7C6A.A1 FS[0] CTOF_DEL --- 0.101 R7C6A.A1 to R7C6A.F1 SLICE_0 ROUTE 1 0.000 R7C6A.F1 to R7C6A.DI1 FS_s[0] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C6A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C6A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[17] (from RCLK_c +) Destination: FF Data in FS[17] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_1 to SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 SLICE_1 (from RCLK_c) ROUTE 6 0.132 R7C8B.Q0 to R7C8B.A0 FS[17] CTOF_DEL --- 0.101 R7C8B.A0 to R7C8B.F0 SLICE_1 ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 FS_s[17] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C8B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C8B.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[15] (from RCLK_c +) Destination: FF Data in FS[15] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_2 to SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q0 SLICE_2 (from RCLK_c) ROUTE 9 0.132 R7C8A.Q0 to R7C8A.A0 FS[15] CTOF_DEL --- 0.101 R7C8A.A0 to R7C8A.F0 SLICE_2 ROUTE 1 0.000 R7C8A.F0 to R7C8A.DI0 FS_s[15] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[16] (from RCLK_c +) Destination: FF Data in FS[16] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_2 to SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q1 SLICE_2 (from RCLK_c) ROUTE 6 0.132 R7C8A.Q1 to R7C8A.A1 FS[16] CTOF_DEL --- 0.101 R7C8A.A1 to R7C8A.F1 SLICE_2 ROUTE 1 0.000 R7C8A.F1 to R7C8A.DI1 FS_s[16] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C8A.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[14] (from RCLK_c +) Destination: FF Data in FS[14] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C7D.CLK to R7C7D.Q1 SLICE_3 (from RCLK_c) ROUTE 18 0.132 R7C7D.Q1 to R7C7D.A1 FS[14] CTOF_DEL --- 0.101 R7C7D.A1 to R7C7D.F1 SLICE_3 ROUTE 1 0.000 R7C7D.F1 to R7C7D.DI1 FS_s[14] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[13] (from RCLK_c +) Destination: FF Data in FS[13] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_3 to SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C7D.CLK to R7C7D.Q0 SLICE_3 (from RCLK_c) ROUTE 22 0.132 R7C7D.Q0 to R7C7D.A0 FS[13] CTOF_DEL --- 0.101 R7C7D.A0 to R7C7D.F0 SLICE_3 ROUTE 1 0.000 R7C7D.F0 to R7C7D.DI0 FS_s[13] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C7D.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FS[12] (from RCLK_c +) Destination: FF Data in FS[12] (to RCLK_c +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay SLICE_4 to SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C7C.CLK to R7C7C.Q1 SLICE_4 (from RCLK_c) ROUTE 21 0.132 R7C7C.Q1 to R7C7C.A1 FS[12] CTOF_DEL --- 0.101 R7C7C.A1 to R7C7C.F1 SLICE_4 ROUTE 1 0.000 R7C7C.F1 to R7C7C.DI1 FS_s[12] (to RCLK_c) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C7C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RCLK to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 47 0.788 63.PADDI to R7C7C.CLK RCLK_c -------- 0.788 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2 | | | FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0 | | | FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0 | | | FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 4 clocks: Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11 No transfer within this clock domain is found Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10 No transfer within this clock domain is found Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47 Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ; Data transfers from: Clock Domain: nCRAS_c Source: nCRAS.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21 Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ; Data transfers from: Clock Domain: RCLK_c Source: RCLK.PAD Not reported because source and destination domains are unrelated. To report these transfers please refer to preference CLKSKEWDIFF to define external clock skew between clock ports. Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1025 paths, 4 nets, and 758 connections (74.53% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------