Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd" Sat Aug 19 21:55:01 2023 PAR: Place And Route Diamond (64-bit) 3.12.1.454. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf Preference file: LCMXO2_640HC_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file LCMXO2_640HC_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-640HC Package: TQFP100 Performance: 4 Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 63+4(JTAG)/80 84% used 63+4(JTAG)/79 85% bonded IOLOGIC 25/80 31% used SLICE 113/320 35% used EFB 1/1 100% used Number of Signals: 374 Number of Connections: 978 Pin Constraint Summary: 63 out of 63 pins locked (100% locked). The following 3 signals are selected to use the primary clock routing resources: RCLK_c (driver: RCLK, clk load #: 47) PHI2_c (driver: PHI2, clk load #: 21) nCRAS_c (driver: nCRAS, clk load #: 10) WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. The following 1 signal is selected to use the secondary clock routing resources: nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0) WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. No signal is selected as Global Set/Reset. Starting Placer Phase 0. ............ Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. .................... Placer score = 53481. Finished Placer Phase 1. REAL time: 5 secs Starting Placer Phase 2. . Placer score = 53406 Finished Placer Phase 2. REAL time: 5 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 4 out of 80 (5%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21 PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10 SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0 PRIMARY : 3 out of 8 (37%) SECONDARY: 1 out of 8 (12%) --------------- End of Clock Report --------------- I/O Usage Summary (final): 63 + 4(JTAG) out of 80 (83.8%) PIO sites used. 63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used. Number of PIO comps: 63; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 13 / 19 ( 68%) | 3.3V | - | | 1 | 20 / 20 (100%) | 3.3V | - | | 2 | 12 / 20 ( 60%) | 3.3V | - | | 3 | 18 / 20 ( 90%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 5 secs Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. 0 connections routed; 978 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. Completed router resource preassignment. Real time: 8 secs Start NBR router at 21:55:09 08/19/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 21:55:09 08/19/23 Start NBR section for initial routing at 21:55:10 08/19/23 Level 1, iteration 1 0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 7.085ns/0.000ns; real time: 9 secs Level 2, iteration 1 0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 7.138ns/0.000ns; real time: 9 secs Level 3, iteration 1 0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 7.276ns/0.000ns; real time: 9 secs Level 4, iteration 1 10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 21:55:10 08/19/23 Level 4, iteration 1 3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23 Start NBR section for re-routing at 21:55:10 08/19/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 6.966ns/0.000ns; real time: 9 secs Start NBR section for post-routing at 21:55:10 08/19/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 6.966ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 9 secs Total REAL time: 9 secs Completely routed. End of route. 978 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = 6.966 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 9 secs Total REAL time to completion: 10 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.