# messages

id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: FX474
kind: warning
message:
User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 


id: FX1143
kind: note
message:
Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.


id: FX271
link: "y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9
kind: note
message:
Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.


id: FX271
link: "y:\repos\ram2gs\cpld\ram2gs-lcmxo2.v":303:4:303:9
kind: note
message:
Replicating instance CmdUFMShift (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.


id: MT246
link: "y:\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16
kind: warning
message:
Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)


id: MT320
kind: note
message:
This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.


id: MT117
kind: warning
message:
Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.  


id: MT118
kind: warning
message:
Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  


id: MT118
kind: warning
message:
Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.  


id: MT116
kind: warning
message:
Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.  


id: MT117
kind: warning
message:
Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.  


