{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1692496760355 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1692496760386 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 19 21:59:20 2023 " "Processing started: Sat Aug 19 21:59:20 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1692496760386 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1692496760386 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1692496760386 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1692496762433 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(61) " "Verilog HDL warning at RAM2GS-MAX.v(61): extended using \"x\" or \"z\"" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 61 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1692496772308 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//zanemac/repos/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file //zanemac/repos/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1692496772323 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1692496772323 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1692496772402 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" {  } { { "UFM.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1692496772402 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" {  } { { "UFM.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1692496772402 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" {  } { { "UFM.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1692496772402 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1692496772402 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1692496773089 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "UFM_inst" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 92 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1692496773651 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" {  } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1692496774308 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778136 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778136 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778136 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778136 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778136 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778136 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778167 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" {  } { { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 27 -1 0 } } { "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" "" { Text "//ZaneMac/Repos/RAM2GS/CPLD/RAM2GS-MAX.v" 60 -1 0 } }  } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1692496778167 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1692496778636 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1692496778636 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1692496778636 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1692496778636 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" {  } {  } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1692496778636 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1692496778636 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file //ZaneMac/Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1692496779401 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4704 " "Peak virtual memory: 4704 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1692496781526 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 19 21:59:41 2023 " "Processing ended: Sat Aug 19 21:59:41 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1692496781526 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1692496781526 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1692496781526 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1692496781526 ""}