Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Sat Oct 09 01:19:13 2021
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP100.
The -d option is LCMXO2-640HC.
Using package TQFP100.
Using performance grade 4.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-640HC
### Package : TQFP100
### Speed : 4
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = RAM2GS.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): RAM2GS
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Top-level module name = RAM2GS.
######## Missing driver on net n1128. Patching with GND.
######## Missing driver on net n1132. Patching with GND.
######## Missing driver on net n1133. Patching with GND.
######## Missing driver on net n1134. Patching with GND.
######## Missing driver on net n1135. Patching with GND.
######## Missing driver on net n1131. Patching with GND.
######## Missing driver on net n1130. Patching with GND.
######## Missing driver on net n1136. Patching with GND.
######## Missing driver on net n1137. Patching with GND.
######## Missing driver on net n1138. Patching with GND.
######## Missing driver on net n1139. Patching with GND.
######## Missing driver on net n1140. Patching with GND.
######## Missing driver on net n1141. Patching with GND.
######## Missing driver on net n1142. Patching with GND.
######## Missing driver on net n1143. Patching with GND.
######## Missing driver on net n1144. Patching with GND.
######## Missing driver on net n1145. Patching with GND.
######## Missing driver on net n1146. Patching with GND.
######## Missing driver on net n1147. Patching with GND.
######## Missing driver on net n1148. Patching with GND.
######## Missing driver on net n1129. Patching with GND.
######## Missing driver on net n1149. Patching with GND.
######## Missing driver on net n1150. Patching with GND.
######## Missing driver on net n1151. Patching with GND.
######## Missing driver on net n1152. Patching with GND.
######## Missing driver on net n1153. Patching with GND.
######## Missing driver on net n1154. Patching with GND.
######## Missing driver on net n1155. Patching with GND.
######## Missing driver on net n1156. Patching with GND.
######## Missing driver on net n1157. Patching with GND.
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
GSR will not be inferred because no asynchronous signal was found in the netlist.
WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in RAM2GS_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
################### Begin Area Report (RAM2GS)######################
Number of register bits => 119 of 877 (13 % )
BB => 8
CCU2D => 10
EFB => 1
FD1P3AX => 30
FD1P3AY => 4
FD1P3IX => 3
FD1S3AX => 64
FD1S3IX => 14
FD1S3JX => 4
GSR => 1
IB => 25
INV => 3
LUT4 => 236
OB => 30
PFUMX => 16
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 5
Net : RCLK_c, loads : 79
Net : PHI2_c, loads : 11
Net : nCRAS_c, loads : 2
Net : nCCAS_c, loads : 2
Net : wb_clk, loads : 1
Clock Enable Nets
Number of Clock Enables: 14
Top 10 highest fanout Clock Enables:
Net : RCLK_c_enable_27, loads : 16
Net : RCLK_c_enable_20, loads : 4
Net : RCLK_c_enable_25, loads : 2
Net : RCLK_c_enable_24, loads : 2
Net : RCLK_c_enable_29, loads : 2
Net : PHI2_N_151_enable_5, loads : 2
Net : PHI2_N_151_enable_3, loads : 2
Net : PHI2_N_151_enable_1, loads : 1
Net : Ready_N_280, loads : 1
Net : PHI2_N_151_enable_6, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : InitReady, loads : 36
Net : FS_11, loads : 32
Net : FS_10, loads : 32
Net : FS_9, loads : 26
Net : FS_7, loads : 25
Net : FS_8, loads : 23
Net : FS_6, loads : 21
Net : FS_5, loads : 21
Net : FS_12, loads : 20
Net : CmdUFMShift, loads : 16
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 *
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
Peak Memory Usage: 58.262 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.813 secs
--------------------------------------------------------------