Lattice Mapping Report File for Design Module 'RAM2GS' Design Information ------------------ Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial -ioreg b RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf //Mac/iCloud /Repos/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO.lpf -c 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml Target Vendor: LATTICE Target Device: LCMXO256CTQFP100 Target Performance: 3 Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 Mapped on: 01/06/24 06:24:57 Design Summary -------------- Number of PFU registers: 92 out of 256 (36%) Number of SLICEs: 76 out of 128 (59%) SLICEs as Logic/ROM: 76 out of 128 (59%) SLICEs as RAM: 0 out of 64 (0%) SLICEs as Carry: 9 out of 128 (7%) Number of LUT4s: 151 out of 256 (59%) Number used as logic LUTs: 133 Number used as distributed RAM: 0 Number used as ripple logic: 18 Number used as shift registers: 0 Number of external PIOs: 67 out of 78 (86%) Number of GSRs: 0 out of 1 (0%) JTAG used : No Readback used : No Oscillator used : No Startup used : No Number of TSALL: 0 out of 1 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 Net PHI2_c: 14 loads, 5 rising, 9 falling (Driver: PIO PHI2 ) Net RCLK_c: 32 loads, 32 rising, 0 falling (Driver: PIO RCLK ) Net nCRAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCRAS ) Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) Number of Clock Enables: 5 Net XOR8MEG18: 3 loads, 3 LSLICEs Net N_24: 1 loads, 1 LSLICEs Net N_26: 1 loads, 1 LSLICEs Net N_153_i: 2 loads, 2 LSLICEs Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs Number of LSRs: 5 Net RA10s_i: 1 loads, 1 LSLICEs Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs Net RASr2: 1 loads, 1 LSLICEs Net Ready_fast: 7 loads, 7 LSLICEs Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 Page 1 Design: RAM2GS Date: 01/06/24 06:24:57 Design Summary (cont) --------------------- Top 10 highest fanout non-clock nets: Net Ready: 18 loads Net InitReady: 17 loads Net S[1]: 17 loads Net CO0: 16 loads Net RASr2: 13 loads Net nRowColSel: 12 loads Net Din_c[5]: 10 loads Net Din_c[3]: 9 loads Net IS[0]: 9 loads Net IS[1]: 8 loads Number of warnings: 0 Number of errors: 0 Design Errors/Warnings ---------------------- No errors or warnings present. IO (PIO) Attributes ------------------- +---------------------+-----------+-----------+------------+------------+ | IO Name | Direction | Levelmode | IO | FIXEDDELAY | | | | IO_TYPE | Register | | +---------------------+-----------+-----------+------------+------------+ | RD[0] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[0] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | PHI2 | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | UFMSDO | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | UFMSDI | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | UFMCLK | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nUFMCS | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RDQML | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RDQMH | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRCAS | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRRAS | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRWE | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RCKE | OUTPUT | LVCMOS33 | | | Page 2 Design: RAM2GS Date: 01/06/24 06:24:57 IO (PIO) Attributes (cont) -------------------------- +---------------------+-----------+-----------+------------+------------+ | RCLK | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nRCS | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[7] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[6] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[5] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[4] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[3] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[2] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RD[1] | BIDIR | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[11] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[10] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[9] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[8] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[7] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[6] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[5] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[4] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[3] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[2] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[1] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RA[0] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RBA[1] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | RBA[0] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | LED | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nFWE | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nCRAS | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | nCCAS | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[7] | OUTPUT | LVCMOS33 | | | Page 3 Design: RAM2GS Date: 01/06/24 06:24:57 IO (PIO) Attributes (cont) -------------------------- +---------------------+-----------+-----------+------------+------------+ | Dout[6] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[5] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[4] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[3] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[2] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Dout[1] | OUTPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[7] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[6] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[5] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[4] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[3] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[2] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[1] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | Din[0] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | CROW[1] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | CROW[0] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[9] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[8] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[7] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[6] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[5] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[4] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[3] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[2] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[1] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ | MAin[0] | INPUT | LVCMOS33 | | | +---------------------+-----------+-----------+------------+------------+ Page 4 Design: RAM2GS Date: 01/06/24 06:24:57 Removed logic ------------- Block GSR_INST undriven or does not drive anything - clipped. Signal nCRAS_c_i was merged into signal nCRAS_c Signal nFWE_c_i was merged into signal nFWE_c Signal nCRAS_c_i_0 was merged into signal nCRAS_c Signal nCCAS_c_i was merged into signal nCCAS_c Signal Ready_fast_i was merged into signal Ready_fast Signal RASr2_i was merged into signal RASr2 Signal XOR8MEG.CN was merged into signal PHI2_c Signal GND undriven or does not drive anything - clipped. Signal VCC undriven or does not drive anything - clipped. Signal FS_cry[2] undriven or does not drive anything - clipped. Signal FS_cry[4] undriven or does not drive anything - clipped. Signal FS_cry[6] undriven or does not drive anything - clipped. Signal FS_cry[8] undriven or does not drive anything - clipped. Signal FS_cry[10] undriven or does not drive anything - clipped. Signal FS_cry[12] undriven or does not drive anything - clipped. Signal FS_cry[14] undriven or does not drive anything - clipped. Signal FS_cry_0_COUT1[16] undriven or does not drive anything - clipped. Signal FS_cry[16] undriven or does not drive anything - clipped. Signal FS_cry[0] undriven or does not drive anything - clipped. Block nCRAS_pad_RNIBPVB was optimized away. Block nFWE_pad_RNI420B was optimized away. Block RASr_RNO was optimized away. Block nCCAS_pad_RNISUR8 was optimized away. Block Ready_fast_RNI29NA was optimized away. Block S_RNO[1] was optimized away. Block XOR8MEG.CN was optimized away. Block GND was optimized away. Block VCC was optimized away. Run Time and Memory Usage ------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 50 MB Page 5 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.