Map TRACE Report
Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Tue Aug 15 05:03:21 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1_map.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,3
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "RCLK_c" 283.768000 MHz (213 errors)
383 items scored, 213 timing errors detected.
Warning: 116.104MHz is the maximum frequency for this preference.
FREQUENCY NET "PHI2_c" 120.077000 MHz (97 errors)
106 items scored, 97 timing errors detected.
Warning: 42.739MHz is the maximum frequency for this preference.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
383 items scored, 213 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 5.089ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_610__i14 (from RCLK_c +)
Destination: FF Data in n8MEGEN_418 (to RCLK_c +)
Delay: 8.369ns (24.4% logic, 75.6% route), 5 logic levels.
Constraint Details:
8.369ns physical path delay SLICE_1 to SLICE_56 exceeds
3.524ns delay constraint less
0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns
Physical Path Details:
Data path SLICE_1 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c)
ROUTE 5 e 1.441 SLICE_1.Q0 to SLICE_90.C1 FS_14
CTOF_DEL --- 0.371 SLICE_90.C1 to SLICE_90.F1 SLICE_90
ROUTE 1 e 1.441 SLICE_90.F1 to SLICE_75.B0 n2328
CTOF_DEL --- 0.371 SLICE_75.B0 to SLICE_75.F0 SLICE_75
ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_87.B1 n2214
CTOF_DEL --- 0.371 SLICE_87.B1 to SLICE_87.F1 SLICE_87
ROUTE 1 e 0.561 SLICE_87.F1 to SLICE_87.A0 n7
CTOF_DEL --- 0.371 SLICE_87.A0 to SLICE_87.F0 SLICE_87
ROUTE 1 e 1.441 SLICE_87.F0 to SLICE_56.CE RCLK_c_enable_11 (to RCLK_c)
--------
8.369 (24.4% logic, 75.6% route), 5 logic levels.
Warning: 116.104MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
106 items scored, 97 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i0 (from PHI2_c +)
Destination: FF Data in C1Submitted_406 (to PHI2_c -)
Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels.
Constraint Details:
11.061ns physical path delay SLICE_88 to SLICE_14 exceeds
4.164ns delay constraint less
0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns
Physical Path Details:
Data path SLICE_88 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 SLICE_88.CLK to SLICE_88.Q0 SLICE_88 (from PHI2_c)
ROUTE 1 e 1.441 SLICE_88.Q0 to SLICE_97.D0 Bank_0
CTOF_DEL --- 0.371 SLICE_97.D0 to SLICE_97.F0 SLICE_97
ROUTE 1 e 1.441 SLICE_97.F0 to SLICE_81.B0 n2314
CTOF_DEL --- 0.371 SLICE_81.B0 to SLICE_81.F0 SLICE_81
ROUTE 1 e 1.441 SLICE_81.F0 to SLICE_18.B1 n26
CTOF_DEL --- 0.371 SLICE_18.B1 to SLICE_18.F1 SLICE_18
ROUTE 8 e 1.441 SLICE_18.F1 to SLICE_89.B0 n1326
CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89
ROUTE 1 e 1.441 SLICE_89.F0 to SLICE_79.C0 n1280
CTOF_DEL --- 0.371 SLICE_79.C0 to SLICE_79.F0 SLICE_79
ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_14.LSR C1Submitted_N_237 (to PHI2_c)
--------
11.061 (21.8% logic, 78.2% route), 6 logic levels.
Warning: 42.739MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.104 MHz| 5 *
| | |
FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 42.739 MHz| 6 *
| | |
----------------------------------------------------------------------------
2 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n1326 | 8| 96| 30.97%
| | |
n26 | 1| 72| 23.23%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Setup):
---------------
Timing errors: 310 Score: 1346529
Cumulative negative slack: 874289
Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Tue Aug 15 05:03:21 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1_map.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors) 383 items scored, 0 timing errors detected.
FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors) 106 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
383 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i4 (from RCLK_c +)
Destination: FF Data in IS_FSM__i5 (to RCLK_c +)
Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels.
Constraint Details:
0.325ns physical path delay SLICE_100 to SLICE_100 meets
-0.017ns M_HLD and
0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
Physical Path Details:
Data path SLICE_100 to SLICE_100:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 SLICE_100.CLK to SLICE_100.Q0 SLICE_100 (from RCLK_c)
ROUTE 1 e 0.199 SLICE_100.Q0 to SLICE_100.M1 n736 (to RCLK_c)
--------
0.325 (38.8% logic, 61.2% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
106 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.430ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted_406 (from PHI2_c -)
Destination: FF Data in C1Submitted_406 (to PHI2_c -)
Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay SLICE_14 to SLICE_14 meets
-0.019ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
Physical Path Details:
Data path SLICE_14 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.C0 C1Submitted
CTOF_DEL --- 0.074 SLICE_14.C0 to SLICE_14.F0 SLICE_14
ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n6_adj_3 (to PHI2_c)
--------
0.411 (51.3% logic, 48.7% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.342 ns| 1
| | |
FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.430 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 310 (setup), 0 (hold)
Score: 1346529 (setup), 0 (hold)
Cumulative negative slack: 874289 (874289+0)
--------------------------------------------------------------------------------
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