synthesis -f "RAM2GS_LCMXO256C_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Tue Aug 15 05:03:20 2023 Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml Synthesis options: The -a option is MachXO. The -s option is 3. The -t option is TQFP100. The -d option is LCMXO256C. Using package TQFP100. Using performance grade 3. ########################################################## ### Lattice Family : MachXO ### Device : LCMXO256C ### Package : TQFP100 ### Speed : 3 ########################################################## Optimization goal = Balanced Top-level module name = RAM2GS. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) -p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) -p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added) -p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v NGD file = RAM2GS_LCMXO256C_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 Top module name (Verilog): RAM2GS Last elaborated design is RAM2GS() Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Top-level module name = RAM2GS. original encoding -> new encoding (one-hot encoding) 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks Results of NGD DRC are available in RAM2GS_drc.log. Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... DRC complete with no errors or warnings Design Results: 318 blocks expanded completed the first expansion All blocks are expanded and NGD expansion is successful. Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. ################### Begin Area Report (RAM2GS)###################### Number of register bits => 102 of 490 (20 % ) BB => 8 CCU2 => 9 FD1P3AX => 28 FD1P3AY => 3 FD1P3IX => 2 FD1S3AX => 47 FD1S3AY => 1 FD1S3IX => 16 FD1S3JX => 5 GSR => 1 IB => 26 INV => 3 OB => 33 ORCALUT4 => 127 PFUMX => 6 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 4 Net : RCLK_c, loads : 62 Net : PHI2_c, loads : 11 Net : nCCAS_c, loads : 2 Net : nCRAS_c, loads : 2 Clock Enable Nets Number of Clock Enables: 13 Top 10 highest fanout Clock Enables: Net : RCLK_c_enable_23, loads : 16 Net : RCLK_c_enable_4, loads : 3 Net : PHI2_N_120_enable_6, loads : 3 Net : RCLK_c_enable_24, loads : 2 Net : RCLK_c_enable_12, loads : 1 Net : PHI2_N_120_enable_1, loads : 1 Net : PHI2_N_120_enable_4, loads : 1 Net : RCLK_c_enable_3, loads : 1 Net : PHI2_N_120_enable_5, loads : 1 Net : RCLK_c_enable_11, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : InitReady, loads : 17 Net : Ready, loads : 17 Net : RCLK_c_enable_23, loads : 16 Net : nCRAS_N_9, loads : 15 Net : RASr2, loads : 13 Net : nRowColSel, loads : 13 Net : n2477, loads : 13 Net : MAin_c_0, loads : 12 Net : nRowColSel_N_35, loads : 12 Net : Din_c_6, loads : 11 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk3 [get_nets nCCAS_c] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk2 [get_nets nCRAS_c] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * | | | create_clock -period 5.000000 -name | | | clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * | | | -------------------------------------------------------------------------------- 2 constraints not met. Peak Memory Usage: 50.672 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.516 secs -------------------------------------------------------------- map -a "MachXO" -p LCMXO256C -t TQFP100 -s 3 -oc Commercial "RAM2GS_LCMXO256C_impl1.ngd" -o "RAM2GS_LCMXO256C_impl1_map.ncd" -pr "RAM2GS_LCMXO256C_impl1.prf" -mp "RAM2GS_LCMXO256C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf" -c 0 map: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: RAM2GS_LCMXO256C_impl1.ngd Picdevice="LCMXO256C" Pictype="TQFP100" Picspeed=3 Remove unused logic Do not produce over sized NCDs. Part used: LCMXO256CTQFP100, Performance used: 3. Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Running general design DRC... Removing unused logic... Optimizing... Design Summary: Number of PFU registers: 102 out of 256 (40%) Number of SLICEs: 71 out of 128 (55%) SLICEs as Logic/ROM: 71 out of 128 (55%) SLICEs as RAM: 0 out of 64 (0%) SLICEs as Carry: 9 out of 128 (7%) Number of LUT4s: 142 out of 256 (55%) Number used as logic LUTs: 124 Number used as distributed RAM: 0 Number used as ripple logic: 18 Number used as shift registers: 0 Number of external PIOs: 67 out of 78 (86%) Number of GSRs: 0 out of 1 (0%) JTAG used : No Readback used : No Oscillator used : No Startup used : No Number of TSALL: 0 out of 1 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) Number of Clock Enables: 13 Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs Net RCLK_c_enable_4: 3 loads, 3 LSLICEs Net RCLK_c_enable_23: 8 loads, 8 LSLICEs Net RCLK_c_enable_12: 1 loads, 1 LSLICEs Net RCLK_c_enable_3: 1 loads, 1 LSLICEs Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs Net RCLK_c_enable_24: 2 loads, 2 LSLICEs Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs Net Ready_N_292: 1 loads, 1 LSLICEs Net RCLK_c_enable_11: 1 loads, 1 LSLICEs Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs Net RCLK_c_enable_25: 1 loads, 1 LSLICEs Number of LSRs: 9 Net RASr2: 1 loads, 1 LSLICEs Net Ready: 7 loads, 7 LSLICEs Net C1Submitted_N_237: 2 loads, 2 LSLICEs Net n2469: 1 loads, 1 LSLICEs Net nRowColSel_N_35: 1 loads, 1 LSLICEs Net n1846: 2 loads, 2 LSLICEs Net LEDEN_N_82: 1 loads, 1 LSLICEs Net nRowColSel_N_34: 1 loads, 1 LSLICEs Net nRWE_N_177: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net Ready: 23 loads Net InitReady: 17 loads Net RASr2: 14 loads Net nRowColSel: 13 loads Net MAin_c_0: 12 loads Net nRowColSel_N_35: 12 loads Net Din_c_3: 11 loads Net Din_c_6: 11 loads Net MAin_c_1: 11 loads Net Din_c_4: 10 loads Number of warnings: 0 Number of errors: 0 Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 29 MB Dumping design to file RAM2GS_LCMXO256C_impl1_map.ncd. ncd2vdb "RAM2GS_LCMXO256C_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO256C_impl1_map.vdb" Loading device for application ncd2vdb from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. ncd2eqn "RAM2GS_LCMXO256C_impl1_map.ncd" ncd2eqn: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Start loading RAM2GS_LCMXO256C_impl1_map.ncd. Loading design for application ncd2eqn from file RAM2GS_LCMXO256C_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application ncd2eqn from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Finish loading RAM2GS_LCMXO256C_impl1_map.ncd. ncd2eqn runs successfully. trce -f "RAM2GS_LCMXO256C_impl1.mt" -o "RAM2GS_LCMXO256C_impl1.tw1" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.prf" trce: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 Tue Aug 15 05:03:21 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf Design file: ram2gs_lcmxo256c_impl1_map.ncd Preference file: ram2gs_lcmxo256c_impl1.prf Device,speed: LCMXO256C,3 Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 310 Score: 1346529 Cumulative negative slack: 874289 Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Tue Aug 15 05:03:21 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf Design file: ram2gs_lcmxo256c_impl1_map.ncd Preference file: ram2gs_lcmxo256c_impl1.prf Device,speed: LCMXO256C,M Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 310 (setup), 0 (hold) Score: 1346529 (setup), 0 (hold) Cumulative negative slack: 874289 (874289+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 32 MB ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO256C_impl1_mapvo.vo" -w -neg ldbanno: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file. Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format. Writing Verilog netlist to file RAM2GS_LCMXO256C_impl1_mapvo.vo Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvo.sdf Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 29 MB ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO256C_impl1_mapvho.vho" -w -neg ldbanno: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file. Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format. Writing VHDL netlist to file RAM2GS_LCMXO256C_impl1_mapvho.vho Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvho.sdf Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 29 MB mpartrce -p "RAM2GS_LCMXO256C_impl1.p2t" -f "RAM2GS_LCMXO256C_impl1.p3t" -tf "RAM2GS_LCMXO256C_impl1.pt" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" Tue Aug 15 05:03:23 2023 PAR: Place And Route Diamond (64-bit) 3.12.1.454. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf Preference file: RAM2GS_LCMXO256C_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 67/79 84% used 67/78 85% bonded SLICE 71/128 55% used Number of Signals: 262 Number of Connections: 662 Pin Constraint Summary: 67 out of 67 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: RCLK_c (driver: RCLK, clk load #: 40) PHI2_c (driver: PHI2, clk load #: 13) The following 1 signal is selected to use the secondary clock routing resources: nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) No signal is selected as Global Set/Reset. Starting Placer Phase 0. ........ Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. .............. Placer score = 831129. Finished Placer Phase 1. REAL time: 5 secs Starting Placer Phase 2. . Placer score = 828350 Finished Placer Phase 2. REAL time: 5 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 4 (25%) General PIO: 1 out of 80 (1%) Global Clocks: PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40 PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0 PRIMARY : 2 out of 4 (50%) SECONDARY: 1 out of 4 (25%) --------------- End of Clock Report --------------- I/O Usage Summary (final): 67 out of 79 (84.8%) PIO sites used. 67 out of 78 (85.9%) bonded PIO sites used. Number of PIO comps: 67; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 36 / 41 ( 87%) | 3.3V | - | - | | 1 | 31 / 37 ( 83%) | 3.3V | - | - | +----------+----------------+------------+------------+------------+ Total placer CPU time: 4 secs Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. 0 connections routed; 662 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 5 secs Start NBR router at 05:03:28 08/15/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 05:03:28 08/15/23 Start NBR section for initial routing at 05:03:28 08/15/23 Level 1, iteration 1 0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs Level 2, iteration 1 3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs Level 3, iteration 1 6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs Level 4, iteration 1 17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 05:03:28 08/15/23 Level 4, iteration 1 12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs Level 4, iteration 2 6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs Level 4, iteration 3 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs Level 4, iteration 4 3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs Level 4, iteration 5 3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs Level 4, iteration 6 1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs Level 4, iteration 7 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs Level 4, iteration 8 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs Level 4, iteration 9 1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs Level 4, iteration 10 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs Start NBR section for re-routing at 05:03:29 08/15/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs Start NBR section for post-routing at 05:03:29 08/15/23 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 256 (38.67%) Estimated worst slack : -10.044ns Timing score : 913247 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 5 secs Total REAL time: 6 secs Completely routed. End of route. 662 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 913247 Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = -10.044 PAR_SUMMARY::Timing score> = 913.247 PAR_SUMMARY::Worst slack> = 0.273 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 5 secs Total REAL time to completion: 6 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 trce -f "RAM2GS_LCMXO256C_impl1.pt" -o "RAM2GS_LCMXO256C_impl1.twr" "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf" trce: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 Tue Aug 15 05:03:29 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf Design file: ram2gs_lcmxo256c_impl1.ncd Preference file: ram2gs_lcmxo256c_impl1.prf Device,speed: LCMXO256C,3 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 326 Score: 913247 Cumulative negative slack: 638389 Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Tue Aug 15 05:03:29 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf Design file: ram2gs_lcmxo256c_impl1.ncd Preference file: ram2gs_lcmxo256c_impl1.prf Device,speed: LCMXO256C,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 326 (setup), 0 (hold) Score: 913247 (setup), 0 (hold) Cumulative negative slack: 638389 (638389+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 31 MB iotiming "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf" I/O Timing Report: : version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application iotiming from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Running Performance Grade: 3 Computing Setup Time ... Computing Max Clock to Output Delay ... Computing Hold Time ... Computing Min Clock to Output Delay ... Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 4 Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Running Performance Grade: 4 Computing Setup Time ... Computing Max Clock to Output Delay ... Computing Hold Time ... Computing Min Clock to Output Delay ... Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 5 Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Running Performance Grade: 5 Computing Setup Time ... Computing Max Clock to Output Delay ... Computing Hold Time ... Computing Min Clock to Output Delay ... Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: M Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Running Performance Grade: M Computing Setup Time ... Computing Max Clock to Output Delay ... Computing Hold Time ... Computing Min Clock to Output Delay ... Done. tmcheck -par "RAM2GS_LCMXO256C_impl1.par" bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd. Design name: RAM2GS NCD version: 3.3 Vendor: LATTICE Device: LCMXO256C Package: TQFP100 Performance: 3 Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.19. Performance Hardware Data Status: Version 1.124. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from RAM2GS_LCMXO256C_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | INBUF | ON** | +---------------------------------+---------------------------------+ | ES | No** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit". Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 44 MB ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed" -comment "RAM2GS_LCMXO256C_impl1.alt" Lattice Diamond Deployment Tool 3.12 Command Line Loading Programmer Device Database... Generating JED..... Device Name: LCMXO256C-XXT100 Reading Input File: RAM2GS_LCMXO256C_impl1.bit Output File: RAM2GS_LCMXO256C_impl1.jed Comment file RAM2GS_LCMXO256C_impl1.alt. Generating JEDEC..... File RAM2GS_LCMXO256C_impl1.jed generated successfully. Lattice Diamond Deployment Tool has exited successfully.