// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454

// ldbanno -n Verilog -o LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd 
// Netlist created on Sat Aug 19 21:54:57 2023
// Netlist written on Sat Aug 19 21:54:59 2023
// Design is for device LCMXO2-640HC
// Design is for package TQFP100
// Design is for performance grade 4

`timescale 1 ns / 1 ps

module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, 
                RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML );
  input  PHI2;
  input  [9:0] MAin;
  input  [1:0] CROW;
  input  [7:0] Din;
  input  nCCAS, nCRAS, nFWE, RCLK;
  output [7:0] Dout;
  output LED;
  output [1:0] RBA;
  output [11:0] RA;
  output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML;
  inout  [7:0] RD;
  wire   \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] , 
         \FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] , 
         \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , 
         \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , 
         \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , 
         \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , 
         \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , 
         \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_304, 
         CmdEnable17_5, CmdEnable17_4, ADWR_7, CmdEnable16, CmdEnable17, 
         un1_ADWR, ADSubmitted, ADSubmitted_r, PHI2_c, CmdEnable16_5, 
         CmdEnable16_4, C1WR_7, C1WR_2, C1Submitted, C1Submitted_s, nCCAS_c, 
         nCCAS_c_i, CASr, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_79_i, 
         Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, CmdEnable_s, XOR8MEG11, 
         \Din_c[1] , CmdLEDEN, XOR8MEG14, N_75, LEDEN, CmdLEDEN_4, XOR8MEG18, 
         CmdUFMShift, CmdUFMShift_3, CmdUFMShift_fast, CmdUFMShift_3_fast, 
         \Din_c[0] , CmdUFMWrite_2, CmdUFMWrite, CmdUFMWrite_3, \Din_c[7] , 
         \Din_c[6] , \Din_c[5] , \Din_c[4] , CmdValid_r, CmdValid, CMDWR_2, 
         N_36_fast, CmdValid_fast, Cmdn8MEGEN, n8MEGEN, N_93, Cmdn8MEGEN_4, 
         nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, Ready, N_250, \IS[0] , 
         N_60_i_i, RA10s_i, \IS[2] , \IS[1] , N_57_i_i, IS_n1_0_x2, N_253_i, 
         N_58_i_i, N_45, N_116, InitReady3_0_a3_2, InitReady, InitReady3, 
         N_487_0, \wb_dato[1] , LEDEN_6, un1_FS_38_i, CBR, nCRAS_c_i_0, RASr, 
         LED_c, nRowColSel, \RowA[4] , \MAin_c[4] , PHI2r, \RA_c[4] , RASr3, 
         un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, PHI2r2, N_41, RCKEEN_8_u_1_0, 
         RCKEEN_8_u_0_0, RCKEEN_8, RCKEEN, \Bank[7] , \Bank[6] , \Bank[5] , 
         \Bank[2] , RCKE_2, RCKE_c, un1_Bank_1_4, N_258, N_486_0, Ready_fast, 
         Ready_0_sqmuxa, N_489_0, \MAin_c[1] , \MAin_c[0] , \RowAd_0[1] , 
         \RowAd_0[0] , \RowA[0] , \RowA[1] , \MAin_c[3] , \MAin_c[2] , 
         \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \RowA[3] , \MAin_c[5] , 
         \RowAd_0[5] , \RowAd_0[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] , 
         \RowAd_0[7] , \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] , 
         \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] , 
         nRRAS_5_u_i_0, XOR8MEG9_1, un1_Din_2, XOR8MEG_3_u_0_bm, XOR8MEG, 
         XOR8MEG_3, \wb_dato[0] , n8MEGEN_6, wb_rst10, CASr3, N_265, 
         nRowColSel_0_0, nRRAS_0_sqmuxa, wb_rst11, \wb_adr[0] , N_181, 
         \wb_dati[7] , \wb_adr_cnst_m2[0] , \wb_adr_5[1] , \wb_adr_5[0] , 
         un1_wb_rst14_i, \wb_adr[1] , \wb_adr[2] , \wb_adr_5[3] , 
         \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] , \wb_adr_5[5] , \wb_adr_5[4] , 
         \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , \wb_adr_5[6] , \wb_adr[7] , 
         un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, N_245, N_102_2, 
         un1_wb_cyc_stb_1_sqmuxa_0, un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i, 
         wb_cyc_stb, \wb_dati_5_1_iv_0_a3_0_0[1] , \wb_dati_5_1_iv_0_0[1] , 
         N_128, N_94, wb_we, \wb_dati_5_0_iv_0_a3_1[0] , N_119, \wb_dati_5[1] , 
         \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] , un1_wb_we95_1, 
         \wb_dati_5_1_iv_0_0[3] , N_240, N_49, \wb_dati_5[3] , \wb_dati_5[2] , 
         \wb_dati[2] , \wb_dati[3] , \wb_dati[4] , \wb_dati_5_1_iv_0_1[4] , 
         un1_wb_rst11_1_s6_1, \wb_dati_5[5] , \wb_dati_5[4] , \wb_dati[5] , 
         \wb_dati_5_1_iv_0_a3_0_0[7] , \wb_dati_5_1_iv_0_1[7] , N_89, 
         \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] , \wb_dati_5[6] , \wb_dati[6] , 
         wb_req, un1_FS_37_i_0, N_78_i, wb_reqe_0, PHI2r3, wb_rst, wb_rste_0, 
         wb_we95, un1_FS_29, un1_wb_adr_0_sqmuxa_3, un1_wb_adr_0_sqmuxa_2, 
         CmdUFMData, wb_we_0, un1_PHI2r3_0, N_102, un1_FS_11, wb_ack, 
         d_N_5_mux, N_254, N_39, nRCAS_0_sqmuxa_1, nRWE_0io_RNO_1, N_37_i_1, 
         CBR_fast, N_37_i, un1_FS_40_1_0_1, un1_FS_40_1_0, nRCAS_0io_RNO_0, 
         N_28_i_1, N_249_i, N_230, nRWE_0io_RNO_4, nRWE_0io_RNO_3, N_131, N_85, 
         N_248, XOR8MEG14_1, \Din_c[3] , CmdUFMData_1_sqmuxa, 
         \wb_dati_5_1_iv_0_a3_0[6] , N_246, N_98, \wb_dati_5_1_iv_0_a3_0[3] , 
         N_25, N_59, \wb_dati_5_1_iv_0_a3_2_0[1] , 
         \wb_dati_5_1_iv_0_a3_1_1[4] , \wb_dati_5_1_iv_0_a3_3_0[7] , N_242, 
         N_91, wb_we95_0_tz_tz_tz, un1_FS_20_3, N_120, N_228, wb_we113_i, 
         un1_FS_40_1_1_1, un1_FS_40_1_1_tz, N_139, N_136, N_28_i_sn, N_25_i, 
         FWEr_fast, N_28_i, N_233, N_102_1, ADWR_5, ADWR_4, C1WR_0, \Bank[1] , 
         \Bank[0] , un1_Bank_1_3, \Bank[4] , \Bank[3] , G_8_0_a3_0_0, 
         nRWE_0io_RNO_2, \Din_c[2] , \RA_c[9] , RDQMH_c, \RA_c[7] , \RA_c[0] , 
         RDQML_c, \RA_c[1] , \RA_c[8] , \RA_c[2] , \RA_c[6] , \RA_c[3] , 
         \RA_c[5] , RA11d_0, \CROW_c[0] , \CROW_c[1] , \RBAd_0[1] , 
         \RBAd_0[0] , \RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, 
         \RD_in[7] , \WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , 
         \RD_in[4] , \WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , 
         \RD_in[1] , \WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , 
         VCCI;

  SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ), 
    .Q1(\FS[0] ), .FCO(\FS_cry[0] ));
  SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c), 
    .FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] ));
  SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ), 
    .DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), 
    .Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] ));
  SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), 
    .DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), 
    .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] ));
  SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), 
    .DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), 
    .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] ));
  SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), 
    .DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), 
    .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] ));
  SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), 
    .DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), 
    .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] ));
  SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), 
    .DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), 
    .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] ));
  SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), 
    .DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), 
    .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] ));
  SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), 
    .DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), 
    .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
  SLICE_10 SLICE_10( .D1(N_304), .C1(CmdEnable17_5), .B1(CmdEnable17_4), 
    .A1(ADWR_7), .D0(CmdEnable16), .C0(CmdEnable17), .B0(un1_ADWR), 
    .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c), .F0(ADSubmitted_r), 
    .Q0(ADSubmitted), .F1(CmdEnable17));
  SLICE_11 SLICE_11( .D1(CmdEnable16_5), .C1(CmdEnable16_4), .B1(C1WR_7), 
    .A1(C1WR_2), .C0(CmdEnable16), .B0(un1_ADWR), .A0(C1Submitted), 
    .DI0(C1Submitted_s), .CLK(PHI2_c), .F0(C1Submitted_s), .Q0(C1Submitted), 
    .F1(CmdEnable16));
  SLICE_12 SLICE_12( .A0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c), 
    .F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2));
  SLICE_16 SLICE_16( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0), 
    .B0(\S[1] ), .A0(CO0), .DI0(N_79_i), .LSR(RASr2), .CLK(RCLK_c), 
    .F0(N_79_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
  SLICE_17 SLICE_17( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted), 
    .C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s), 
    .M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
  SLICE_18 SLICE_18( .C1(XOR8MEG11), .B1(\Din_c[1] ), .A1(CmdLEDEN), 
    .C0(XOR8MEG14), .B0(N_75), .A0(LEDEN), .DI0(CmdLEDEN_4), .CE(XOR8MEG18), 
    .CLK(PHI2_c), .F0(CmdLEDEN_4), .Q0(CmdLEDEN), .F1(N_75));
  SLICE_20 SLICE_20( .D0(XOR8MEG14), .C0(XOR8MEG11), .B0(\Din_c[1] ), 
    .A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c), 
    .F0(CmdUFMShift_3), .Q0(CmdUFMShift));
  SLICE_21 SLICE_21( .D0(XOR8MEG14), .C0(XOR8MEG11), .B0(\Din_c[1] ), 
    .A0(CmdUFMShift_fast), .DI0(CmdUFMShift_3_fast), .CE(XOR8MEG18), 
    .CLK(PHI2_c), .F0(CmdUFMShift_3_fast), .Q0(CmdUFMShift_fast));
  SLICE_22 SLICE_22( .B1(\Din_c[1] ), .A1(\Din_c[0] ), .D0(XOR8MEG14), 
    .C0(XOR8MEG11), .B0(CmdUFMWrite_2), .A0(CmdUFMWrite), .DI0(CmdUFMWrite_3), 
    .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3), .Q0(CmdUFMWrite), 
    .F1(CmdUFMWrite_2));
  SLICE_23 SLICE_23( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ), 
    .A1(\Din_c[4] ), .C0(XOR8MEG14), .B0(XOR8MEG11), .A0(XOR8MEG18), 
    .DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid), 
    .F1(XOR8MEG11));
  SLICE_24 SLICE_24( .C1(CmdEnable), .B1(CMDWR_2), .A1(C1WR_7), .C0(XOR8MEG14), 
    .B0(XOR8MEG11), .A0(XOR8MEG18), .DI0(N_36_fast), .CLK(PHI2_c), 
    .F0(N_36_fast), .Q0(CmdValid_fast), .F1(XOR8MEG18));
  SLICE_25 SLICE_25( .C1(XOR8MEG11), .B1(\Din_c[0] ), .A1(Cmdn8MEGEN), 
    .C0(n8MEGEN), .B0(XOR8MEG14), .A0(N_93), .DI0(Cmdn8MEGEN_4), 
    .CE(XOR8MEG18), .CLK(PHI2_c), .F0(Cmdn8MEGEN_4), .Q0(Cmdn8MEGEN), 
    .F1(N_93));
  SLICE_26 SLICE_26( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i), 
    .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i));
  SLICE_28 SLICE_28( .D1(Ready), .C1(N_250), .B1(\IS[3] ), .A1(\IS[0] ), 
    .C0(Ready), .B0(N_250), .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c), 
    .F0(N_60_i_i), .Q0(\IS[0] ), .F1(RA10s_i));
  SLICE_29 SLICE_29( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ), 
    .A0(\IS[0] ), .DI1(N_57_i_i), .DI0(IS_n1_0_x2), .CE(N_253_i), .CLK(RCLK_c), 
    .F0(IS_n1_0_x2), .Q0(\IS[1] ), .F1(N_57_i_i), .Q1(\IS[2] ));
  SLICE_30 SLICE_30( .B1(\IS[2] ), .A1(\IS[1] ), .D0(\IS[0] ), .C0(\IS[1] ), 
    .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_58_i_i), .CE(N_253_i), .CLK(RCLK_c), 
    .F0(N_58_i_i), .Q0(\IS[3] ), .F1(N_45));
  SLICE_31 SLICE_31( .D1(N_116), .C1(InitReady3_0_a3_2), .B1(\FS[14] ), 
    .A1(\FS[13] ), .B0(InitReady), .A0(InitReady3), .DI0(N_487_0), 
    .CLK(RCLK_c), .F0(N_487_0), .Q0(InitReady), .F1(InitReady3));
  SLICE_32 SLICE_32( .C0(\wb_dato[1] ), .B0(InitReady), .A0(CmdLEDEN), 
    .DI0(LEDEN_6), .CE(un1_FS_38_i), .CLK(RCLK_c), .F0(LEDEN_6), .Q0(LEDEN));
  SLICE_34 SLICE_34( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c), 
    .DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr), 
    .F1(LED_c), .Q1(RASr2));
  SLICE_35 SLICE_35( .B1(\FS[7] ), .A1(\FS[3] ), .C0(nRowColSel), 
    .B0(\RowA[4] ), .A0(\MAin_c[4] ), .M1(PHI2r), .M0(RASr2), .CLK(RCLK_c), 
    .F0(\RA_c[4] ), .Q0(RASr3), .F1(un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1), 
    .Q1(PHI2r2));
  SLICE_36 SLICE_36( .D1(N_41), .C1(InitReady), .B1(RASr2), .A1(Ready), 
    .D0(Ready), .C0(RCKEEN_8_u_1_0), .B0(RCKEEN_8_u_0_0), .A0(CBR), 
    .DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN), 
    .F1(RCKEEN_8_u_0_0));
  SLICE_37 SLICE_37( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ), 
    .A1(\Bank[2] ), .D0(RCKEEN), .C0(RASr3), .B0(RASr2), .A0(RASr), 
    .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2), .Q0(RCKE_c), .F1(un1_Bank_1_4));
  SLICE_38 SLICE_38( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady), 
    .C0(N_258), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_486_0), 
    .CLK(RCLK_c), .F0(N_486_0), .Q0(Ready), .F1(N_258));
  SLICE_39 SLICE_39( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_258), 
    .A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_489_0), 
    .CLK(RCLK_c), .F0(N_489_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa));
  SLICE_40 SLICE_40( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast), 
    .A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c), 
    .F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] ));
  SLICE_41 SLICE_41( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast), 
    .A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c), 
    .F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] ));
  SLICE_42 SLICE_42( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast), 
    .A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c), 
    .F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] ));
  SLICE_43 SLICE_43( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast), 
    .A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c), 
    .F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] ));
  SLICE_44 SLICE_44( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast), 
    .A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c), 
    .F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] ));
  SLICE_45 SLICE_45( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(N_41), 
    .B0(\S[1] ), .A0(CO0), .DI0(N_41), .LSR(RASr2), .CLK(RCLK_c), .F0(N_41), 
    .Q0(\S[1] ), .F1(nRRAS_5_u_i_0));
  SLICE_46 SLICE_46( .D1(\Din_c[1] ), .C1(\Din_c[0] ), .B1(XOR8MEG9_1), 
    .A1(LEDEN), .C0(un1_Din_2), .B0(XOR8MEG_3_u_0_bm), .A0(XOR8MEG), 
    .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(XOR8MEG_3), 
    .Q0(XOR8MEG), .F1(XOR8MEG_3_u_0_bm));
  SLICE_47 SLICE_47( .D1(InitReady), .C1(\FS[17] ), .B1(\FS[16] ), 
    .A1(\FS[15] ), .C0(\wb_dato[0] ), .B0(InitReady), .A0(Cmdn8MEGEN), 
    .DI0(n8MEGEN_6), .CE(un1_FS_38_i), .CLK(RCLK_c), .F0(n8MEGEN_6), 
    .Q0(n8MEGEN), .F1(wb_rst10));
  SLICE_48 SLICE_48( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ), 
    .C0(Ready), .B0(N_265), .A0(CO0), .DI0(nRowColSel_0_0), 
    .LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel), 
    .F1(N_265));
  SLICE_49 SLICE_49( .D1(wb_rst11), .C1(\wb_adr[0] ), .B1(N_181), 
    .A1(InitReady), .C0(\wb_dati[7] ), .B0(\wb_adr_cnst_m2[0] ), 
    .A0(InitReady), .DI1(\wb_adr_5[1] ), .DI0(\wb_adr_5[0] ), 
    .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[0] ), .Q0(\wb_adr[0] ), 
    .F1(\wb_adr_5[1] ), .Q1(\wb_adr[1] ));
  SLICE_50 SLICE_50( .B1(\wb_adr[2] ), .A1(InitReady), .B0(\wb_adr[1] ), 
    .A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ), 
    .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ), 
    .F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] ));
  SLICE_51 SLICE_51( .C1(wb_rst11), .B1(\wb_adr[4] ), .A1(InitReady), 
    .C0(wb_rst11), .B0(\wb_adr[3] ), .A0(InitReady), .DI1(\wb_adr_5[5] ), 
    .DI0(\wb_adr_5[4] ), .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[4] ), 
    .Q0(\wb_adr[4] ), .F1(\wb_adr_5[5] ), .Q1(\wb_adr[5] ));
  SLICE_52 SLICE_52( .B1(\wb_adr[6] ), .A1(InitReady), .C0(wb_rst11), 
    .B0(\wb_adr[5] ), .A0(InitReady), .DI1(\wb_adr_5[7] ), .DI0(\wb_adr_5[6] ), 
    .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_adr_5[6] ), .Q0(\wb_adr[6] ), 
    .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] ));
  SLICE_53 SLICE_53( .D1(un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1), .C1(\FS[5] ), 
    .B1(\FS[4] ), .A1(\FS[2] ), .D0(wb_rst11), 
    .C0(un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1), .B0(N_245), .A0(N_102_2), 
    .DI0(un1_wb_cyc_stb_1_sqmuxa_0), .CE(un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i), 
    .LSR(wb_rst10), .CLK(RCLK_c), .F0(un1_wb_cyc_stb_1_sqmuxa_0), 
    .Q0(wb_cyc_stb), .F1(N_102_2));
  SLICE_54 SLICE_54( .D1(\wb_dati_5_1_iv_0_a3_0_0[1] ), 
    .C1(\wb_dati_5_1_iv_0_0[1] ), .B1(N_128), .A1(N_94), .D0(wb_we), 
    .C0(\wb_dati_5_0_iv_0_a3_1[0] ), .B0(N_119), .A0(InitReady), 
    .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ), .CE(un1_wb_rst14_i), 
    .CLK(RCLK_c), .F0(\wb_dati_5[0] ), .Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), 
    .Q1(\wb_dati[1] ));
  SLICE_55 SLICE_55( .D1(N_94), .C1(wb_rst11), .B1(un1_wb_we95_1), 
    .A1(\wb_dati_5_1_iv_0_0[3] ), .D0(\wb_dati[1] ), .C0(N_240), .B0(N_49), 
    .A0(InitReady), .DI1(\wb_dati_5[3] ), .DI0(\wb_dati_5[2] ), 
    .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ), 
    .F1(\wb_dati_5[3] ), .Q1(\wb_dati[3] ));
  SLICE_56 SLICE_56( .D1(\wb_dati[4] ), .C1(N_240), .B1(N_49), .A1(InitReady), 
    .D0(\wb_dati_5_1_iv_0_1[4] ), .C0(\wb_dati[3] ), .B0(un1_wb_rst11_1_s6_1), 
    .A0(InitReady), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ), 
    .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[4] ), .Q0(\wb_dati[4] ), 
    .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] ));
  SLICE_57 SLICE_57( .D1(\wb_dati_5_1_iv_0_a3_0_0[7] ), 
    .C1(\wb_dati_5_1_iv_0_1[7] ), .B1(N_119), .A1(N_89), 
    .C0(\wb_dati_5_1_iv_0_a3_0_0[1] ), .B0(\wb_dati_5_1_iv_0_1[6] ), 
    .A0(N_128), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ), 
    .CE(un1_wb_rst14_i), .CLK(RCLK_c), .F0(\wb_dati_5[6] ), .Q0(\wb_dati[6] ), 
    .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] ));
  SLICE_58 SLICE_58( .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ), 
    .D0(wb_rst11), .C0(wb_req), .B0(un1_FS_37_i_0), .A0(N_78_i), 
    .DI0(wb_reqe_0), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), 
    .F1(un1_FS_37_i_0));
  SLICE_59 SLICE_59( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady), .A1(CmdValid), 
    .D0(wb_rst10), .C0(wb_rst), .B0(N_78_i), .A0(\FS[14] ), .DI0(wb_rste_0), 
    .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(N_78_i));
  SLICE_60 SLICE_60( .B1(wb_we95), .A1(un1_FS_29), .D0(un1_wb_adr_0_sqmuxa_3), 
    .C0(un1_wb_adr_0_sqmuxa_2), .B0(InitReady), .A0(CmdUFMData), .DI0(wb_we_0), 
    .CE(un1_wb_rst14_i), .LSR(wb_rst10), .CLK(RCLK_c), .F0(wb_we_0), 
    .Q0(wb_we), .F1(un1_wb_adr_0_sqmuxa_2));
  wb_cyc_stb_RNO_SLICE_61 \wb_cyc_stb_RNO/SLICE_61 ( .D1(CmdUFMWrite), 
    .C1(un1_PHI2r3_0), .B1(CmdUFMShift), .A1(CmdValid), .C0(N_102), 
    .B0(un1_FS_11), .A0(wb_ack), .M0(InitReady), 
    .OFX0(un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i));
  SLICE_62 SLICE_62( .D1(un1_PHI2r3_0), .C1(d_N_5_mux), .B1(InitReady), 
    .A1(CmdValid_fast), .D0(wb_ack), .C0(un1_FS_29), .B0(un1_FS_11), 
    .A0(InitReady), .F0(d_N_5_mux), .F1(un1_FS_38_i));
  SLICE_63 SLICE_63( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2), 
    .D0(\S[1] ), .C0(Ready), .B0(N_254), .A0(N_250), .F0(N_39), .F1(N_250));
  SLICE_64 SLICE_64( .D1(Ready), .C1(nRCAS_0_sqmuxa_1), .B1(nRWE_0io_RNO_1), 
    .A1(N_37_i_1), .D0(Ready), .C0(RASr2), .B0(N_41), .A0(CBR_fast), 
    .F0(nRCAS_0_sqmuxa_1), .F1(N_37_i));
  SLICE_65 SLICE_65( .D1(un1_FS_40_1_0_1), .C1(\FS[13] ), .B1(\FS[10] ), 
    .A1(\FS[9] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[9] ), 
    .F0(un1_FS_40_1_0_1), .F1(un1_FS_40_1_0));
  SLICE_66 SLICE_66( .C1(\S[1] ), .B1(N_39), .A1(CBR), .D0(\S[1] ), 
    .C0(nRCAS_0io_RNO_0), .B0(nRCAS_0_sqmuxa_1), .A0(N_28_i_1), .F0(N_249_i), 
    .F1(nRCAS_0io_RNO_0));
  SLICE_67 SLICE_67( .D1(\FS[9] ), .C1(wb_rst11), .B1(\FS[13] ), .A1(N_230), 
    .C0(un1_wb_we95_1), .B0(wb_rst11), .A0(N_94), .F0(N_49), .F1(N_94));
  SLICE_68 SLICE_68( .C1(Ready), .B1(nRWE_0io_RNO_4), .A1(nRWE_0io_RNO_3), 
    .D0(\IS[1] ), .C0(\IS[2] ), .B0(\IS[0] ), .A0(N_250), .F0(nRWE_0io_RNO_4), 
    .F1(nRWE_0io_RNO_1));
  SLICE_69 SLICE_69( .C1(nRRAS_0_sqmuxa), .B1(RCKE_c), .A1(RASr2), .C0(CO0), 
    .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa), .F1(nRWE_0io_RNO_3));
  SLICE_70 SLICE_70( .D1(N_131), .C1(N_119), .B1(\FS[14] ), .A1(\FS[13] ), 
    .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[12] ), .F0(N_131), .F1(N_85));
  SLICE_71 SLICE_71( .B1(\FS[11] ), .A1(\FS[10] ), .D0(\FS[12] ), .C0(N_116), 
    .B0(\FS[13] ), .A0(\FS[14] ), .F0(\wb_dati_5_1_iv_0_a3_0_0[7] ), 
    .F1(N_116));
  SLICE_72 SLICE_72( .D1(wb_rst11), .C1(N_248), .B1(\FS[14] ), .A1(\FS[13] ), 
    .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[12] ), .A0(\FS[9] ), .F0(N_248), 
    .F1(N_240));
  SLICE_73 SLICE_73( .D1(XOR8MEG14_1), .C1(\Din_c[7] ), .B1(\Din_c[5] ), 
    .A1(\Din_c[3] ), .D0(C1WR_7), .C0(CMDWR_2), .B0(CmdEnable), .A0(XOR8MEG14), 
    .M0(\Din_c[0] ), .CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), 
    .F0(CmdUFMData_1_sqmuxa), .Q0(CmdUFMData), .F1(XOR8MEG14));
  SLICE_74 SLICE_74( .D1(\wb_dati_5_1_iv_0_a3_0[6] ), .C1(N_246), 
    .B1(\FS[12] ), .A1(\FS[10] ), .D0(\wb_dati[5] ), .C0(N_98), .B0(N_85), 
    .A0(InitReady), .F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_98));
  SLICE_75 SLICE_75( .C1(\FS[14] ), .B1(wb_rst11), .A1(\FS[11] ), 
    .D0(\wb_dati_5_1_iv_0_a3_0[3] ), .C0(\wb_dati[2] ), .B0(N_128), 
    .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[3] ), .F1(N_128));
  SLICE_76 SLICE_76( .D1(\FS[15] ), .C1(\FS[16] ), .B1(\FS[17] ), 
    .A1(InitReady), .B0(wb_rst11), .A0(un1_wb_we95_1), 
    .F0(un1_wb_rst11_1_s6_1), .F1(wb_rst11));
  SLICE_77 SLICE_77( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), 
    .D0(nRRAS_5_u_i_0), .C0(N_254), .B0(N_250), .A0(\IS[0] ), .F0(N_25), 
    .F1(N_254));
  SLICE_78 SLICE_78( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .C0(N_128), 
    .B0(N_59), .A0(\FS[13] ), .F0(N_89), .F1(N_59));
  SLICE_79 SLICE_79( .C1(wb_rst11), .B1(\FS[14] ), .A1(\FS[13] ), 
    .D0(\wb_dati_5_1_iv_0_a3_2_0[1] ), .C0(\wb_dati[0] ), .B0(N_248), 
    .A0(InitReady), .F0(\wb_dati_5_1_iv_0_0[1] ), 
    .F1(\wb_dati_5_1_iv_0_a3_2_0[1] ));
  SLICE_80 SLICE_80( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), 
    .D0(\wb_dati_5_1_iv_0_a3_1_1[4] ), .C0(N_248), .B0(N_246), .A0(N_85), 
    .F0(\wb_dati_5_1_iv_0_1[4] ), .F1(\wb_dati_5_1_iv_0_a3_1_1[4] ));
  SLICE_81 SLICE_81( .D1(wb_rst11), .C1(\wb_dati_5_1_iv_0_a3_3_0[7] ), 
    .B1(\FS[12] ), .A1(\FS[10] ), .D0(\wb_dati[6] ), .C0(N_242), .B0(N_91), 
    .A0(InitReady), .F0(\wb_dati_5_1_iv_0_1[7] ), .F1(N_242));
  SLICE_82 SLICE_82( .B1(\FS[14] ), .A1(\FS[13] ), .D0(wb_we95_0_tz_tz_tz), 
    .C0(un1_FS_20_3), .B0(\FS[12] ), .A0(\FS[11] ), .F0(un1_wb_we95_1), 
    .F1(un1_FS_20_3));
  SLICE_83 SLICE_83( .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ), .D0(N_120), 
    .C0(N_119), .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_91), .F1(N_120));
  SLICE_84 SLICE_84( .D1(wb_we95_0_tz_tz_tz), .C1(N_228), .B1(\FS[14] ), 
    .A1(\FS[13] ), .C0(wb_we113_i), .B0(wb_we95), .A0(un1_FS_29), .F0(N_181), 
    .F1(un1_FS_29));
  SLICE_85 SLICE_85( .C1(wb_rst11), .B1(un1_FS_40_1_1_1), .A1(un1_FS_40_1_0), 
    .D0(un1_FS_40_1_1_tz), .C0(N_139), .B0(\FS[10] ), .A0(\FS[9] ), 
    .F0(un1_FS_40_1_1_1), .F1(\wb_adr_cnst_m2[0] ));
  SLICE_86 SLICE_86( .D1(\FS[12] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), 
    .C0(N_136), .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_139), .F1(N_136));
  SLICE_87 SLICE_87( .B1(\FS[10] ), .A1(\FS[9] ), .D0(wb_we95_0_tz_tz_tz), 
    .C0(un1_FS_20_3), .B0(\FS[12] ), .A0(\FS[11] ), .F0(wb_we95), 
    .F1(wb_we95_0_tz_tz_tz));
  SLICE_88 SLICE_88( .D1(Ready), .C1(N_28_i_sn), .B1(N_28_i_1), .A1(N_25_i), 
    .D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_28_i_1), 
    .F1(N_28_i));
  SLICE_89 SLICE_89( .B1(wb_req), .A1(\FS[0] ), .D0(N_233), .C0(N_102_2), 
    .B0(N_102_1), .A0(InitReady), .F0(N_102), .F1(N_233));
  SLICE_90 SLICE_90( .D1(ADWR_7), .C1(C1WR_2), .B1(C1WR_7), .A1(CMDWR_2), 
    .D0(N_304), .C0(\MAin_c[7] ), .B0(\MAin_c[6] ), .A0(\MAin_c[5] ), 
    .F0(C1WR_7), .F1(un1_CMDWR));
  SLICE_91 SLICE_91( .C1(C1WR_7), .B1(C1WR_2), .A1(ADWR_7), .D0(\MAin_c[3] ), 
    .C0(\MAin_c[1] ), .B0(ADWR_5), .A0(ADWR_4), .F0(ADWR_7), .F1(un1_ADWR));
  SLICE_92 SLICE_92( .C1(\MAin_c[4] ), .B1(\MAin_c[3] ), .A1(\MAin_c[2] ), 
    .D0(nFWE_c), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), .A0(C1WR_0), .F0(C1WR_2), 
    .F1(C1WR_0));
  SLICE_93 SLICE_93( .C1(wb_we113_i), .B1(wb_rst11), .A1(un1_FS_37_i_0), 
    .D0(wb_we95_0_tz_tz_tz), .C0(N_228), .B0(\FS[14] ), .A0(\FS[13] ), 
    .F0(wb_we113_i), .F1(un1_wb_adr_0_sqmuxa_3));
  SLICE_94 SLICE_94( .B1(\Bank[1] ), .A1(\Bank[0] ), .D0(un1_Bank_1_4), 
    .C0(un1_Bank_1_3), .B0(\Bank[4] ), .A0(\Bank[3] ), .F0(N_304), 
    .F1(un1_Bank_1_3));
  SLICE_95 SLICE_95( .B1(PHI2r3), .A1(PHI2r2), .D0(un1_PHI2r3_0), 
    .C0(InitReady), .B0(CmdValid), .A0(CmdUFMShift), .F0(N_245), 
    .F1(un1_PHI2r3_0));
  SLICE_96 SLICE_96( .C1(\FS[8] ), .B1(\FS[6] ), .A1(\FS[1] ), .C0(wb_req), 
    .B0(N_102_1), .A0(\FS[0] ), .F0(un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1), 
    .F1(N_102_1));
  SLICE_97 SLICE_97( .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady), 
    .C0(G_8_0_a3_0_0), .B0(CmdValid_fast), .A0(CmdUFMShift_fast), 
    .F0(un1_wb_rst14_i), .F1(G_8_0_a3_0_0));
  SLICE_98 SLICE_98( .D1(\S[1] ), .C1(CO0), .B1(CASr3), .A1(CASr2), 
    .C0(nRWE_0io_RNO_2), .B0(FWEr), .A0(CBR_fast), .F0(N_37_i_1), 
    .F1(nRWE_0io_RNO_2));
  SLICE_99 SLICE_99( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), 
    .D0(\FS[13] ), .C0(\FS[12] ), .B0(\FS[10] ), .A0(\FS[9] ), 
    .F0(\wb_dati_5_1_iv_0_a3_0[3] ), .F1(\wb_dati_5_1_iv_0_a3_0_0[1] ));
  SLICE_100 SLICE_100( .D1(\FS[14] ), .C1(\FS[13] ), .B1(\FS[12] ), 
    .A1(\FS[11] ), .D0(\FS[14] ), .C0(\FS[12] ), .B0(\FS[11] ), .A0(\FS[10] ), 
    .F0(N_230), .F1(un1_FS_40_1_1_tz));
  SLICE_101 SLICE_101( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[4] ), 
    .A1(\Din_c[3] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ), 
    .A0(\Din_c[4] ), .F0(un1_Din_2), .F1(CmdEnable17_5));
  SLICE_102 SLICE_102( .D1(\FS[17] ), .C1(\FS[16] ), .B1(\FS[15] ), 
    .A1(\FS[12] ), .C0(\FS[17] ), .B0(\FS[16] ), .A0(\FS[15] ), .F0(un1_FS_11), 
    .F1(InitReady3_0_a3_2));
  SLICE_103 SLICE_103( .C1(\FS[13] ), .B1(\FS[11] ), .A1(\FS[9] ), 
    .D0(\FS[14] ), .C0(\FS[13] ), .B0(\FS[11] ), .A0(\FS[9] ), 
    .F0(\wb_dati_5_1_iv_0_a3_3_0[7] ), .F1(\wb_dati_5_1_iv_0_a3_0[6] ));
  SLICE_104 SLICE_104( .D1(\Din_c[6] ), .C1(\Din_c[5] ), .B1(\Din_c[1] ), 
    .A1(\Din_c[0] ), .D0(\Din_c[6] ), .C0(\Din_c[2] ), .B0(\Din_c[1] ), 
    .A0(\Din_c[0] ), .F0(CmdEnable17_4), .F1(CmdEnable16_4));
  SLICE_105 SLICE_105( .C1(nFWE_c), .B1(\MAin_c[6] ), .A1(\MAin_c[0] ), 
    .D0(nFWE_c), .C0(\MAin_c[1] ), .B0(\MAin_c[0] ), .A0(C1WR_0), 
    .M1(nCCAS_c_i), .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CMDWR_2), .Q0(CBR), 
    .F1(ADWR_4), .Q1(CBR_fast));
  SLICE_106 SLICE_106( .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(\Din_c[7] ), 
    .C0(\Din_c[4] ), .B0(\Din_c[3] ), .A0(\Din_c[2] ), .M0(CASr2), 
    .CLK(RCLK_c), .F0(CmdEnable16_5), .Q0(CASr3), .F1(XOR8MEG9_1));
  SLICE_107 SLICE_107( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
    .B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c));
  SLICE_108 SLICE_108( .D1(\IS[0] ), .C1(N_250), .B1(N_254), 
    .A1(nRRAS_5_u_i_0), .B0(Ready), .A0(N_250), .M0(nFWE_c_i), .CLK(nCRAS_c), 
    .F0(N_253_i), .Q0(FWEr_fast), .F1(N_25_i));
  SLICE_109 SLICE_109( .B1(wb_rst11), .A1(\FS[14] ), .B0(wb_rst11), 
    .A0(\FS[9] ), .F0(N_119), .F1(N_246));
  SLICE_110 SLICE_110( .B1(\FS[12] ), .A1(\FS[11] ), .D0(N_116), .C0(\FS[14] ), 
    .B0(\FS[13] ), .A0(\FS[12] ), .F0(\wb_dati_5_0_iv_0_a3_1[0] ), .F1(N_228));
  SLICE_111 SLICE_111( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ), 
    .D0(\MAin_c[7] ), .C0(\MAin_c[5] ), .B0(\MAin_c[4] ), .A0(\MAin_c[2] ), 
    .F0(ADWR_5), .F1(\RA_c[7] ));
  SLICE_112 SLICE_112( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel), 
    .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ), .F1(RDQML_c));
  SLICE_113 SLICE_113( .C1(nRowColSel), .B1(\RowA[8] ), .A1(\MAin_c[8] ), 
    .C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ), 
    .F1(\RA_c[8] ));
  SLICE_114 SLICE_114( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ), 
    .C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ), 
    .F1(\RA_c[6] ));
  SLICE_115 SLICE_115( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ), 
    .C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ), 
    .F1(\RA_c[5] ));
  SLICE_116 SLICE_116( .D1(n8MEGEN), .C1(XOR8MEG), .B1(Ready_fast), 
    .A1(\Din_c[6] ), .B0(\Din_c[6] ), .A0(\Din_c[4] ), .F0(XOR8MEG14_1), 
    .F1(RA11d_0));
  SLICE_117 SLICE_117( .C1(\S[1] ), .B1(N_25), .A1(CBR_fast), .D0(\S[1] ), 
    .C0(FWEr), .B0(CO0), .A0(CASr2), .F0(RCKEEN_8_u_1_0), .F1(N_28_i_sn));
  SLICE_118 SLICE_118( .B1(Ready_fast), .A1(\CROW_c[0] ), .B0(Ready_fast), 
    .A0(\CROW_c[1] ), .M0(PHI2r2), .CLK(RCLK_c), .F0(\RBAd_0[1] ), .Q0(PHI2r3), 
    .F1(\RBAd_0[0] ));
  RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i), 
    .RD0(RD[0]));
  RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ), 
    .CLK(nCCAS_c));
  Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
  PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
  PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r));
  RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
  RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
  nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS));
  nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_249_i), .CLK(RCLK_c));
  nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS));
  nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_25_i), .CLK(RCLK_c));
  nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
  nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_37_i), .CLK(RCLK_c));
  RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
  RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
  nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS));
  nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_28_i), .CLK(RCLK_c));
  RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i), 
    .RD7(RD[7]));
  RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ), 
    .CLK(nCCAS_c));
  RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .IOLDO(\WRD[6] ), .PADDT(RD_1_i), 
    .RD6(RD[6]));
  RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ), 
    .CLK(nCCAS_c));
  RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .IOLDO(\WRD[5] ), .PADDT(RD_1_i), 
    .RD5(RD[5]));
  RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ), 
    .CLK(nCCAS_c));
  RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .IOLDO(\WRD[4] ), .PADDT(RD_1_i), 
    .RD4(RD[4]));
  RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ), 
    .CLK(nCCAS_c));
  RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .IOLDO(\WRD[3] ), .PADDT(RD_1_i), 
    .RD3(RD[3]));
  RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ), 
    .CLK(nCCAS_c));
  RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .IOLDO(\WRD[2] ), .PADDT(RD_1_i), 
    .RD2(RD[2]));
  RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ), 
    .CLK(nCCAS_c));
  RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .IOLDO(\WRD[1] ), .PADDT(RD_1_i), 
    .RD1(RD[1]));
  RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ), 
    .CLK(nCCAS_c));
  RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
  RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0), 
    .CLK(PHI2_c));
  RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
  RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(N_45), .LSR(RA10s_i), 
    .CLK(RCLK_c));
  RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
  RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
  RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
  RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
  RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
  RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
  RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
  RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
  RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
  RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
  RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1]));
  RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ), 
    .CLK(nCRAS_c));
  RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0]));
  RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ), 
    .CLK(nCRAS_c));
  LED LED_I( .PADDO(LED_c), .LED(LED));
  nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
  nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
  nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
  Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
  Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
  Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
  Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
  Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
  Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
  Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
  Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
  Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] ));
  Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
  Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] ));
  Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
  Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] ));
  Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
  Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] ));
  Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
  Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] ));
  Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
  Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CLK(PHI2_c), .IN(\Bank[2] ));
  Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
  Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CLK(PHI2_c), .IN(\Bank[1] ));
  Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
  Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CLK(PHI2_c), .IN(\Bank[0] ));
  CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
  CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
  MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
  MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
  MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
  MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
  MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
  MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
  MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
  MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
  MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
  MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
  ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(RCLK_c), .WBRSTI(wb_rst), 
    .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), 
    .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), 
    .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), 
    .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), 
    .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), 
    .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), 
    .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), 
    .WBACKO(wb_ack));
  VHI VHI_INST( .Z(VCCI));
  PUR PUR_INST( .PUR(VCCI));
  GSR GSR_INST( .GSR(VCCI));
endmodule

module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly;

  vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );

  FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module vcc ( output PWR1 );

  VHI INST1( .Z(PWR1));
endmodule

module gnd ( output PWR0 );

  VLO INST1( .Z(PWR0));
endmodule

module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );

  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
  defparam inst1.INIT0 = 16'h000A;
  defparam inst1.INIT1 = 16'h300A;
  defparam inst1.INJECT1_0 = "NO";
  defparam inst1.INJECT1_1 = "NO";
endmodule

module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly;

  vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1());

  specify
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );

  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
  defparam inst1.INIT0 = 16'h5002;
  defparam inst1.INIT1 = 16'h300A;
  defparam inst1.INJECT1_0 = "NO";
  defparam inst1.INJECT1_1 = "NO";
endmodule

module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );

  CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), 
    .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
  defparam inst1.INIT0 = 16'h300A;
  defparam inst1.INIT1 = 16'h300A;
  defparam inst1.INJECT1_0 = "NO";
  defparam inst1.INJECT1_1 = "NO";
endmodule

module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;

  vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), 
    .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));

  specify
    (A1 => F1) = (0:0:0,0:0:0);
    (A1 => FCO) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (A0 => F1) = (0:0:0,0:0:0);
    (A0 => FCO) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    (FCI => F0) = (0:0:0,0:0:0);
    (FCI => F1) = (0:0:0,0:0:0);
    (FCI => FCO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
    Q0, F1 );
  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;

  lut4 CmdEnable17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40003 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut4 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40003 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module inverter ( input I, output Z );

  INV INST1( .A(I), .Z(Z));
endmodule

module SLICE_11 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;

  lut4 CmdEnable16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40004 C1Submitted_s( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40004 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_12 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;

  lut40005 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q0));

  specify
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40005 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_16 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;

  lut40006 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40007 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre0008 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40006 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40007 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module vmuxregsre0008 ( input D0, D1, SD, SP, CK, LSR, output Q );

  FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module SLICE_17 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
  wire   GNDI, \SLICE_17/SLICE_17_K1_H1 , \SLICE_17/CmdEnable_s/GATE_H0 , VCCI, 
         CLK_NOTIN, DI0_dly, CLK_dly;

  lut40009 SLICE_17_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
    .Z(\SLICE_17/SLICE_17_K1_H1 ));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40010 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(\SLICE_17/CmdEnable_s/GATE_H0 ));
  vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  selmux2 SLICE_17_K0K1MUX( .D0(\SLICE_17/CmdEnable_s/GATE_H0 ), 
    .D1(\SLICE_17/SLICE_17_K1_H1 ), .SD(M0), .Z(OFX0));

  specify
    (B1 => OFX0) = (0:0:0,0:0:0);
    (A1 => OFX0) = (0:0:0,0:0:0);
    (D0 => OFX0) = (0:0:0,0:0:0);
    (C0 => OFX0) = (0:0:0,0:0:0);
    (B0 => OFX0) = (0:0:0,0:0:0);
    (A0 => OFX0) = (0:0:0,0:0:0);
    (M0 => OFX0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40009 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40010 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module selmux2 ( input D0, D1, SD, output Z );

  MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
endmodule

module SLICE_18 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;

  lut40011 CmdLEDEN_4_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 CmdLEDEN_4_u( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module lut40011 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40012 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;

  lut40013 CmdUFMShift_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module lut40013 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h030A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_21 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
  wire   VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;

  lut40013 CmdUFMShift_3_u_fast( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdUFMShift_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module SLICE_22 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;

  lut40014 CmdUFMWrite_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40015 CmdUFMWrite_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module lut40014 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40015 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0C0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_23 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;

  lut40016 XOR8MEG11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40017 CmdValid_r( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40016 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40017 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;

  lut40018 XOR8MEG18( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40017 CmdValid_r_fast( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40018 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;

  lut40019 Cmdn8MEGEN_4_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40020 Cmdn8MEGEN_4_u( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module lut40019 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40020 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_26 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;

  lut40021 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40005 nFWE_pad_RNI420B( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40021 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_28 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly;

  lut40022 RA10_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40023 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40022 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40023 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_29 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
    F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40024 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40025 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40024 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40025 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_30 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40021 RA10_2_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40026 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40026 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_31 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly;

  lut4 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40021 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_32 ( input C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40027 LEDEN_6( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40027 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_34 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;

  lut40028 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40005 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40028 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_35 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, M1_dly, CLK_dly, M0_dly;

  lut40029 un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1( .A(A1), .B(B1), .C(GNDI), 
    .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40029 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
    Q0, F1 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly;

  lut40030 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40031 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40030 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40031 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
    Q0, F1 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly;

  lut40032 un1_Bank_1_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40033 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40032 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40033 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_38 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly;

  lut40034 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40035 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40034 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40035 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_39 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly;

  lut40036 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40021 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40036 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_40 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;

  lut40037 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40037 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_41 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;

  lut40037 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module SLICE_42 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;

  lut40038 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module lut40038 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_43 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;

  lut40037 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module SLICE_44 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;

  lut40038 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
  endspecify

endmodule

module SLICE_45 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, 
    F1 );
  wire   GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;

  lut40039 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40021 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre0008 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40039 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_46 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;

  lut40040 XOR8MEG_3_u_0_bm( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40011 \XOR8MEG_3_u_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module lut40040 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h40C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_47 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;

  lut40041 wb_rst10( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40027 n8MEGEN_6( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40041 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output 
    F0, Q0, F1 );
  wire   VCCI, DI0_dly, CLK_dly, LSR_dly;

  lut40042 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40043 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre0008 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40042 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40043 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_49 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
    F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40044 \wb_adr_5[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40045 \wb_adr_5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40044 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40045 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_50 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, 
    Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40037 \wb_adr_5[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \wb_adr_5[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_51 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40046 \wb_adr_5[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40046 \wb_adr_5[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40046 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_52 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, 
    F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40037 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40046 \wb_adr_5[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, 
    output F0, Q0, F1 );
  wire   VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;

  lut40047 un1_wb_cyc_stb_2_sqmuxa_i_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), 
    .Z(F1));
  lut40048 un1_wb_cyc_stb_1_sqmuxa_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre0008 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40047 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40048 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
    output F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40049 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40050 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40049 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40050 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
    output F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40051 \wb_dati_5_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40052 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40051 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40052 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, 
    output F0, Q0, F1, Q1 );
  wire   VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40052 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40053 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40053 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFE4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_57 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output 
    F0, Q0, F1, Q1 );
  wire   GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;

  lut40049 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40054 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40054 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_58 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;

  lut40018 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40055 wb_reqe( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre0008 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40055 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7250) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, 
    Q0, F1 );
  wire   VCCI, GNDI, DI0_dly, CLK_dly;

  lut40056 PHI2r3_RNIS5A51( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40057 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40056 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40057 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_60 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, 
    Q0, F1 );
  wire   GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;

  lut40021 un1_wb_adr_0_sqmuxa_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40058 wb_we_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre0008 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), 
    .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
    $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge LSR, 0:0:0);
    $width (negedge LSR, 0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module lut40058 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h888F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module wb_cyc_stb_RNO_SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, M0, output 
    OFX0 );
  wire   \wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 , GNDI, 
         \wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ;

  lut40059 \wb_cyc_stb_RNO/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), 
    .Z(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 ));
  lut40060 \wb_cyc_stb_RNO/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
    .Z(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ));
  gnd DRIVEGND( .PWR0(GNDI));
  selmux2 \wb_cyc_stb_RNO/SLICE_61_K0K1MUX ( 
    .D0(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/GATE_H0 ), 
    .D1(\wb_cyc_stb_RNO/SLICE_61/wb_cyc_stb_RNO/SLICE_61_K1_H1 ), .SD(M0), 
    .Z(OFX0));

  specify
    (D1 => OFX0) = (0:0:0,0:0:0);
    (C1 => OFX0) = (0:0:0,0:0:0);
    (B1 => OFX0) = (0:0:0,0:0:0);
    (A1 => OFX0) = (0:0:0,0:0:0);
    (C0 => OFX0) = (0:0:0,0:0:0);
    (B0 => OFX0) = (0:0:0,0:0:0);
    (A0 => OFX0) = (0:0:0,0:0:0);
    (M0 => OFX0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40059 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40060 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40061 CmdValid_fast_RNITQBM1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40032 \ufmefb/EFBInst_0_RNI9PBJ ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40061 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hB8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40022 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40062 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40062 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40063 nRWE_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40064 nRCAS_0_sqmuxa_1_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40063 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF1FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40064 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40065 un1_FS_40_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40066 un1_FS_40_1_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40065 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1108) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40066 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2A2B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_66 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40067 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40068 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40067 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40068 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40069 \wb_dati_5_1_iv_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40070 \wb_dati_5_1_iv_0_o3[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40069 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40070 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_68 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40071 nRWE_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40072 nRWE_0io_RNO_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40071 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5252) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40072 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_69 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40073 nRWE_0io_RNO_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40074 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40073 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40074 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut4 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40075 \wb_dati_5_1_iv_0_a3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), 
    .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40075 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_71 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40037 wb_we113_i_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40076 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40076 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40077 \wb_dati_5_1_iv_0_a3[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40016 \FS_RNI3V8E[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40077 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hB000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, 
    Q0, F1 );
  wire   VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;

  lut40006 XOR8MEG14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut4 CmdUFMData_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
    $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
  endspecify

endmodule

module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40042 \wb_dati_5_1_iv_0_a3[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40052 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40078 \wb_dati_5_1_iv_0_a2_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40079 \wb_dati_5_1_iv_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40078 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40079 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_76 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40047 \wb_adr_cnst_sn.m2_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40037 \wb_dati_5_1_iv_0_RNO[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
    .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40080 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40081 nRRAS_5_u_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40080 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40081 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_78 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40082 \wb_dati_5_1_iv_0_m3[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40018 \wb_dati_5_1_iv_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40082 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hD3D3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40018 \wb_dati_5_1_iv_0_a3_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40079 \wb_dati_5_1_iv_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40042 \wb_dati_5_1_iv_0_a3_1_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), 
    .Z(F1));
  lut40083 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40083 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hEEEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40042 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40052 \wb_dati_5_1_iv_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_82 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40029 wb_we95_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40084 un1_wb_we95_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40084 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40085 \wb_dati_5_1_iv_0_a2[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40077 \wb_dati_5_1_iv_0_a3_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40085 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_84 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40016 un1_FS_29( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40086 \wb_adr_cnst_sn.m4_32 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40086 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_85 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40087 \wb_adr_cnst_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40088 un1_FS_40_1_1_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40087 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h9090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40088 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hF6F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_86 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40089 un1_FS_40_1_o6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40018 un1_FS_40_1_a6( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40089 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hFFB1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_87 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40090 un1_FS_21_1_i( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40091 wb_we95( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40090 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40091 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40092 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40093 nRCAS_r_i_a3_1_1_tz( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40092 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40093 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40007 un1_wb_cyc_stb_2_sqmuxa_i_o3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40032 un1_wb_cyc_stb_2_sqmuxa_i_a3( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40094 un1_CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut4 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40094 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40095 un1_ADWR( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut4 ADWR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40095 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40018 C1WR_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40096 C1WR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40096 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_93 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40073 un1_wb_adr_0_sqmuxa_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40097 wb_we113_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40097 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hBBBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40037 un1_Bank_1_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut4 un1_Bank_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_95 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40014 un1_PHI2r3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40032 un1_wb_cyc_stb_1_sqmuxa_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_96 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40085 un1_wb_cyc_stb_2_sqmuxa_i_a3_1( .A(A1), .B(B1), .C(C1), .D(GNDI), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40018 un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(GNDI), 
    .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40014 PHI2r3_RNIFT0I( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40098 CmdUFMShift_fast_RNIG9JD1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40098 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_98 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40064 nRWE_0io_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40075 nRWE_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_99 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut4 \wb_dati_5_1_iv_0_a3_0_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40099 \wb_dati_5_1_iv_0_a3_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), 
    .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40099 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40100 un1_FS_40_1_1_tz( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40101 \wb_dati_5_1_iv_0_o3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40100 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4042) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40101 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40064 CmdEnable17_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40041 un1_Din_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_102 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut4 InitReady3_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40074 un1_FS_11( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_103 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40102 \wb_dati_5_1_iv_0_a3_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut4 \wb_dati_5_1_iv_0_a3_3_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40102 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h8282) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );

  lut40036 CmdEnable16_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40096 CmdEnable17_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_105 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, 
    Q0, F1, Q1 );
  wire   GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;

  lut40103 ADWR_4( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40104 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), 
    .LSR(GNDI), .Q(Q0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    (CLK => Q1) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
  endspecify

endmodule

module lut40103 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40104 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_106 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, M0_dly, CLK_dly;

  lut40014 XOR8MEG9_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40047 CmdEnable16_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
  vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), 
    .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module SLICE_107 ( input B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40038 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_108 ( input D1, C1, B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly;

  lut40105 nRRAS_5_u_i_0_RNILD5I( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40029 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
    .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));
  vmuxregsre FWEr_fast( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
    .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
  endspecify

endmodule

module lut40105 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_109 ( input B1, A1, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40014 \wb_dati_5_1_iv_0_a2[4] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), 
    .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40014 \wb_dati_5_1_iv_0_a2_0[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), 
    .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_110 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40090 un1_FS_22_1_i( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40106 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40106 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h4800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40012 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut4 ADWR_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_112 ( input B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40090 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40012 \un9_RA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_114 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40012 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_115 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40012 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40012 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module SLICE_116 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40107 RA11d( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
  lut40108 XOR8MEG14_1( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (D1 => F1) = (0:0:0,0:0:0);
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40107 ( input A, B, C, D, output Z );

  ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module lut40108 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_117 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
  wire   GNDI;

  lut40086 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40109 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));

  specify
    (C1 => F1) = (0:0:0,0:0:0);
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (D0 => F0) = (0:0:0,0:0:0);
    (C0 => F0) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
  endspecify

endmodule

module lut40109 ( input A, B, C, D, output Z );

  ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule

module SLICE_118 ( input B1, A1, B0, A0, M0, CLK, output F0, Q0, F1 );
  wire   GNDI, VCCI, M0_dly, CLK_dly;

  lut40037 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
  gnd DRIVEGND( .PWR0(GNDI));
  lut40037 \RBAd[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
  vmuxregsre PHI2r3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), 
    .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (B1 => F1) = (0:0:0,0:0:0);
    (A1 => F1) = (0:0:0,0:0:0);
    (B0 => F0) = (0:0:0,0:0:0);
    (A0 => F0) = (0:0:0,0:0:0);
    (CLK => Q0) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 );

  xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));

  specify
    (IOLDO => RD0) = (0:0:0,0:0:0);
    (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD0, 0:0:0);
    $width (negedge RD0, 0:0:0);
  endspecify

endmodule

module xo2iobuf ( input I, T, output Z, PAD, input PADI );

  IB INST1( .I(PADI), .O(Z));
  OBW INST2( .I(I), .T(T), .O(PAD));
endmodule

module RD_0__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module mfflsre ( input D0, SP, CK, LSR, output Q );

  FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module Dout_0_ ( input PADDO, output Dout0 );

  xo2iobuf0110 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));

  specify
    (PADDO => Dout0) = (0:0:0,0:0:0);
  endspecify

endmodule

module xo2iobuf0110 ( input I, output PAD );

  OB INST5( .I(I), .O(PAD));
endmodule

module PHI2 ( output PADDI, input PHI2 );

  xo2iobuf0111 PHI2_pad( .Z(PADDI), .PAD(PHI2));

  specify
    (PHI2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge PHI2, 0:0:0);
    $width (negedge PHI2, 0:0:0);
  endspecify

endmodule

module xo2iobuf0111 ( output Z, input PAD );

  IBPD INST1( .I(PAD), .O(Z));
endmodule

module PHI2_MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module smuxlregsre ( input D0, SP, CK, LSR, output Q );

  IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module RDQML ( input PADDO, output RDQML );

  xo2iobuf0110 RDQML_pad( .I(PADDO), .PAD(RDQML));

  specify
    (PADDO => RDQML) = (0:0:0,0:0:0);
  endspecify

endmodule

module RDQMH ( input PADDO, output RDQMH );

  xo2iobuf0110 RDQMH_pad( .I(PADDO), .PAD(RDQMH));

  specify
    (PADDO => RDQMH) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRCAS ( input IOLDO, output nRCAS );

  xo2iobuf0110 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));

  specify
    (IOLDO => nRCAS) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0112 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module mfflsre0112 ( input D0, SP, CK, LSR, output Q );

  FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module nRRAS ( input IOLDO, output nRRAS );

  xo2iobuf0110 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));

  specify
    (IOLDO => nRRAS) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0112 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module nRWE ( input IOLDO, output nRWE );

  xo2iobuf0110 nRWE_pad( .I(IOLDO), .PAD(nRWE));

  specify
    (IOLDO => nRWE) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0112 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RCKE ( input PADDO, output RCKE );

  xo2iobuf0110 RCKE_pad( .I(PADDO), .PAD(RCKE));

  specify
    (PADDO => RCKE) = (0:0:0,0:0:0);
  endspecify

endmodule

module RCLK ( output PADDI, input RCLK );

  xo2iobuf0113 RCLK_pad( .Z(PADDI), .PAD(RCLK));

  specify
    (RCLK => PADDI) = (0:0:0,0:0:0);
    $width (posedge RCLK, 0:0:0);
    $width (negedge RCLK, 0:0:0);
  endspecify

endmodule

module xo2iobuf0113 ( output Z, input PAD );

  IB INST1( .I(PAD), .O(Z));
endmodule

module nRCS ( input IOLDO, output nRCS );

  xo2iobuf0110 nRCS_pad( .I(IOLDO), .PAD(nRCS));

  specify
    (IOLDO => nRCS) = (0:0:0,0:0:0);
  endspecify

endmodule

module nRCS_MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre0112 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RD_7_ ( output PADDI, input IOLDO, PADDT, inout RD7 );

  xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));

  specify
    (IOLDO => RD7) = (0:0:0,0:0:0);
    (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD7 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD7, 0:0:0);
    $width (negedge RD7, 0:0:0);
  endspecify

endmodule

module RD_7__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RD_6_ ( output PADDI, input IOLDO, PADDT, inout RD6 );

  xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));

  specify
    (IOLDO => RD6) = (0:0:0,0:0:0);
    (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD6 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD6, 0:0:0);
    $width (negedge RD6, 0:0:0);
  endspecify

endmodule

module RD_6__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RD_5_ ( output PADDI, input IOLDO, PADDT, inout RD5 );

  xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));

  specify
    (IOLDO => RD5) = (0:0:0,0:0:0);
    (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD5 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD5, 0:0:0);
    $width (negedge RD5, 0:0:0);
  endspecify

endmodule

module RD_5__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RD_4_ ( output PADDI, input IOLDO, PADDT, inout RD4 );

  xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));

  specify
    (IOLDO => RD4) = (0:0:0,0:0:0);
    (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD4 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD4, 0:0:0);
    $width (negedge RD4, 0:0:0);
  endspecify

endmodule

module RD_4__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RD_3_ ( output PADDI, input IOLDO, PADDT, inout RD3 );

  xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));

  specify
    (IOLDO => RD3) = (0:0:0,0:0:0);
    (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD3 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD3, 0:0:0);
    $width (negedge RD3, 0:0:0);
  endspecify

endmodule

module RD_3__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RD_2_ ( output PADDI, input IOLDO, PADDT, inout RD2 );

  xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));

  specify
    (IOLDO => RD2) = (0:0:0,0:0:0);
    (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD2, 0:0:0);
    $width (negedge RD2, 0:0:0);
  endspecify

endmodule

module RD_2__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RD_1_ ( output PADDI, input IOLDO, PADDT, inout RD1 );

  xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));

  specify
    (IOLDO => RD1) = (0:0:0,0:0:0);
    (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
    (RD1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge RD1, 0:0:0);
    $width (negedge RD1, 0:0:0);
  endspecify

endmodule

module RD_1__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RA_11_ ( input IOLDO, output RA11 );

  xo2iobuf0110 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));

  specify
    (IOLDO => RA11) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, GNDI, OPOS_dly, CLK_dly;

  mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module RA_10_ ( input IOLDO, output RA10 );

  xo2iobuf0110 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));

  specify
    (IOLDO => RA10) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
  wire   VCCI, OPOS_dly, CLK_dly, LSR_dly;

  mfflsre0114 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
    $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module mfflsre0114 ( input D0, SP, CK, LSR, output Q );

  FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
  defparam INST01.GSR = "DISABLED";
endmodule

module RA_9_ ( input PADDO, output RA9 );

  xo2iobuf0110 \RA_pad[9] ( .I(PADDO), .PAD(RA9));

  specify
    (PADDO => RA9) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_8_ ( input PADDO, output RA8 );

  xo2iobuf0110 \RA_pad[8] ( .I(PADDO), .PAD(RA8));

  specify
    (PADDO => RA8) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_7_ ( input PADDO, output RA7 );

  xo2iobuf0110 \RA_pad[7] ( .I(PADDO), .PAD(RA7));

  specify
    (PADDO => RA7) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_6_ ( input PADDO, output RA6 );

  xo2iobuf0110 \RA_pad[6] ( .I(PADDO), .PAD(RA6));

  specify
    (PADDO => RA6) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_5_ ( input PADDO, output RA5 );

  xo2iobuf0110 \RA_pad[5] ( .I(PADDO), .PAD(RA5));

  specify
    (PADDO => RA5) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_4_ ( input PADDO, output RA4 );

  xo2iobuf0110 \RA_pad[4] ( .I(PADDO), .PAD(RA4));

  specify
    (PADDO => RA4) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_3_ ( input PADDO, output RA3 );

  xo2iobuf0110 \RA_pad[3] ( .I(PADDO), .PAD(RA3));

  specify
    (PADDO => RA3) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_2_ ( input PADDO, output RA2 );

  xo2iobuf0110 \RA_pad[2] ( .I(PADDO), .PAD(RA2));

  specify
    (PADDO => RA2) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_1_ ( input PADDO, output RA1 );

  xo2iobuf0110 \RA_pad[1] ( .I(PADDO), .PAD(RA1));

  specify
    (PADDO => RA1) = (0:0:0,0:0:0);
  endspecify

endmodule

module RA_0_ ( input PADDO, output RA0 );

  xo2iobuf0110 \RA_pad[0] ( .I(PADDO), .PAD(RA0));

  specify
    (PADDO => RA0) = (0:0:0,0:0:0);
  endspecify

endmodule

module RBA_1_ ( input IOLDO, output RBA1 );

  xo2iobuf0110 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));

  specify
    (IOLDO => RBA1) = (0:0:0,0:0:0);
  endspecify

endmodule

module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module RBA_0_ ( input IOLDO, output RBA0 );

  xo2iobuf0110 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));

  specify
    (IOLDO => RBA0) = (0:0:0,0:0:0);
  endspecify

endmodule

module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK );
  wire   VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;

  mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), 
    .Q(IOLDO));
  vcc DRIVEVCC( .PWR1(VCCI));
  inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IOLDO) = (0:0:0,0:0:0);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
    $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
  endspecify

endmodule

module LED ( input PADDO, output LED );

  xo2iobuf0115 LED_pad( .I(PADDO), .PAD(LED));

  specify
    (PADDO => LED) = (0:0:0,0:0:0);
  endspecify

endmodule

module xo2iobuf0115 ( input I, output PAD );

  OB INST5( .I(I), .O(PAD));
endmodule

module nFWE ( output PADDI, input nFWE );

  xo2iobuf0116 nFWE_pad( .Z(PADDI), .PAD(nFWE));

  specify
    (nFWE => PADDI) = (0:0:0,0:0:0);
    $width (posedge nFWE, 0:0:0);
    $width (negedge nFWE, 0:0:0);
  endspecify

endmodule

module xo2iobuf0116 ( output Z, input PAD );

  IBPU INST1( .I(PAD), .O(Z));
endmodule

module nCRAS ( output PADDI, input nCRAS );

  xo2iobuf0116 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));

  specify
    (nCRAS => PADDI) = (0:0:0,0:0:0);
    $width (posedge nCRAS, 0:0:0);
    $width (negedge nCRAS, 0:0:0);
  endspecify

endmodule

module nCCAS ( output PADDI, input nCCAS );

  xo2iobuf0116 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));

  specify
    (nCCAS => PADDI) = (0:0:0,0:0:0);
    $width (posedge nCCAS, 0:0:0);
    $width (negedge nCCAS, 0:0:0);
  endspecify

endmodule

module Dout_7_ ( input PADDO, output Dout7 );

  xo2iobuf0110 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));

  specify
    (PADDO => Dout7) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_6_ ( input PADDO, output Dout6 );

  xo2iobuf0110 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));

  specify
    (PADDO => Dout6) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_5_ ( input PADDO, output Dout5 );

  xo2iobuf0110 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));

  specify
    (PADDO => Dout5) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_4_ ( input PADDO, output Dout4 );

  xo2iobuf0110 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));

  specify
    (PADDO => Dout4) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_3_ ( input PADDO, output Dout3 );

  xo2iobuf0110 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));

  specify
    (PADDO => Dout3) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_2_ ( input PADDO, output Dout2 );

  xo2iobuf0110 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));

  specify
    (PADDO => Dout2) = (0:0:0,0:0:0);
  endspecify

endmodule

module Dout_1_ ( input PADDO, output Dout1 );

  xo2iobuf0110 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));

  specify
    (PADDO => Dout1) = (0:0:0,0:0:0);
  endspecify

endmodule

module Din_7_ ( output PADDI, input Din7 );

  xo2iobuf0113 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));

  specify
    (Din7 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din7, 0:0:0);
    $width (negedge Din7, 0:0:0);
  endspecify

endmodule

module Din_7__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_6_ ( output PADDI, input Din6 );

  xo2iobuf0113 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));

  specify
    (Din6 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din6, 0:0:0);
    $width (negedge Din6, 0:0:0);
  endspecify

endmodule

module Din_6__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_5_ ( output PADDI, input Din5 );

  xo2iobuf0113 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));

  specify
    (Din5 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din5, 0:0:0);
    $width (negedge Din5, 0:0:0);
  endspecify

endmodule

module Din_5__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_4_ ( output PADDI, input Din4 );

  xo2iobuf0113 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));

  specify
    (Din4 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din4, 0:0:0);
    $width (negedge Din4, 0:0:0);
  endspecify

endmodule

module Din_4__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_3_ ( output PADDI, input Din3 );

  xo2iobuf0113 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));

  specify
    (Din3 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din3, 0:0:0);
    $width (negedge Din3, 0:0:0);
  endspecify

endmodule

module Din_3__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_2_ ( output PADDI, input Din2 );

  xo2iobuf0113 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));

  specify
    (Din2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din2, 0:0:0);
    $width (negedge Din2, 0:0:0);
  endspecify

endmodule

module Din_2__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[2] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_1_ ( output PADDI, input Din1 );

  xo2iobuf0113 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));

  specify
    (Din1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din1, 0:0:0);
    $width (negedge Din1, 0:0:0);
  endspecify

endmodule

module Din_1__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[1] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module Din_0_ ( output PADDI, input Din0 );

  xo2iobuf0113 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));

  specify
    (Din0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge Din0, 0:0:0);
    $width (negedge Din0, 0:0:0);
  endspecify

endmodule

module Din_0__MGIOL ( input DI, CLK, output IN );
  wire   VCCI, GNDI, DI_dly, CLK_dly;

  smuxlregsre \Bank_0io[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), 
    .Q(IN));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));

  specify
    (CLK => IN) = (0:0:0,0:0:0);
    $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
    $width (posedge CLK, 0:0:0);
    $width (negedge CLK, 0:0:0);
  endspecify

endmodule

module CROW_1_ ( output PADDI, input CROW1 );

  xo2iobuf0113 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));

  specify
    (CROW1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge CROW1, 0:0:0);
    $width (negedge CROW1, 0:0:0);
  endspecify

endmodule

module CROW_0_ ( output PADDI, input CROW0 );

  xo2iobuf0113 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));

  specify
    (CROW0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge CROW0, 0:0:0);
    $width (negedge CROW0, 0:0:0);
  endspecify

endmodule

module MAin_9_ ( output PADDI, input MAin9 );

  xo2iobuf0113 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));

  specify
    (MAin9 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin9, 0:0:0);
    $width (negedge MAin9, 0:0:0);
  endspecify

endmodule

module MAin_8_ ( output PADDI, input MAin8 );

  xo2iobuf0113 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));

  specify
    (MAin8 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin8, 0:0:0);
    $width (negedge MAin8, 0:0:0);
  endspecify

endmodule

module MAin_7_ ( output PADDI, input MAin7 );

  xo2iobuf0113 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));

  specify
    (MAin7 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin7, 0:0:0);
    $width (negedge MAin7, 0:0:0);
  endspecify

endmodule

module MAin_6_ ( output PADDI, input MAin6 );

  xo2iobuf0113 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));

  specify
    (MAin6 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin6, 0:0:0);
    $width (negedge MAin6, 0:0:0);
  endspecify

endmodule

module MAin_5_ ( output PADDI, input MAin5 );

  xo2iobuf0113 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));

  specify
    (MAin5 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin5, 0:0:0);
    $width (negedge MAin5, 0:0:0);
  endspecify

endmodule

module MAin_4_ ( output PADDI, input MAin4 );

  xo2iobuf0113 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));

  specify
    (MAin4 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin4, 0:0:0);
    $width (negedge MAin4, 0:0:0);
  endspecify

endmodule

module MAin_3_ ( output PADDI, input MAin3 );

  xo2iobuf0113 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));

  specify
    (MAin3 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin3, 0:0:0);
    $width (negedge MAin3, 0:0:0);
  endspecify

endmodule

module MAin_2_ ( output PADDI, input MAin2 );

  xo2iobuf0113 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));

  specify
    (MAin2 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin2, 0:0:0);
    $width (negedge MAin2, 0:0:0);
  endspecify

endmodule

module MAin_1_ ( output PADDI, input MAin1 );

  xo2iobuf0113 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));

  specify
    (MAin1 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin1, 0:0:0);
    $width (negedge MAin1, 0:0:0);
  endspecify

endmodule

module MAin_0_ ( output PADDI, input MAin0 );

  xo2iobuf0113 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));

  specify
    (MAin0 => PADDI) = (0:0:0,0:0:0);
    $width (posedge MAin0, 0:0:0);
    $width (negedge MAin0, 0:0:0);
  endspecify

endmodule

module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, 
    WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, 
    WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output 
    WBDATO0, WBDATO1, WBACKO );
  wire   VCCI, GNDI;

  EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), 
    .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), 
    .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), 
    .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), 
    .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), 
    .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), 
    .WBDATO1(WBDATO1), .WBDATO2(), .WBDATO3(), .WBDATO4(), .WBDATO5(), 
    .WBDATO6(), .WBDATO7(), .WBACKO(WBACKO), .WBCUFMIRQ(), .UFMSN(VCCI), 
    .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), .I2C1SCLO(), .I2C1SCLOEN(), 
    .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLI(GNDI), .I2C2SCLO(), 
    .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), .I2C2SDAOEN(), .I2C1IRQO(), 
    .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), .SPISCKEN(), .SPIMISOI(GNDI), 
    .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), .SPIMOSIO(), .SPIMOSIEN(), 
    .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), .SPIMCSN3(), .SPIMCSN4(), 
    .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), .SPICSNEN(), .SPISCSN(GNDI), 
    .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), .TCIC(GNDI), .TCINT(), .TCOC(), 
    .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), .PLLWEO(), .PLLADRO0(), 
    .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), .PLLADRO4(), .PLLDATO0(), 
    .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), .PLLDATO4(), .PLLDATO5(), 
    .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), .PLL0DATI1(GNDI), 
    .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), .PLL0DATI5(GNDI), 
    .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), .PLL1DATI0(GNDI), 
    .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), .PLL1DATI4(GNDI), 
    .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), .PLL1ACKI(GNDI));
  vcc DRIVEVCC( .PWR1(VCCI));
  gnd DRIVEGND( .PWR0(GNDI));
endmodule

module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, 
    WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, 
    WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, 
    WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, 
    WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output 
    I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input 
    I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, 
    I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, 
    input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output 
    SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, 
    SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, 
    input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, 
    PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, 
    PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, 
    PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, 
    PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, 
    PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI );
  wire   WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, 
         WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, 
         WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, 
         WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, 
         WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, 
         PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, 
         PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, 
         PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, 
         PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, 
         I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, 
         SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, 
         UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, 
         WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, 
         PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, 
         PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, 
         PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, 
         PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, 
         I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, 
         I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, 
         I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, 
         SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, 
         SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, 
         SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, 
         CFGWAKE_buf, CFGSTDBY_buf;

  EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), 
    .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), 
    .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), 
    .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), 
    .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), 
    .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), 
    .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), 
    .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), 
    .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), 
    .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), 
    .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), 
    .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), 
    .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), 
    .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), 
    .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), 
    .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), 
    .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), 
    .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), 
    .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), 
    .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), 
    .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), 
    .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), 
    .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), 
    .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), 
    .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), 
    .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), 
    .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), 
    .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), 
    .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), 
    .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), 
    .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), 
    .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), 
    .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), 
    .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), 
    .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), 
    .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), 
    .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), 
    .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), 
    .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), 
    .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), 
    .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), 
    .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf));
  defparam INST10.DEV_DENSITY = "640L";
  defparam INST10.EFB_I2C1 = "DISABLED";
  defparam INST10.EFB_I2C2 = "DISABLED";
  defparam INST10.EFB_SPI = "DISABLED";
  defparam INST10.EFB_TC = "DISABLED";
  defparam INST10.EFB_TC_PORTMODE = "WB";
  defparam INST10.EFB_UFM = "ENABLED";
  defparam INST10.EFB_WB_CLK_FREQ = "66.7";
  defparam INST10.GSR = "ENABLED";
  defparam INST10.I2C1_ADDRESSING = "7BIT";
  defparam INST10.I2C1_BUS_PERF = "100kHz";
  defparam INST10.I2C1_CLK_DIVIDER = 1;
  defparam INST10.I2C1_GEN_CALL = "DISABLED";
  defparam INST10.I2C1_SLAVE_ADDR = "0b1000001";
  defparam INST10.I2C1_WAKEUP = "DISABLED";
  defparam INST10.I2C2_ADDRESSING = "7BIT";
  defparam INST10.I2C2_BUS_PERF = "100kHz";
  defparam INST10.I2C2_CLK_DIVIDER = 1;
  defparam INST10.I2C2_GEN_CALL = "DISABLED";
  defparam INST10.I2C2_SLAVE_ADDR = "0b1000010";
  defparam INST10.I2C2_WAKEUP = "DISABLED";
  defparam INST10.SPI_CLK_DIVIDER = 1;
  defparam INST10.SPI_CLK_INV = "DISABLED";
  defparam INST10.SPI_INTR_RXOVR = "DISABLED";
  defparam INST10.SPI_INTR_RXRDY = "DISABLED";
  defparam INST10.SPI_INTR_TXOVR = "DISABLED";
  defparam INST10.SPI_INTR_TXRDY = "DISABLED";
  defparam INST10.SPI_LSB_FIRST = "DISABLED";
  defparam INST10.SPI_MODE = "MASTER";
  defparam INST10.SPI_PHASE_ADJ = "DISABLED";
  defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED";
  defparam INST10.SPI_WAKEUP = "DISABLED";
  defparam INST10.TC_CCLK_SEL = 1;
  defparam INST10.TC_ICAPTURE = "DISABLED";
  defparam INST10.TC_ICR_INT = "OFF";
  defparam INST10.TC_MODE = "CTCM";
  defparam INST10.TC_OCR_INT = "OFF";
  defparam INST10.TC_OCR_SET = 32767;
  defparam INST10.TC_OC_MODE = "TOGGLE";
  defparam INST10.TC_OVERFLOW = "DISABLED";
  defparam INST10.TC_OV_INT = "OFF";
  defparam INST10.TC_RESETN = "ENABLED";
  defparam INST10.TC_SCLK_SEL = "PCLOCK";
  defparam INST10.TC_TOP_SEL = "OFF";
  defparam INST10.TC_TOP_SET = 65535;
  defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED";
  defparam INST10.UFM_INIT_FILE_FORMAT = "HEX";
  defparam INST10.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem";
  defparam INST10.UFM_INIT_PAGES = 1;
  defparam INST10.UFM_INIT_START_PAGE = 190;
  EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), 
    .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), 
    .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), 
    .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), 
    .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), 
    .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), 
    .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), 
    .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), 
    .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), 
    .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), 
    .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), 
    .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), 
    .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), 
    .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), 
    .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), 
    .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), 
    .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), 
    .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), 
    .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), 
    .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), 
    .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), 
    .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), 
    .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), 
    .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), 
    .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), 
    .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), 
    .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), 
    .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), 
    .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), 
    .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), 
    .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), 
    .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), 
    .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), 
    .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), 
    .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), 
    .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), 
    .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), 
    .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), 
    .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), 
    .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), 
    .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), 
    .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), 
    .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), 
    .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), 
    .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), 
    .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), 
    .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), 
    .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), 
    .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), 
    .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), 
    .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), 
    .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), 
    .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), 
    .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), 
    .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), 
    .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), 
    .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), 
    .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), 
    .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), 
    .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), 
    .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), 
    .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), 
    .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), 
    .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), 
    .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), 
    .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), 
    .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), 
    .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), 
    .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), 
    .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), 
    .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), 
    .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), 
    .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), 
    .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), 
    .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), 
    .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), 
    .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), 
    .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), 
    .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), 
    .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), 
    .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), 
    .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), 
    .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), 
    .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), 
    .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), 
    .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), 
    .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), 
    .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), 
    .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), 
    .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), 
    .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), 
    .CFGSTDBYin(CFGSTDBY_buf));
endmodule

module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, 
    output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, 
    output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output 
    WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output 
    WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output 
    WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output 
    WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output 
    WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output 
    WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output 
    WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output 
    WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output 
    PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, 
    output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input 
    PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, 
    input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output 
    PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, 
    output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input 
    PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, 
    input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output 
    PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, 
    output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input 
    I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, 
    input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, 
    input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, 
    input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, 
    input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input 
    TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input 
    WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input 
    WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input 
    WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input 
    WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input 
    WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input 
    PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, 
    input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, 
    input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, 
    input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, 
    input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, 
    input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, 
    input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, 
    input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, 
    input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output 
    I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, 
    output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input 
    I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, 
    input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output 
    I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, 
    output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, 
    output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input 
    SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, 
    input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output 
    SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, 
    output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, 
    output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, 
    output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, 
    output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, 
    output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, 
    output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin );
  wire   WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, 
         WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, 
         WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, 
         WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, 
         WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly;

  BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout));
  BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout));
  BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout));
  BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout));
  BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout));
  BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out));
  BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out));
  BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out));
  BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out));
  BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out));
  BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out));
  BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out));
  BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out));
  BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out));
  BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out));
  BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out));
  BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out));
  BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out));
  BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out));
  BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out));
  BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out));
  BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out));
  BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out));
  BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out));
  BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out));
  BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out));
  BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out));
  BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out));
  BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out));
  BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout));
  BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out));
  BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out));
  BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out));
  BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out));
  BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out));
  BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out));
  BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out));
  BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out));
  BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout));
  BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout));
  BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout));
  BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout));
  BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout));
  BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout));
  BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout));
  BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout));
  BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout));
  BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout));
  BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout));
  BUFBA TCIC_buf( .A(TCICin), .Z(TCICout));
  BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout));
  BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out));
  BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out));
  BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out));
  BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out));
  BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out));
  BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out));
  BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out));
  BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out));
  BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout));
  BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout));
  BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout));
  BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout));
  BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout));
  BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout));
  BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out));
  BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out));
  BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out));
  BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out));
  BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out));
  BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out));
  BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out));
  BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out));
  BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out));
  BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out));
  BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out));
  BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out));
  BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out));
  BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout));
  BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout));
  BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout));
  BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout));
  BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout));
  BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout));
  BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout));
  BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout));
  BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout));
  BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout));
  BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout));
  BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout));
  BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout));
  BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout));
  BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout));
  BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout));
  BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out));
  BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out));
  BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out));
  BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out));
  BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out));
  BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out));
  BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out));
  BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out));
  BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout));
  BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout));
  BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout));
  BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout));
  BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout));
  BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout));
  BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout));

  specify
    (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0);
    (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0);
    (WBCLKIin => WBACKOout) = (0:0:0,0:0:0);
    $setuphold 
      (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly);
    $setuphold 
      (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly);
    $setuphold 
      (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly);
    $width (posedge WBCLKIin, 0:0:0);
    $width (negedge WBCLKIin, 0:0:0);
  endspecify

endmodule