Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.12.1.454
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 15 05:03:20 2023
Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
Synthesis options:
The -a option is MachXO.
The -s option is 3.
The -t option is TQFP100.
The -d option is LCMXO256C.
Using package TQFP100.
Using performance grade 3.
##########################################################
### Lattice Family : MachXO
### Device : LCMXO256C
### Package : TQFP100
### Speed : 3
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = RAM2GS.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added)
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
NGD file = RAM2GS_LCMXO256C_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
Top module name (Verilog): RAM2GS
INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Top-level module name = RAM2GS.
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
GSR will not be inferred because no asynchronous signal was found in the netlist.
WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in RAM2GS_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
################### Begin Area Report (RAM2GS)######################
Number of register bits => 102 of 490 (20 % )
BB => 8
CCU2 => 9
FD1P3AX => 28
FD1P3AY => 3
FD1P3IX => 2
FD1S3AX => 47
FD1S3AY => 1
FD1S3IX => 16
FD1S3JX => 5
GSR => 1
IB => 26
INV => 3
OB => 33
ORCALUT4 => 127
PFUMX => 6
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 4
Net : RCLK_c, loads : 62
Net : PHI2_c, loads : 11
Net : nCCAS_c, loads : 2
Net : nCRAS_c, loads : 2
Clock Enable Nets
Number of Clock Enables: 13
Top 10 highest fanout Clock Enables:
Net : RCLK_c_enable_23, loads : 16
Net : RCLK_c_enable_4, loads : 3
Net : PHI2_N_120_enable_6, loads : 3
Net : RCLK_c_enable_24, loads : 2
Net : RCLK_c_enable_12, loads : 1
Net : PHI2_N_120_enable_1, loads : 1
Net : PHI2_N_120_enable_4, loads : 1
Net : RCLK_c_enable_3, loads : 1
Net : PHI2_N_120_enable_5, loads : 1
Net : RCLK_c_enable_11, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : InitReady, loads : 17
Net : Ready, loads : 17
Net : RCLK_c_enable_23, loads : 16
Net : nCRAS_N_9, loads : 15
Net : RASr2, loads : 13
Net : nRowColSel, loads : 13
Net : n2477, loads : 13
Net : MAin_c_0, loads : 12
Net : nRowColSel_N_35, loads : 12
Net : Din_c_6, loads : 11
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
Peak Memory Usage: 50.672 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.516 secs
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