mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-30 18:51:48 +00:00
94 lines
4.2 KiB
Verilog
94 lines
4.2 KiB
Verilog
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.3.469 */
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/* Module Version: 5.7 */
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/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 */
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/* Sun Jul 14 22:23:22 2024 */
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`timescale 1 ns / 1 ps
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module RPLL (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */;
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input wire CLKI;
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output wire CLKOP;
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wire LOCK;
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wire CLKOP_t;
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wire scuba_vlo;
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VLO scuba_vlo_inst (.Z(scuba_vlo));
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defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
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defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
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defparam PLLInst_0.MRST_ENA = "DISABLED" ;
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defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
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defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
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defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
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defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
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defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
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defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
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defparam PLLInst_0.CLKOS_FPHASE = 0 ;
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defparam PLLInst_0.CLKOS_CPHASE = 0 ;
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defparam PLLInst_0.CLKOP_FPHASE = 0 ;
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defparam PLLInst_0.CLKOP_CPHASE = 7 ;
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defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
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defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
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defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
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defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
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defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
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defparam PLLInst_0.FRACN_DIV = 0 ;
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defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
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defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
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defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
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defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
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defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ;
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defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
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defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
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defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
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defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
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defparam PLLInst_0.CLKOS3_DIV = 1 ;
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defparam PLLInst_0.CLKOS2_DIV = 1 ;
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defparam PLLInst_0.CLKOS_DIV = 1 ;
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defparam PLLInst_0.CLKOP_DIV = 8 ;
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defparam PLLInst_0.CLKFB_DIV = 6 ;
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defparam PLLInst_0.CLKI_DIV = 13 ;
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defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
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EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
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.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
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.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
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.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
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.ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
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.ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
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.PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
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.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
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.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
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.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
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.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(),
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.LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(), .PLLACK(),
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.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
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.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
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/* synthesis FREQUENCY_PIN_CLKOP="61.384615" */
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/* synthesis FREQUENCY_PIN_CLKI="133.000000" */
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/* synthesis ICP_CURRENT="7" */
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/* synthesis LPF_RESISTOR="8" */;
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assign CLKOP = CLKOP_t;
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// exemplar begin
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 61.384615
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// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 133.000000
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// exemplar attribute PLLInst_0 ICP_CURRENT 7
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// exemplar attribute PLLInst_0 LPF_RESISTOR 8
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// exemplar end
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endmodule
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