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316 lines
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<HEAD><TITLE>Place & Route Report</TITLE>
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Sat Jan 06 06:25:12 2024
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C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
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RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
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RAM2GS_LCMXO640C_impl1.prf -gui -msgset
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//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml
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Preference file: RAM2GS_LCMXO640C_impl1.prf.
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<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 7.529 0 0.273 0 08 Completed
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* : Design saved.
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Total (real) run time for 1-seed: 8 secs
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par done!
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Note: user must run 'Trace' for timing closure signoff.
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Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
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Sat Jan 06 06:25:12 2024
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<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
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PAR: Place And Route Diamond (64-bit) 3.12.1.454.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
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Preference file: RAM2GS_LCMXO640C_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO640C
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Package: TQFP100
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Performance: 3
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Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.17.
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Performance Hardware Data Status: Version 1.124.
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License checked out.
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Ignore Preference Error(s): True
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<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
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PIO (prelim) 67/159 42% used
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67/74 90% bonded
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SLICE 76/320 23% used
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Number of Signals: 266
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Number of Connections: 681
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Pin Constraint Summary:
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67 out of 67 pins locked (100% locked).
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The following 2 signals are selected to use the primary clock routing resources:
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RCLK_c (driver: RCLK, clk load #: 32)
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PHI2_c (driver: PHI2, clk load #: 14)
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The following 1 signal is selected to use the secondary clock routing resources:
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nCRAS_c (driver: nCRAS, clk load #: 8, sr load #: 0, ce load #: 0)
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No signal is selected as Global Set/Reset.
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Starting Placer Phase 0.
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.......
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Finished Placer Phase 0. REAL time: 0 secs
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Starting Placer Phase 1.
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...............
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Placer score = 758162.
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Finished Placer Phase 1. REAL time: 6 secs
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Starting Placer Phase 2.
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.
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Placer score = 756179
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Finished Placer Phase 2. REAL time: 7 secs
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<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
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Global Clock Resources:
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CLK_PIN : 1 out of 4 (25%)
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General PIO: 1 out of 160 (0%)
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Global Clocks:
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PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 32
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PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 14
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SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 8, ce load = 0, sr load = 0
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PRIMARY : 2 out of 4 (50%)
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SECONDARY: 1 out of 4 (25%)
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I/O Usage Summary (final):
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67 out of 159 (42.1%) PIO sites used.
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67 out of 74 (90.5%) bonded PIO sites used.
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Number of PIO comps: 67; differential: 0.
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Number of Vref pins used: 0.
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I/O Bank Usage Summary:
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+----------+----------------+------------+------------+------------+
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| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
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+----------+----------------+------------+------------+------------+
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| 0 | 18 / 18 (100%) | 3.3V | - | - |
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| 1 | 18 / 21 ( 85%) | 3.3V | - | - |
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| 2 | 13 / 14 ( 92%) | - | - | - |
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| 3 | 18 / 21 ( 85%) | 3.3V | - | - |
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+----------+----------------+------------+------------+------------+
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Total placer CPU time: 6 secs
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Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
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0 connections routed; 681 unrouted.
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Starting router resource preassignment
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WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
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WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=nCCAS_c loads=8 clock_loads=4
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Completed router resource preassignment. Real time: 7 secs
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Start NBR router at 06:25:19 01/06/24
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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in the earlier iterations. In each iteration, it tries to
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solve the conflicts while keeping the critical connections
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routed as short as possible. The routing process is said to
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be completed when no conflicts exist and all connections
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are routed.
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Note: NBR uses a different method to calculate timing slacks. The
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worst slack and total negative slack may not be the same as
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that in TRCE report. You should always run TRCE to verify
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your design.
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*****************************************************************
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Start NBR special constraint process at 06:25:19 01/06/24
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Start NBR section for initial routing at 06:25:19 01/06/24
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Level 1, iteration 1
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0(0.00%) conflict; 596(87.52%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.600ns/0.000ns; real time: 7 secs
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Level 2, iteration 1
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0(0.00%) conflict; 592(86.93%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.684ns/0.000ns; real time: 7 secs
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Level 3, iteration 1
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0(0.00%) conflict; 592(86.93%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.684ns/0.000ns; real time: 7 secs
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Level 4, iteration 1
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8(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs
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Info: Initial congestion level at 75% usage is 0
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Info: Initial congestion area at 75% usage is 0 (0.00%)
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Start NBR section for normal routing at 06:25:19 01/06/24
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Level 4, iteration 1
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2(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs
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Level 4, iteration 2
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1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs
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Level 4, iteration 3
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1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs
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Level 4, iteration 4
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1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.653ns/0.000ns; real time: 7 secs
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Level 4, iteration 5
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.529ns/0.000ns; real time: 7 secs
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Start NBR section for setup/hold timing optimization with effort level 3 at 06:25:19 01/06/24
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Start NBR section for re-routing at 06:25:20 01/06/24
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 7.529ns/0.000ns; real time: 8 secs
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Start NBR section for post-routing at 06:25:20 01/06/24
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End NBR router with 0 unrouted connection
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NBR Summary
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-----------
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Number of unrouted connections : 0 (0.00%)
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Number of connections with timing violations : 0 (0.00%)
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Estimated worst slack<setup> : 7.529ns
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Timing score<setup> : 0
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=nCCAS_c loads=8 clock_loads=4
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Total CPU time 7 secs
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Total REAL time: 8 secs
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Completely routed.
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End of route. 681 routed (100.00%); 0 unrouted.
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Hold time timing score: 0, hold timing errors: 0
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Timing score: 0
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Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Run status = Completed
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PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Worst slack<setup/<ns>> = 7.529
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PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
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PAR_SUMMARY::Worst slack<hold /<ns>> = 0.273
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PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
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PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 8 secs
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Total REAL time to completion: 8 secs
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par done!
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Note: user must run 'Trace' for timing closure signoff.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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