RAM2GS/CPLD/RAM2GS-MAX.mif
2024-01-06 21:52:05 -05:00

29 lines
1.1 KiB
Plaintext

-- Copyright (C) 2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- Quartus Prime generated Memory Initialization File (.mif)
WIDTH=16;
DEPTH=512;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
[000..0FD] : 0000;
0FE : 7FFF;
[0FF..1FF] : FFFF;
END;