212 lines
8.1 KiB
Plaintext
212 lines
8.1 KiB
Plaintext
|
|
Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
|
|
Mon Aug 16 21:32:27 2021
|
|
|
|
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
|
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
|
|
Preference file: RAM2GS_LCMXO256C_impl1.prf.
|
|
Placement level-cost: 5-1.
|
|
Routing Iterations: 6
|
|
|
|
Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO256C
|
|
Package: TQFP100
|
|
Performance: 3
|
|
Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
|
Package Status: Final Version 1.19.
|
|
Performance Hardware Data Status: Version 1.124.
|
|
License checked out.
|
|
|
|
|
|
Ignore Preference Error(s): True
|
|
Device utilization summary:
|
|
|
|
PIO (prelim) 67/79 84% used
|
|
67/78 85% bonded
|
|
SLICE 65/128 50% used
|
|
|
|
|
|
|
|
Number of Signals: 252
|
|
Number of Connections: 618
|
|
|
|
Pin Constraint Summary:
|
|
67 out of 67 pins locked (100% locked).
|
|
|
|
The following 4 signals are selected to use the primary clock routing resources:
|
|
RCLK_c (driver: RCLK, clk load #: 39)
|
|
PHI2_c (driver: PHI2, clk load #: 13)
|
|
nCCAS_c (driver: nCCAS, clk load #: 4)
|
|
nCRAS_c (driver: nCRAS, clk load #: 7)
|
|
|
|
No signal is selected as secondary clock.
|
|
|
|
No signal is selected as Global Set/Reset.
|
|
Starting Placer Phase 0.
|
|
........
|
|
Finished Placer Phase 0. REAL time: 0 secs
|
|
|
|
Starting Placer Phase 1.
|
|
...............
|
|
Placer score = 586066.
|
|
Finished Placer Phase 1. REAL time: 6 secs
|
|
|
|
Starting Placer Phase 2.
|
|
.
|
|
Placer score = 584668
|
|
Finished Placer Phase 2. REAL time: 6 secs
|
|
|
|
|
|
------------------ Clock Report ------------------
|
|
|
|
Global Clock Resources:
|
|
CLK_PIN : 1 out of 4 (25%)
|
|
General PIO: 3 out of 80 (3%)
|
|
|
|
Global Clocks:
|
|
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
|
|
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
|
|
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
|
|
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
|
|
|
|
PRIMARY : 4 out of 4 (100%)
|
|
SECONDARY: 0 out of 4 (0%)
|
|
|
|
--------------- End of Clock Report ---------------
|
|
|
|
|
|
I/O Usage Summary (final):
|
|
67 out of 79 (84.8%) PIO sites used.
|
|
67 out of 78 (85.9%) bonded PIO sites used.
|
|
Number of PIO comps: 67; differential: 0.
|
|
Number of Vref pins used: 0.
|
|
|
|
I/O Bank Usage Summary:
|
|
+----------+----------------+------------+------------+------------+
|
|
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
|
|
+----------+----------------+------------+------------+------------+
|
|
| 0 | 36 / 41 ( 87%) | 3.3V | - | - |
|
|
| 1 | 31 / 37 ( 83%) | 3.3V | - | - |
|
|
+----------+----------------+------------+------------+------------+
|
|
|
|
Total placer CPU time: 6 secs
|
|
|
|
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
|
|
|
0 connections routed; 618 unrouted.
|
|
Starting router resource preassignment
|
|
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
|
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
|
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
|
|
|
Completed router resource preassignment. Real time: 6 secs
|
|
|
|
Start NBR router at 21:32:33 08/16/21
|
|
|
|
*****************************************************************
|
|
Info: NBR allows conflicts(one node used by more than one signal)
|
|
in the earlier iterations. In each iteration, it tries to
|
|
solve the conflicts while keeping the critical connections
|
|
routed as short as possible. The routing process is said to
|
|
be completed when no conflicts exist and all connections
|
|
are routed.
|
|
Note: NBR uses a different method to calculate timing slacks. The
|
|
worst slack and total negative slack may not be the same as
|
|
that in TRCE report. You should always run TRCE to verify
|
|
your design.
|
|
*****************************************************************
|
|
|
|
Start NBR special constraint process at 21:32:33 08/16/21
|
|
|
|
Start NBR section for initial routing at 21:32:33 08/16/21
|
|
Level 1, iteration 1
|
|
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
|
|
Level 2, iteration 1
|
|
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
|
|
Level 3, iteration 1
|
|
0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs
|
|
Level 4, iteration 1
|
|
23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
|
|
|
Info: Initial congestion level at 75% usage is 0
|
|
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
|
|
|
Start NBR section for normal routing at 21:32:33 08/16/21
|
|
Level 1, iteration 1
|
|
0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
|
Level 4, iteration 1
|
|
8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
|
Level 4, iteration 2
|
|
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
|
Level 4, iteration 3
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
|
|
|
Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
|
|
|
|
Start NBR section for re-routing at 21:32:33 08/16/21
|
|
Level 4, iteration 1
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
|
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
|
|
|
Start NBR section for post-routing at 21:32:33 08/16/21
|
|
|
|
End NBR router with 0 unrouted connection
|
|
|
|
NBR Summary
|
|
-----------
|
|
Number of unrouted connections : 0 (0.00%)
|
|
Number of connections with timing violations : 0 (0.00%)
|
|
Estimated worst slack<setup> : 2.023ns
|
|
Timing score<setup> : 0
|
|
-----------
|
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
|
|
|
|
|
|
|
Total CPU time 6 secs
|
|
Total REAL time: 7 secs
|
|
Completely routed.
|
|
End of route. 618 routed (100.00%); 0 unrouted.
|
|
|
|
Hold time timing score: 0, hold timing errors: 0
|
|
|
|
Timing score: 0
|
|
|
|
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
|
|
|
|
|
All signals are completely routed.
|
|
|
|
|
|
PAR_SUMMARY::Run status = Completed
|
|
PAR_SUMMARY::Number of unrouted conns = 0
|
|
PAR_SUMMARY::Worst slack<setup/<ns>> = 2.023
|
|
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
|
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.339
|
|
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
|
PAR_SUMMARY::Number of errors = 0
|
|
|
|
Total CPU time to completion: 6 secs
|
|
Total REAL time to completion: 7 secs
|
|
|
|
par done!
|
|
|
|
Note: user must run 'Trace' for timing closure signoff.
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|