377 lines
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377 lines
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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Mon Aug 16 21:32:26 2021
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: RAM2GS
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
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122 items scored, 121 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 10.378ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
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Destination: FD1P3AX SP CmdUFMCS_385 (to PHI2_c -)
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Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
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Constraint Details:
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12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
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2.500ns delay constraint less
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0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
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Path Details: Bank_i5 to CmdUFMCS_385
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
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Route 1 e 1.220 Bank[5]
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LUT4 --- 0.390 B to Z i1856_4_lut
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Route 1 e 1.220 n2166
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LUT4 --- 0.390 B to Z i12_4_lut
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Route 1 e 1.220 n26
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LUT4 --- 0.390 B to Z i13_4_lut
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Route 4 e 1.552 n1285
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LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
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Route 3 e 1.483 n2290
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LUT4 --- 0.390 D to Z i3_4_lut
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Route 3 e 1.483 XOR8MEG_N_112
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LUT4 --- 0.390 A to Z i2_3_lut_4_lut
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Route 3 e 1.483 PHI2_N_114_enable_7
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--------
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12.614 (23.4% logic, 76.6% route), 7 logic levels.
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Error: The following path violates requirements by 10.378ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
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Destination: FD1P3AX SP CmdUFMSDI_387 (to PHI2_c -)
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Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
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Constraint Details:
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12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
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2.500ns delay constraint less
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0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
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Path Details: Bank_i5 to CmdUFMSDI_387
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
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Route 1 e 1.220 Bank[5]
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LUT4 --- 0.390 B to Z i1856_4_lut
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Route 1 e 1.220 n2166
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LUT4 --- 0.390 B to Z i12_4_lut
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Route 1 e 1.220 n26
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LUT4 --- 0.390 B to Z i13_4_lut
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Route 4 e 1.552 n1285
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LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
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Route 3 e 1.483 n2290
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LUT4 --- 0.390 D to Z i3_4_lut
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Route 3 e 1.483 XOR8MEG_N_112
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LUT4 --- 0.390 A to Z i2_3_lut_4_lut
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Route 3 e 1.483 PHI2_N_114_enable_7
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--------
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12.614 (23.4% logic, 76.6% route), 7 logic levels.
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Error: The following path violates requirements by 10.378ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
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Destination: FD1P3AX SP CmdUFMCLK_386 (to PHI2_c -)
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Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
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Constraint Details:
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12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
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2.500ns delay constraint less
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0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
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Path Details: Bank_i5 to CmdUFMCLK_386
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
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Route 1 e 1.220 Bank[5]
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LUT4 --- 0.390 B to Z i1856_4_lut
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Route 1 e 1.220 n2166
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LUT4 --- 0.390 B to Z i12_4_lut
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Route 1 e 1.220 n26
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LUT4 --- 0.390 B to Z i13_4_lut
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Route 4 e 1.552 n1285
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LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
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Route 3 e 1.483 n2290
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LUT4 --- 0.390 D to Z i3_4_lut
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Route 3 e 1.483 XOR8MEG_N_112
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LUT4 --- 0.390 A to Z i2_3_lut_4_lut
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Route 3 e 1.483 PHI2_N_114_enable_7
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--------
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12.614 (23.4% logic, 76.6% route), 7 logic levels.
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Warning: 12.878 ns is the maximum delay for this constraint.
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
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369 items scored, 244 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 6.291ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_577__i12 (from RCLK_c +)
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Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +)
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Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
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Constraint Details:
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11.027ns data_path FS_577__i12 to LEDEN_392 violates
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5.000ns delay constraint less
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0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
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Path Details: FS_577__i12 to LEDEN_392
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c)
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Route 3 e 1.603 FS[12]
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LUT4 --- 0.390 C to Z i4_4_lut
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Route 3 e 1.483 n10
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LUT4 --- 0.390 B to Z i5_3_lut_rep_23
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Route 4 e 1.552 n2300
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LUT4 --- 0.390 B to Z i4_3_lut_4_lut
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Route 1 e 1.220 n11
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LUT4 --- 0.390 C to Z i2_4_lut_adj_4
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Route 2 e 1.386 n2119
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LUT4 --- 0.390 C to Z i2_3_lut_3_lut
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Route 1 e 1.220 RCLK_c_enable_25
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--------
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11.027 (23.2% logic, 76.8% route), 6 logic levels.
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Error: The following path violates requirements by 6.291ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_577__i12 (from RCLK_c +)
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Destination: FD1P3AX SP n8MEGEN_391 (to RCLK_c +)
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Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
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Constraint Details:
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11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
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5.000ns delay constraint less
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0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
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Path Details: FS_577__i12 to n8MEGEN_391
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c)
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Route 3 e 1.603 FS[12]
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LUT4 --- 0.390 C to Z i4_4_lut
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Route 3 e 1.483 n10
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LUT4 --- 0.390 B to Z i5_3_lut_rep_23
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Route 4 e 1.552 n2300
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LUT4 --- 0.390 B to Z i4_3_lut_4_lut
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Route 1 e 1.220 n11
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LUT4 --- 0.390 C to Z i2_4_lut_adj_4
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Route 2 e 1.386 n2119
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LUT4 --- 0.390 D to Z i1248_4_lut
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Route 1 e 1.220 RCLK_c_enable_7
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--------
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11.027 (23.2% logic, 76.8% route), 6 logic levels.
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Error: The following path violates requirements by 6.291ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_577__i13 (from RCLK_c +)
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Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +)
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Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
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Constraint Details:
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11.027ns data_path FS_577__i13 to LEDEN_392 violates
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5.000ns delay constraint less
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0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
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Path Details: FS_577__i13 to LEDEN_392
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.613 CK to Q FS_577__i13 (from RCLK_c)
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Route 3 e 1.603 FS[13]
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LUT4 --- 0.390 B to Z i4_4_lut
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Route 3 e 1.483 n10
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LUT4 --- 0.390 B to Z i5_3_lut_rep_23
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Route 4 e 1.552 n2300
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LUT4 --- 0.390 B to Z i4_3_lut_4_lut
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Route 1 e 1.220 n11
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LUT4 --- 0.390 C to Z i2_4_lut_adj_4
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Route 2 e 1.386 n2119
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LUT4 --- 0.390 C to Z i2_3_lut_3_lut
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Route 1 e 1.220 RCLK_c_enable_25
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--------
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11.027 (23.2% logic, 76.8% route), 6 logic levels.
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Warning: 11.291 ns is the maximum delay for this constraint.
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 5.000000 -name | | |
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clk3 [get_nets nCCAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk2 [get_nets nCRAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk1 [get_nets PHI2_c] | 5.000 ns| 25.756 ns| 7 *
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create_clock -period 5.000000 -name | | |
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clk0 [get_nets RCLK_c] | 5.000 ns| 11.291 ns| 6 *
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--------------------------------------------------------------------------------
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2 constraints not met.
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--------------------------------------------------------------------------------
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Critical Nets | Loads| Errors| % of total
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--------------------------------------------------------------------------------
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n1285 | 4| 112| 30.68%
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n26 | 1| 70| 19.18%
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RCLK_c_enable_23 | 16| 64| 17.53%
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n2290 | 3| 64| 17.53%
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XOR8MEG_N_112 | 3| 54| 14.79%
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n2119 | 2| 48| 13.15%
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n2166 | 1| 42| 11.51%
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--------------------------------------------------------------------------------
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 365 Score: 2309745
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Constraints cover 495 paths, 177 nets, and 464 connections (66.5% coverage)
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Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes
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CPU_TIME_REPORT: 0 secs
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