3315 lines
212 KiB
HTML
3315 lines
212 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<META content="MSHTML 6.00.2900.2180" name=GENERATOR></HEAD>
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</B>
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<BR><PRE><A name="Report Header"></A>
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
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Mon Aug 16 20:23:38 2021
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Design file: RAM2GS
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Device,speed: LCMXO256C,3
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Report level: verbose report, limited to 10 items per preference
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--------------------------------------------------------------------------------
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Derating parameters
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-------------------
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Voltage: 3.300 V
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</A><A name="PERIOD NET 'PHI2_c' 350.000000 ns"></A>================================================================================
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Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
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10 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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<font color=#000000>
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Passed: The following path meets requirements by 162.969ns (weighted slack = 325.938ns)
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:SLICE_93">Bank_i0</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
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Destination: FF Data in <A href="#@comp:SLICE_23">Cmdn8MEGEN_377</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
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Delay: 11.766ns (23.7% logic, 76.3% route), 7 logic levels.
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Constraint Details:
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11.766ns physical path delay SLICE_93 to SLICE_23 meets
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175.000ns delay constraint less
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0.000ns skew and
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0.265ns CE_SET requirement (totaling 174.735ns) by 162.969ns
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Physical Path Details:
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q0,SLICE_93:ROUTE, 1.086,R2C2B.Q0,R2C3A.B1,Bank_0:CTOF_DEL, 0.371,R2C3A.B1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 0.727,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.371,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 2.130,R6C3A.F0,R7C3A.CE,PHI2_N_114_enable_6">Data path</A> SLICE_93 to SLICE_23:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q0 <A href="#@comp:SLICE_93">SLICE_93</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
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ROUTE 1 1.086<A href="#@net:Bank_0:R2C2B.Q0:R2C3A.B1:1.086"> R2C2B.Q0 to R2C3A.B1 </A> <A href="#@net:Bank_0">Bank_0</A>
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CTOF_DEL --- 0.371 R2C3A.B1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
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ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
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CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
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ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
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CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
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ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
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CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
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ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
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CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
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ROUTE 3 0.727<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.727"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
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CTOF_DEL --- 0.371 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
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ROUTE 2 2.130<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C3A.CE:2.130"> R6C3A.F0 to R7C3A.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
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--------
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11.766 (23.7% logic, 76.3% route), 7 logic levels.
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Clock Skew Details:
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_93:
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Name Fanout Delay (ns) Site Resource
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ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.924"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
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--------
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3.924 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C3A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_23:
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Name Fanout Delay (ns) Site Resource
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ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C3A.CLK:3.924"> 39.PADDI to R7C3A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
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--------
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3.924 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 163.029ns (weighted slack = 326.058ns)
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:SLICE_98">Bank_i6</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
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Destination: FF Data in <A href="#@comp:SLICE_23">Cmdn8MEGEN_377</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
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Delay: 11.706ns (23.8% logic, 76.2% route), 7 logic levels.
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Constraint Details:
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11.706ns physical path delay SLICE_98 to SLICE_23 meets
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175.000ns delay constraint less
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0.000ns skew and
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0.265ns CE_SET requirement (totaling 174.735ns) by 163.029ns
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Physical Path Details:
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2C.CLK,R2C2C.Q0,SLICE_98:ROUTE, 1.026,R2C2C.Q0,R2C3A.A1,Bank_6:CTOF_DEL, 0.371,R2C3A.A1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 0.727,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.371,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 2.130,R6C3A.F0,R7C3A.CE,PHI2_N_114_enable_6">Data path</A> SLICE_98 to SLICE_23:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
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ROUTE 1 1.026<A href="#@net:Bank_6:R2C2C.Q0:R2C3A.A1:1.026"> R2C2C.Q0 to R2C3A.A1 </A> <A href="#@net:Bank_6">Bank_6</A>
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CTOF_DEL --- 0.371 R2C3A.A1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
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ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
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CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
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ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
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CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
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ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
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CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
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ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
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CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
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ROUTE 3 0.727<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.727"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
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CTOF_DEL --- 0.371 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
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ROUTE 2 2.130<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C3A.CE:2.130"> R6C3A.F0 to R7C3A.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
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--------
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11.706 (23.8% logic, 76.2% route), 7 logic levels.
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Clock Skew Details:
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
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Name Fanout Delay (ns) Site Resource
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ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2C.CLK:3.924"> 39.PADDI to R2C2C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
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--------
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3.924 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C3A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_23:
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Name Fanout Delay (ns) Site Resource
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ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C3A.CLK:3.924"> 39.PADDI to R7C3A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
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--------
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3.924 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 163.113ns (weighted slack = 326.226ns)
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:SLICE_93">Bank_i0</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
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Destination: FF Data in <A href="#@comp:SLICE_94">XOR8MEG_376</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
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Delay: 11.622ns (24.0% logic, 76.0% route), 7 logic levels.
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Constraint Details:
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11.622ns physical path delay SLICE_93 to SLICE_94 meets
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175.000ns delay constraint less
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0.000ns skew and
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0.265ns CE_SET requirement (totaling 174.735ns) by 163.113ns
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Physical Path Details:
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q0,SLICE_93:ROUTE, 1.086,R2C2B.Q0,R2C3A.B1,Bank_0:CTOF_DEL, 0.371,R2C3A.B1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 1.057,R6C3A.F1,R7C3C.A0,XOR8MEG_N_112:CTOF_DEL, 0.371,R7C3C.A0,R7C3C.F0,SLICE_97:ROUTE, 1.656,R7C3C.F0,R8C5C.CE,PHI2_N_114_enable_2">Data path</A> SLICE_93 to SLICE_94:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q0 <A href="#@comp:SLICE_93">SLICE_93</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
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ROUTE 1 1.086<A href="#@net:Bank_0:R2C2B.Q0:R2C3A.B1:1.086"> R2C2B.Q0 to R2C3A.B1 </A> <A href="#@net:Bank_0">Bank_0</A>
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CTOF_DEL --- 0.371 R2C3A.B1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
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ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
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CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
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ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
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CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
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ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
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CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
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ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
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CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
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ROUTE 3 1.057<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R7C3C.A0:1.057"> R6C3A.F1 to R7C3C.A0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
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CTOF_DEL --- 0.371 R7C3C.A0 to R7C3C.F0 <A href="#@comp:SLICE_97">SLICE_97</A>
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ROUTE 1 1.656<A href="#@net:PHI2_N_114_enable_2:R7C3C.F0:R8C5C.CE:1.656"> R7C3C.F0 to R8C5C.CE </A> <A href="#@net:PHI2_N_114_enable_2">PHI2_N_114_enable_2</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
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--------
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11.622 (24.0% logic, 76.0% route), 7 logic levels.
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Clock Skew Details:
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_93:
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Name Fanout Delay (ns) Site Resource
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ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.924"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
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--------
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3.924 (0.0% logic, 100.0% route), 0 logic levels.
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<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R8C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_94:
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Name Fanout Delay (ns) Site Resource
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ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R8C5C.CLK:3.924"> 39.PADDI to R8C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
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--------
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3.924 (0.0% logic, 100.0% route), 0 logic levels.
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<font color=#000000>
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Passed: The following path meets requirements by 163.173ns (weighted slack = 326.346ns)
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</font>
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q <A href="#@comp:SLICE_98">Bank_i6</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_94">XOR8MEG_376</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.562ns (24.1% logic, 75.9% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.562ns physical path delay SLICE_98 to SLICE_94 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.173ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2C.CLK,R2C2C.Q0,SLICE_98:ROUTE, 1.026,R2C2C.Q0,R2C3A.A1,Bank_6:CTOF_DEL, 0.371,R2C3A.A1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 1.057,R6C3A.F1,R7C3C.A0,XOR8MEG_N_112:CTOF_DEL, 0.371,R7C3C.A0,R7C3C.F0,SLICE_97:ROUTE, 1.656,R7C3C.F0,R8C5C.CE,PHI2_N_114_enable_2">Data path</A> SLICE_98 to SLICE_94:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 1.026<A href="#@net:Bank_6:R2C2C.Q0:R2C3A.A1:1.026"> R2C2C.Q0 to R2C3A.A1 </A> <A href="#@net:Bank_6">Bank_6</A>
|
|
CTOF_DEL --- 0.371 R2C3A.A1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 1.057<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R7C3C.A0:1.057"> R6C3A.F1 to R7C3C.A0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R7C3C.A0 to R7C3C.F0 <A href="#@comp:SLICE_97">SLICE_97</A>
|
|
ROUTE 1 1.656<A href="#@net:PHI2_N_114_enable_2:R7C3C.F0:R8C5C.CE:1.656"> R7C3C.F0 to R8C5C.CE </A> <A href="#@net:PHI2_N_114_enable_2">PHI2_N_114_enable_2</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.562 (24.1% logic, 75.9% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2C.CLK:3.924"> 39.PADDI to R2C2C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R8C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_94:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R8C5C.CLK:3.924"> 39.PADDI to R8C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 163.236ns (weighted slack = 326.472ns)
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_90">Bank_i5</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_23">Cmdn8MEGEN_377</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.499ns (24.2% logic, 75.8% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.499ns physical path delay SLICE_90 to SLICE_23 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.236ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C3A.CLK,R2C3A.Q1,SLICE_90:ROUTE, 0.819,R2C3A.Q1,R2C3A.C1,Bank_5:CTOF_DEL, 0.371,R2C3A.C1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 0.727,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.371,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 2.130,R6C3A.F0,R7C3A.CE,PHI2_N_114_enable_6">Data path</A> SLICE_90 to SLICE_23:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C3A.CLK to R2C3A.Q1 <A href="#@comp:SLICE_90">SLICE_90</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 0.819<A href="#@net:Bank_5:R2C3A.Q1:R2C3A.C1:0.819"> R2C3A.Q1 to R2C3A.C1 </A> <A href="#@net:Bank_5">Bank_5</A>
|
|
CTOF_DEL --- 0.371 R2C3A.C1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 0.727<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.727"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 2 2.130<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C3A.CE:2.130"> R6C3A.F0 to R7C3A.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.499 (24.2% logic, 75.8% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C3A.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C3A.CLK:3.924"> 39.PADDI to R2C3A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C3A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_23:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C3A.CLK:3.924"> 39.PADDI to R7C3A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 163.277ns (weighted slack = 326.554ns)
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_93">Bank_i0</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.458ns (24.3% logic, 75.7% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.458ns physical path delay SLICE_93 to SLICE_77 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.277ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q0,SLICE_93:ROUTE, 1.086,R2C2B.Q0,R2C3A.B1,Bank_0:CTOF_DEL, 0.371,R2C3A.B1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 1.379,R6C3A.F1,R4C5A.C1,XOR8MEG_N_112:CTOF_DEL, 0.371,R4C5A.C1,R4C5A.F1,SLICE_73:ROUTE, 1.170,R4C5A.F1,R7C5C.CE,PHI2_N_114_enable_7">Data path</A> SLICE_93 to SLICE_77:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q0 <A href="#@comp:SLICE_93">SLICE_93</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 1.086<A href="#@net:Bank_0:R2C2B.Q0:R2C3A.B1:1.086"> R2C2B.Q0 to R2C3A.B1 </A> <A href="#@net:Bank_0">Bank_0</A>
|
|
CTOF_DEL --- 0.371 R2C3A.B1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 1.379<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R4C5A.C1:1.379"> R6C3A.F1 to R4C5A.C1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
|
|
ROUTE 2 1.170<A href="#@net:PHI2_N_114_enable_7:R4C5A.F1:R7C5C.CE:1.170"> R4C5A.F1 to R7C5C.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.458 (24.3% logic, 75.7% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.924"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C5C.CLK:3.924"> 39.PADDI to R7C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 163.337ns (weighted slack = 326.674ns)
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_98">Bank_i6</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.398ns (24.4% logic, 75.6% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.398ns physical path delay SLICE_98 to SLICE_77 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.337ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2C.CLK,R2C2C.Q0,SLICE_98:ROUTE, 1.026,R2C2C.Q0,R2C3A.A1,Bank_6:CTOF_DEL, 0.371,R2C3A.A1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 1.379,R6C3A.F1,R4C5A.C1,XOR8MEG_N_112:CTOF_DEL, 0.371,R4C5A.C1,R4C5A.F1,SLICE_73:ROUTE, 1.170,R4C5A.F1,R7C5C.CE,PHI2_N_114_enable_7">Data path</A> SLICE_98 to SLICE_77:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 1.026<A href="#@net:Bank_6:R2C2C.Q0:R2C3A.A1:1.026"> R2C2C.Q0 to R2C3A.A1 </A> <A href="#@net:Bank_6">Bank_6</A>
|
|
CTOF_DEL --- 0.371 R2C3A.A1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 1.379<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R4C5A.C1:1.379"> R6C3A.F1 to R4C5A.C1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
|
|
ROUTE 2 1.170<A href="#@net:PHI2_N_114_enable_7:R4C5A.F1:R7C5C.CE:1.170"> R4C5A.F1 to R7C5C.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.398 (24.4% logic, 75.6% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2C.CLK:3.924"> 39.PADDI to R2C2C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C5C.CLK:3.924"> 39.PADDI to R7C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 163.380ns (weighted slack = 326.760ns)
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_90">Bank_i5</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_94">XOR8MEG_376</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.355ns (24.5% logic, 75.5% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.355ns physical path delay SLICE_90 to SLICE_94 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C3A.CLK,R2C3A.Q1,SLICE_90:ROUTE, 0.819,R2C3A.Q1,R2C3A.C1,Bank_5:CTOF_DEL, 0.371,R2C3A.C1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 1.057,R6C3A.F1,R7C3C.A0,XOR8MEG_N_112:CTOF_DEL, 0.371,R7C3C.A0,R7C3C.F0,SLICE_97:ROUTE, 1.656,R7C3C.F0,R8C5C.CE,PHI2_N_114_enable_2">Data path</A> SLICE_90 to SLICE_94:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C3A.CLK to R2C3A.Q1 <A href="#@comp:SLICE_90">SLICE_90</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 0.819<A href="#@net:Bank_5:R2C3A.Q1:R2C3A.C1:0.819"> R2C3A.Q1 to R2C3A.C1 </A> <A href="#@net:Bank_5">Bank_5</A>
|
|
CTOF_DEL --- 0.371 R2C3A.C1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 1.057<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R7C3C.A0:1.057"> R6C3A.F1 to R7C3C.A0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R7C3C.A0 to R7C3C.F0 <A href="#@comp:SLICE_97">SLICE_97</A>
|
|
ROUTE 1 1.656<A href="#@net:PHI2_N_114_enable_2:R7C3C.F0:R8C5C.CE:1.656"> R7C3C.F0 to R8C5C.CE </A> <A href="#@net:PHI2_N_114_enable_2">PHI2_N_114_enable_2</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.355 (24.5% logic, 75.5% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C3A.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_90:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C3A.CLK:3.924"> 39.PADDI to R2C3A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R8C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_94:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R8C5C.CLK:3.924"> 39.PADDI to R8C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 163.430ns (weighted slack = 326.860ns)
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_93">Bank_i0</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_19">CmdSubmitted_378</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.305ns (24.6% logic, 75.4% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.305ns physical path delay SLICE_93 to SLICE_19 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.430ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q0,SLICE_93:ROUTE, 1.086,R2C2B.Q0,R2C3A.B1,Bank_0:CTOF_DEL, 0.371,R2C3A.B1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 0.727,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.371,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 1.669,R6C3A.F0,R7C4D.CE,PHI2_N_114_enable_6">Data path</A> SLICE_93 to SLICE_19:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q0 <A href="#@comp:SLICE_93">SLICE_93</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 1.086<A href="#@net:Bank_0:R2C2B.Q0:R2C3A.B1:1.086"> R2C2B.Q0 to R2C3A.B1 </A> <A href="#@net:Bank_0">Bank_0</A>
|
|
CTOF_DEL --- 0.371 R2C3A.B1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 0.727<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.727"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 2 1.669<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C4D.CE:1.669"> R6C3A.F0 to R7C4D.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.305 (24.6% logic, 75.4% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_93:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.924"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C4D.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_19:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C4D.CLK:3.924"> 39.PADDI to R7C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns)
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_98">Bank_i6</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_19">CmdSubmitted_378</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
|
|
|
|
Delay: 11.245ns (24.8% logic, 75.2% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.245ns physical path delay SLICE_98 to SLICE_19 meets
|
|
175.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.265ns CE_SET requirement (totaling 174.735ns) by 163.490ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2C.CLK,R2C2C.Q0,SLICE_98:ROUTE, 1.026,R2C2C.Q0,R2C3A.A1,Bank_6:CTOF_DEL, 0.371,R2C3A.A1,R2C3A.F1,SLICE_90:ROUTE, 1.643,R2C3A.F1,R5C4D.B1,n2160:CTOF_DEL, 0.371,R5C4D.B1,R5C4D.F1,SLICE_84:ROUTE, 0.819,R5C4D.F1,R5C4B.C1,n26:CTOF_DEL, 0.371,R5C4B.C1,R5C4B.F1,SLICE_74:ROUTE, 1.601,R5C4B.F1,R6C3C.B1,n1279:CTOF_DEL, 0.371,R6C3C.B1,R6C3C.F1,SLICE_9:ROUTE, 0.974,R6C3C.F1,R6C3A.A1,n2288:CTOF_DEL, 0.371,R6C3A.A1,R6C3A.F1,SLICE_76:ROUTE, 0.727,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.371,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 1.669,R6C3A.F0,R7C4D.CE,PHI2_N_114_enable_6">Data path</A> SLICE_98 to SLICE_19:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
ROUTE 1 1.026<A href="#@net:Bank_6:R2C2C.Q0:R2C3A.A1:1.026"> R2C2C.Q0 to R2C3A.A1 </A> <A href="#@net:Bank_6">Bank_6</A>
|
|
CTOF_DEL --- 0.371 R2C3A.A1 to R2C3A.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 1.643<A href="#@net:n2160:R2C3A.F1:R5C4D.B1:1.643"> R2C3A.F1 to R5C4D.B1 </A> <A href="#@net:n2160">n2160</A>
|
|
CTOF_DEL --- 0.371 R5C4D.B1 to R5C4D.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
|
|
ROUTE 1 0.819<A href="#@net:n26:R5C4D.F1:R5C4B.C1:0.819"> R5C4D.F1 to R5C4B.C1 </A> <A href="#@net:n26">n26</A>
|
|
CTOF_DEL --- 0.371 R5C4B.C1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
ROUTE 5 1.601<A href="#@net:n1279:R5C4B.F1:R6C3C.B1:1.601"> R5C4B.F1 to R6C3C.B1 </A> <A href="#@net:n1279">n1279</A>
|
|
CTOF_DEL --- 0.371 R6C3C.B1 to R6C3C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
|
|
ROUTE 2 0.974<A href="#@net:n2288:R6C3C.F1:R6C3A.A1:0.974"> R6C3C.F1 to R6C3A.A1 </A> <A href="#@net:n2288">n2288</A>
|
|
CTOF_DEL --- 0.371 R6C3A.A1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 3 0.727<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.727"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
|
|
CTOF_DEL --- 0.371 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
|
|
ROUTE 2 1.669<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C4D.CE:1.669"> R6C3A.F0 to R7C4D.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
|
|
--------
|
|
11.245 (24.8% logic, 75.2% route), 7 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R2C2C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R2C2C.CLK:3.924"> 39.PADDI to R2C2C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.924,39.PADDI,R7C4D.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_19:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 14 3.924<A href="#@net:PHI2_c:39.PADDI:R7C4D.CLK:3.924"> 39.PADDI to R7C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
|
|
--------
|
|
3.924 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Report: 24.062ns is the minimum period for this preference.
|
|
|
|
|
|
</A><A name="PERIOD NET 'nCCAS_c' 350.000000 ns"></A>================================================================================
|
|
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 348.000ns
|
|
The internal maximum frequency of the following component is 500.000 MHz
|
|
|
|
Logical Details: Cell type Pin name Component name
|
|
|
|
Destination: FSLICE CLK <A href="#@comp:SLICE_73">SLICE_73</A>
|
|
|
|
Delay: 2.000ns -- based on Minimum Pulse Width
|
|
|
|
Report: 2.000ns is the minimum period for this preference.
|
|
|
|
|
|
</A><A name="PERIOD NET 'nCRAS_c' 350.000000 ns"></A>================================================================================
|
|
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 348.000ns
|
|
The internal maximum frequency of the following component is 500.000 MHz
|
|
|
|
Logical Details: Cell type Pin name Component name
|
|
|
|
Destination: FSLICE CLK <A href="#@comp:SLICE_74">SLICE_74</A>
|
|
|
|
Delay: 2.000ns -- based on Minimum Pulse Width
|
|
|
|
Report: 2.000ns is the minimum period for this preference.
|
|
|
|
|
|
</A><A name="PERIOD NET 'RCLK_c' 15.000000 ns"></A>================================================================================
|
|
Preference: PERIOD NET "RCLK_c" 15.000000 ns ;
|
|
10 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.275ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i14</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 8.481ns (28.5% logic, 71.5% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.481ns physical path delay SLICE_7 to SLICE_85 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.275ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4D.CLK,R8C4D.Q0,SLICE_7:ROUTE, 1.466,R8C4D.Q0,R8C5D.B1,FS_14:CTOF_DEL, 0.371,R8C5D.B1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 1.042,R7C5C.F1,R5C5A.A1,n2111:CTOF_DEL, 0.371,R5C5A.A1,R5C5A.F1,SLICE_100:ROUTE, 0.703,R5C5A.F1,R7C5D.CE,RCLK_c_enable_25">Data path</A> SLICE_7 to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 1.466<A href="#@net:FS_14:R8C4D.Q0:R8C5D.B1:1.466"> R8C4D.Q0 to R8C5D.B1 </A> <A href="#@net:FS_14">FS_14</A>
|
|
CTOF_DEL --- 0.371 R8C5D.B1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 1.042<A href="#@net:n2111:R7C5C.F1:R5C5A.A1:1.042"> R7C5C.F1 to R5C5A.A1 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R5C5A.A1 to R5C5A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
|
|
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R5C5A.F1:R7C5D.CE:0.703"> R5C5A.F1 to R7C5D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
8.481 (28.5% logic, 71.5% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4D.CLK:1.353"> 86.PADDI to R8C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C5D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C5D.CLK:1.353"> 86.PADDI to R7C5D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.434ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i14</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 8.322ns (29.0% logic, 71.0% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.322ns physical path delay SLICE_7 to SLICE_56 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.434ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4D.CLK,R8C4D.Q0,SLICE_7:ROUTE, 1.466,R8C4D.Q0,R8C5D.B1,FS_14:CTOF_DEL, 0.371,R8C5D.B1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 0.513,R7C5C.F1,R7C5C.C0,n2111:CTOF_DEL, 0.371,R7C5C.C0,R7C5C.F0,SLICE_77:ROUTE, 1.073,R7C5C.F0,R7C4B.CE,RCLK_c_enable_7">Data path</A> SLICE_7 to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 1.466<A href="#@net:FS_14:R8C4D.Q0:R8C5D.B1:1.466"> R8C4D.Q0 to R8C5D.B1 </A> <A href="#@net:FS_14">FS_14</A>
|
|
CTOF_DEL --- 0.371 R8C5D.B1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 0.513<A href="#@net:n2111:R7C5C.F1:R7C5C.C0:0.513"> R7C5C.F1 to R7C5C.C0 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R7C5C.F0:R7C4B.CE:1.073"> R7C5C.F0 to R7C4B.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
8.322 (29.0% logic, 71.0% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4D.CLK:1.353"> 86.PADDI to R8C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C4B.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C4B.CLK:1.353"> 86.PADDI to R7C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.474ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i15</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 8.282ns (29.2% logic, 70.8% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.282ns physical path delay SLICE_7 to SLICE_85 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.474ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4D.CLK,R8C4D.Q1,SLICE_7:ROUTE, 1.267,R8C4D.Q1,R8C5D.C1,FS_15:CTOF_DEL, 0.371,R8C5D.C1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 1.042,R7C5C.F1,R5C5A.A1,n2111:CTOF_DEL, 0.371,R5C5A.A1,R5C5A.F1,SLICE_100:ROUTE, 0.703,R5C5A.F1,R7C5D.CE,RCLK_c_enable_25">Data path</A> SLICE_7 to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 1.267<A href="#@net:FS_15:R8C4D.Q1:R8C5D.C1:1.267"> R8C4D.Q1 to R8C5D.C1 </A> <A href="#@net:FS_15">FS_15</A>
|
|
CTOF_DEL --- 0.371 R8C5D.C1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 1.042<A href="#@net:n2111:R7C5C.F1:R5C5A.A1:1.042"> R7C5C.F1 to R5C5A.A1 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R5C5A.A1 to R5C5A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
|
|
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R5C5A.F1:R7C5D.CE:0.703"> R5C5A.F1 to R7C5D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
8.282 (29.2% logic, 70.8% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4D.CLK:1.353"> 86.PADDI to R8C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C5D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C5D.CLK:1.353"> 86.PADDI to R7C5D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.633ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i15</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 8.123ns (29.7% logic, 70.3% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.123ns physical path delay SLICE_7 to SLICE_56 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.633ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4D.CLK,R8C4D.Q1,SLICE_7:ROUTE, 1.267,R8C4D.Q1,R8C5D.C1,FS_15:CTOF_DEL, 0.371,R8C5D.C1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 0.513,R7C5C.F1,R7C5C.C0,n2111:CTOF_DEL, 0.371,R7C5C.C0,R7C5C.F0,SLICE_77:ROUTE, 1.073,R7C5C.F0,R7C4B.CE,RCLK_c_enable_7">Data path</A> SLICE_7 to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 1.267<A href="#@net:FS_15:R8C4D.Q1:R8C5D.C1:1.267"> R8C4D.Q1 to R8C5D.C1 </A> <A href="#@net:FS_15">FS_15</A>
|
|
CTOF_DEL --- 0.371 R8C5D.C1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 0.513<A href="#@net:n2111:R7C5C.F1:R7C5C.C0:0.513"> R7C5C.F1 to R7C5C.C0 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R7C5C.F0:R7C4B.CE:1.073"> R7C5C.F0 to R7C4B.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
8.123 (29.7% logic, 70.3% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4D.CLK:1.353"> 86.PADDI to R8C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C4B.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C4B.CLK:1.353"> 86.PADDI to R7C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.693ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_8">FS_571__i13</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 8.063ns (30.0% logic, 70.0% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.063ns physical path delay SLICE_8 to SLICE_85 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.693ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4C.CLK,R8C4C.Q1,SLICE_8:ROUTE, 1.048,R8C4C.Q1,R8C5D.A1,FS_13:CTOF_DEL, 0.371,R8C5D.A1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 1.042,R7C5C.F1,R5C5A.A1,n2111:CTOF_DEL, 0.371,R5C5A.A1,R5C5A.F1,SLICE_100:ROUTE, 0.703,R5C5A.F1,R7C5D.CE,RCLK_c_enable_25">Data path</A> SLICE_8 to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 <A href="#@comp:SLICE_8">SLICE_8</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 1.048<A href="#@net:FS_13:R8C4C.Q1:R8C5D.A1:1.048"> R8C4C.Q1 to R8C5D.A1 </A> <A href="#@net:FS_13">FS_13</A>
|
|
CTOF_DEL --- 0.371 R8C5D.A1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 1.042<A href="#@net:n2111:R7C5C.F1:R5C5A.A1:1.042"> R7C5C.F1 to R5C5A.A1 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R5C5A.A1 to R5C5A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
|
|
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R5C5A.F1:R7C5D.CE:0.703"> R5C5A.F1 to R7C5D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
8.063 (30.0% logic, 70.0% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_8:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4C.CLK:1.353"> 86.PADDI to R8C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C5D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C5D.CLK:1.353"> 86.PADDI to R7C5D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.852ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_8">FS_571__i13</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 7.904ns (30.6% logic, 69.4% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.904ns physical path delay SLICE_8 to SLICE_56 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.852ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4C.CLK,R8C4C.Q1,SLICE_8:ROUTE, 1.048,R8C4C.Q1,R8C5D.A1,FS_13:CTOF_DEL, 0.371,R8C5D.A1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 0.513,R7C5C.F1,R7C5C.C0,n2111:CTOF_DEL, 0.371,R7C5C.C0,R7C5C.F0,SLICE_77:ROUTE, 1.073,R7C5C.F0,R7C4B.CE,RCLK_c_enable_7">Data path</A> SLICE_8 to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 <A href="#@comp:SLICE_8">SLICE_8</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 1.048<A href="#@net:FS_13:R8C4C.Q1:R8C5D.A1:1.048"> R8C4C.Q1 to R8C5D.A1 </A> <A href="#@net:FS_13">FS_13</A>
|
|
CTOF_DEL --- 0.371 R8C5D.A1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 0.513<A href="#@net:n2111:R7C5C.F1:R7C5C.C0:0.513"> R7C5C.F1 to R7C5C.C0 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R7C5C.F0:R7C4B.CE:1.073"> R7C5C.F0 to R7C4B.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
7.904 (30.6% logic, 69.4% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_8:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4C.CLK:1.353"> 86.PADDI to R8C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C4B.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C4B.CLK:1.353"> 86.PADDI to R7C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.891ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_4">FS_571__i2</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 7.865ns (26.0% logic, 74.0% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.865ns physical path delay SLICE_4 to SLICE_85 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.891ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C3B.CLK,R8C3B.Q0,SLICE_4:ROUTE, 1.563,R8C3B.Q0,R7C4C.B1,FS_2:CTOF_DEL, 0.371,R7C4C.B1,R7C4C.F1,SLICE_68:ROUTE, 1.487,R7C4C.F1,R9C5A.A0,n2164:CTOF_DEL, 0.371,R9C5A.A0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 1.042,R7C5C.F1,R5C5A.A1,n2111:CTOF_DEL, 0.371,R5C5A.A1,R5C5A.F1,SLICE_100:ROUTE, 0.703,R5C5A.F1,R7C5D.CE,RCLK_c_enable_25">Data path</A> SLICE_4 to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C3B.CLK to R8C3B.Q0 <A href="#@comp:SLICE_4">SLICE_4</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 2 1.563<A href="#@net:FS_2:R8C3B.Q0:R7C4C.B1:1.563"> R8C3B.Q0 to R7C4C.B1 </A> <A href="#@net:FS_2">FS_2</A>
|
|
CTOF_DEL --- 0.371 R7C4C.B1 to R7C4C.F1 <A href="#@comp:SLICE_68">SLICE_68</A>
|
|
ROUTE 1 1.487<A href="#@net:n2164:R7C4C.F1:R9C5A.A0:1.487"> R7C4C.F1 to R9C5A.A0 </A> <A href="#@net:n2164">n2164</A>
|
|
CTOF_DEL --- 0.371 R9C5A.A0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 1.042<A href="#@net:n2111:R7C5C.F1:R5C5A.A1:1.042"> R7C5C.F1 to R5C5A.A1 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R5C5A.A1 to R5C5A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
|
|
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R5C5A.F1:R7C5D.CE:0.703"> R5C5A.F1 to R7C5D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
7.865 (26.0% logic, 74.0% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C3B.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C3B.CLK:1.353"> 86.PADDI to R8C3B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C5D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C5D.CLK:1.353"> 86.PADDI to R7C5D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 6.951ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_5">FS_571__i1</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 7.805ns (26.2% logic, 73.8% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.805ns physical path delay SLICE_5 to SLICE_85 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 6.951ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C3A.CLK,R8C3A.Q1,SLICE_5:ROUTE, 1.503,R8C3A.Q1,R7C4C.A1,FS_1:CTOF_DEL, 0.371,R7C4C.A1,R7C4C.F1,SLICE_68:ROUTE, 1.487,R7C4C.F1,R9C5A.A0,n2164:CTOF_DEL, 0.371,R9C5A.A0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 1.042,R7C5C.F1,R5C5A.A1,n2111:CTOF_DEL, 0.371,R5C5A.A1,R5C5A.F1,SLICE_100:ROUTE, 0.703,R5C5A.F1,R7C5D.CE,RCLK_c_enable_25">Data path</A> SLICE_5 to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C3A.CLK to R8C3A.Q1 <A href="#@comp:SLICE_5">SLICE_5</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 2 1.503<A href="#@net:FS_1:R8C3A.Q1:R7C4C.A1:1.503"> R8C3A.Q1 to R7C4C.A1 </A> <A href="#@net:FS_1">FS_1</A>
|
|
CTOF_DEL --- 0.371 R7C4C.A1 to R7C4C.F1 <A href="#@comp:SLICE_68">SLICE_68</A>
|
|
ROUTE 1 1.487<A href="#@net:n2164:R7C4C.F1:R9C5A.A0:1.487"> R7C4C.F1 to R9C5A.A0 </A> <A href="#@net:n2164">n2164</A>
|
|
CTOF_DEL --- 0.371 R9C5A.A0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 1.042<A href="#@net:n2111:R7C5C.F1:R5C5A.A1:1.042"> R7C5C.F1 to R5C5A.A1 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R5C5A.A1 to R5C5A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
|
|
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R5C5A.F1:R7C5D.CE:0.703"> R5C5A.F1 to R7C5D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
7.805 (26.2% logic, 73.8% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C3A.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_5:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C3A.CLK:1.353"> 86.PADDI to R8C3A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C5D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C5D.CLK:1.353"> 86.PADDI to R7C5D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 7.017ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_8">FS_571__i12</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 7.739ns (31.2% logic, 68.8% route), 6 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.739ns physical path delay SLICE_8 to SLICE_85 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 7.017ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C4C.CLK,R8C4C.Q0,SLICE_8:ROUTE, 0.724,R8C4C.Q0,R8C5D.D1,FS_12:CTOF_DEL, 0.371,R8C5D.D1,R8C5D.F1,SLICE_78:ROUTE, 1.117,R8C5D.F1,R9C5A.B1,n10:CTOF_DEL, 0.371,R9C5A.B1,R9C5A.F1,SLICE_75:ROUTE, 0.712,R9C5A.F1,R9C5A.B0,n2298:CTOF_DEL, 0.371,R9C5A.B0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 1.042,R7C5C.F1,R5C5A.A1,n2111:CTOF_DEL, 0.371,R5C5A.A1,R5C5A.F1,SLICE_100:ROUTE, 0.703,R5C5A.F1,R7C5D.CE,RCLK_c_enable_25">Data path</A> SLICE_8 to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 <A href="#@comp:SLICE_8">SLICE_8</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 3 0.724<A href="#@net:FS_12:R8C4C.Q0:R8C5D.D1:0.724"> R8C4C.Q0 to R8C5D.D1 </A> <A href="#@net:FS_12">FS_12</A>
|
|
CTOF_DEL --- 0.371 R8C5D.D1 to R8C5D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
|
|
ROUTE 3 1.117<A href="#@net:n10:R8C5D.F1:R9C5A.B1:1.117"> R8C5D.F1 to R9C5A.B1 </A> <A href="#@net:n10">n10</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B1 to R9C5A.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 4 0.712<A href="#@net:n2298:R9C5A.F1:R9C5A.B0:0.712"> R9C5A.F1 to R9C5A.B0 </A> <A href="#@net:n2298">n2298</A>
|
|
CTOF_DEL --- 0.371 R9C5A.B0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 1.042<A href="#@net:n2111:R7C5C.F1:R5C5A.A1:1.042"> R7C5C.F1 to R5C5A.A1 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R5C5A.A1 to R5C5A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
|
|
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R5C5A.F1:R7C5D.CE:0.703"> R5C5A.F1 to R7C5D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
7.739 (31.2% logic, 68.8% route), 6 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C4C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_8:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C4C.CLK:1.353"> 86.PADDI to R8C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C5D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C5D.CLK:1.353"> 86.PADDI to R7C5D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
<font color=#000000>
|
|
|
|
Passed: The following path meets requirements by 7.050ns
|
|
</font>
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_4">FS_571__i2</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
|
|
Delay: 7.706ns (26.5% logic, 73.5% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
7.706ns physical path delay SLICE_4 to SLICE_56 meets
|
|
15.000ns delay constraint less
|
|
0.000ns skew and
|
|
0.244ns CE_SET requirement (totaling 14.756ns) by 7.050ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.560,R8C3B.CLK,R8C3B.Q0,SLICE_4:ROUTE, 1.563,R8C3B.Q0,R7C4C.B1,FS_2:CTOF_DEL, 0.371,R7C4C.B1,R7C4C.F1,SLICE_68:ROUTE, 1.487,R7C4C.F1,R9C5A.A0,n2164:CTOF_DEL, 0.371,R9C5A.A0,R9C5A.F0,SLICE_75:ROUTE, 1.026,R9C5A.F0,R7C5C.A1,n11:CTOF_DEL, 0.371,R7C5C.A1,R7C5C.F1,SLICE_77:ROUTE, 0.513,R7C5C.F1,R7C5C.C0,n2111:CTOF_DEL, 0.371,R7C5C.C0,R7C5C.F0,SLICE_77:ROUTE, 1.073,R7C5C.F0,R7C4B.CE,RCLK_c_enable_7">Data path</A> SLICE_4 to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R8C3B.CLK to R8C3B.Q0 <A href="#@comp:SLICE_4">SLICE_4</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 2 1.563<A href="#@net:FS_2:R8C3B.Q0:R7C4C.B1:1.563"> R8C3B.Q0 to R7C4C.B1 </A> <A href="#@net:FS_2">FS_2</A>
|
|
CTOF_DEL --- 0.371 R7C4C.B1 to R7C4C.F1 <A href="#@comp:SLICE_68">SLICE_68</A>
|
|
ROUTE 1 1.487<A href="#@net:n2164:R7C4C.F1:R9C5A.A0:1.487"> R7C4C.F1 to R9C5A.A0 </A> <A href="#@net:n2164">n2164</A>
|
|
CTOF_DEL --- 0.371 R9C5A.A0 to R9C5A.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
|
|
ROUTE 1 1.026<A href="#@net:n11:R9C5A.F0:R7C5C.A1:1.026"> R9C5A.F0 to R7C5C.A1 </A> <A href="#@net:n11">n11</A>
|
|
CTOF_DEL --- 0.371 R7C5C.A1 to R7C5C.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 2 0.513<A href="#@net:n2111:R7C5C.F1:R7C5C.C0:0.513"> R7C5C.F1 to R7C5C.C0 </A> <A href="#@net:n2111">n2111</A>
|
|
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
|
|
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R7C5C.F0:R7C4B.CE:1.073"> R7C5C.F0 to R7C4B.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
--------
|
|
7.706 (26.5% logic, 73.5% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R8C3B.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R8C3B.CLK:1.353"> 86.PADDI to R8C3B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 1.353,86.PADDI,R7C4B.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C4B.CLK:1.353"> 86.PADDI to R7C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.353 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Report: 8.725ns is the minimum period for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'Dout[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RBA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RBA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RBA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RBA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[11]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[11]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.904ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_55">RA10_368</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[10]">RA[10]</A>
|
|
|
|
Data Path Delay: 6.180ns (67.9% logic, 32.1% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_55 and
|
|
6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
|
|
12.500ns offset RCLK to RA[10] by 3.904ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R2C4B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R2C4B.CLK:1.353"> 86.PADDI to R2C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C4B.CLK,R2C4B.Q0,SLICE_55:ROUTE, 1.984,R2C4B.Q0,87.PADDO,n974:DOPAD_DEL, 3.636,87.PADDO,87.PAD,RA[10]">Data path</A> SLICE_55 to RA[10]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C4B.CLK to R2C4B.Q0 <A href="#@comp:SLICE_55">SLICE_55</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 1.984<A href="#@net:n974:R2C4B.Q0:87.PADDO:1.984"> R2C4B.Q0 to 87.PADDO </A> <A href="#@net:n974">n974</A>
|
|
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD <A href="#@comp:RA[10]">RA[10]</A>
|
|
--------
|
|
6.180 (67.9% logic, 32.1% route), 2 logic levels.
|
|
|
|
Report: 8.596ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 7.280ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_55">RA10_368</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[10]">RA[10]</A>
|
|
|
|
Data Path Delay: 5.683ns (73.0% logic, 27.0% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_55 and
|
|
5.683ns delay SLICE_55 to RA[10] (totaling 7.280ns) meets
|
|
0.000ns hold offset RCLK to RA[10] by 7.280ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R2C4B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R2C4B.CLK:0.730"> 86.PADDI to R2C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C4B.CLK,R2C4B.Q0,SLICE_55:ROUTE, 1.532,R2C4B.Q0,87.PADDO,n974:DOPAD_DEL, 3.636,87.PADDO,87.PAD,RA[10]">Data path</A> SLICE_55 to RA[10]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R2C4B.CLK to R2C4B.Q0 <A href="#@comp:SLICE_55">SLICE_55</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 1.532<A href="#@net:n974:R2C4B.Q0:87.PADDO:1.532"> R2C4B.Q0 to 87.PADDO </A> <A href="#@net:n974">n974</A>
|
|
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD <A href="#@comp:RA[10]">RA[10]</A>
|
|
--------
|
|
5.683 (73.0% logic, 27.0% route), 2 logic levels.
|
|
|
|
Report: 7.280ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 1.684ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[9]">RA[9]</A>
|
|
|
|
Data Path Delay: 8.400ns (54.4% logic, 45.6% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
8.400ns delay SLICE_64 to RA[9] (totaling 10.816ns) meets
|
|
12.500ns offset RCLK to RA[9] by 1.684ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.781,R7C2B.Q0,R3C5A.D1,nRowColSel:CTOF_DEL, 0.371,R3C5A.D1,R3C5A.F1,SLICE_87:ROUTE, 2.052,R3C5A.F1,85.PADDO,RA_c_9:DOPAD_DEL, 3.636,85.PADDO,85.PAD,RA[9]">Data path</A> SLICE_64 to RA[9]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.781<A href="#@net:nRowColSel:R7C2B.Q0:R3C5A.D1:1.781"> R7C2B.Q0 to R3C5A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R3C5A.D1 to R3C5A.F1 <A href="#@comp:SLICE_87">SLICE_87</A>
|
|
ROUTE 1 2.052<A href="#@net:RA_c_9:R3C5A.F1:85.PADDO:2.052"> R3C5A.F1 to 85.PADDO </A> <A href="#@net:RA_c_9">RA_c_9</A>
|
|
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD <A href="#@comp:RA[9]">RA[9]</A>
|
|
--------
|
|
8.400 (54.4% logic, 45.6% route), 3 logic levels.
|
|
|
|
Report: 10.816ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 9.193ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[9]">RA[9]</A>
|
|
|
|
Data Path Delay: 7.596ns (58.6% logic, 41.4% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
7.596ns delay SLICE_64 to RA[9] (totaling 9.193ns) meets
|
|
0.000ns hold offset RCLK to RA[9] by 9.193ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.534,R7C2B.Q0,R3C5A.D1,nRowColSel:CTOF_DEL, 0.301,R3C5A.D1,R3C5A.F1,SLICE_87:ROUTE, 1.610,R3C5A.F1,85.PADDO,RA_c_9:DOPAD_DEL, 3.636,85.PADDO,85.PAD,RA[9]">Data path</A> SLICE_64 to RA[9]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.534<A href="#@net:nRowColSel:R7C2B.Q0:R3C5A.D1:1.534"> R7C2B.Q0 to R3C5A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R3C5A.D1 to R3C5A.F1 <A href="#@comp:SLICE_87">SLICE_87</A>
|
|
ROUTE 1 1.610<A href="#@net:RA_c_9:R3C5A.F1:85.PADDO:1.610"> R3C5A.F1 to 85.PADDO </A> <A href="#@net:RA_c_9">RA_c_9</A>
|
|
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD <A href="#@comp:RA[9]">RA[9]</A>
|
|
--------
|
|
7.596 (58.6% logic, 41.4% route), 3 logic levels.
|
|
|
|
Report: 9.193ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.988ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[8]">RA[8]</A>
|
|
|
|
Data Path Delay: 7.096ns (64.4% logic, 35.6% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.096ns delay SLICE_64 to RA[8] (totaling 9.512ns) meets
|
|
12.500ns offset RCLK to RA[8] by 2.988ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.712,R7C2B.Q0,R2C2C.D0,nRowColSel:CTOF_DEL, 0.371,R2C2C.D0,R2C2C.F0,SLICE_98:ROUTE, 0.817,R2C2C.F0,96.PADDO,RA_c_8:DOPAD_DEL, 3.636,96.PADDO,96.PAD,RA[8]">Data path</A> SLICE_64 to RA[8]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.712<A href="#@net:nRowColSel:R7C2B.Q0:R2C2C.D0:1.712"> R7C2B.Q0 to R2C2C.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C2C.D0 to R2C2C.F0 <A href="#@comp:SLICE_98">SLICE_98</A>
|
|
ROUTE 1 0.817<A href="#@net:RA_c_8:R2C2C.F0:96.PADDO:0.817"> R2C2C.F0 to 96.PADDO </A> <A href="#@net:RA_c_8">RA_c_8</A>
|
|
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD <A href="#@comp:RA[8]">RA[8]</A>
|
|
--------
|
|
7.096 (64.4% logic, 35.6% route), 3 logic levels.
|
|
|
|
Report: 9.512ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.119ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[8]">RA[8]</A>
|
|
|
|
Data Path Delay: 6.522ns (68.3% logic, 31.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.522ns delay SLICE_64 to RA[8] (totaling 8.119ns) meets
|
|
0.000ns hold offset RCLK to RA[8] by 8.119ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.424,R7C2B.Q0,R2C2C.D0,nRowColSel:CTOF_DEL, 0.301,R2C2C.D0,R2C2C.F0,SLICE_98:ROUTE, 0.646,R2C2C.F0,96.PADDO,RA_c_8:DOPAD_DEL, 3.636,96.PADDO,96.PAD,RA[8]">Data path</A> SLICE_64 to RA[8]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.424<A href="#@net:nRowColSel:R7C2B.Q0:R2C2C.D0:1.424"> R7C2B.Q0 to R2C2C.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C2C.D0 to R2C2C.F0 <A href="#@comp:SLICE_98">SLICE_98</A>
|
|
ROUTE 1 0.646<A href="#@net:RA_c_8:R2C2C.F0:96.PADDO:0.646"> R2C2C.F0 to 96.PADDO </A> <A href="#@net:RA_c_8">RA_c_8</A>
|
|
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD <A href="#@comp:RA[8]">RA[8]</A>
|
|
--------
|
|
6.522 (68.3% logic, 31.7% route), 3 logic levels.
|
|
|
|
Report: 8.119ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.977ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[7]">RA[7]</A>
|
|
|
|
Data Path Delay: 7.107ns (64.3% logic, 35.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.107ns delay SLICE_64 to RA[7] (totaling 9.523ns) meets
|
|
12.500ns offset RCLK to RA[7] by 2.977ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.880,R7C2B.Q0,R7C2B.C1,nRowColSel:CTOF_DEL, 0.371,R7C2B.C1,R7C2B.F1,SLICE_64:ROUTE, 1.660,R7C2B.F1,100.PADDO,RA_c_7:DOPAD_DEL, 3.636,100.PADDO,100.PAD,RA[7]">Data path</A> SLICE_64 to RA[7]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 0.880<A href="#@net:nRowColSel:R7C2B.Q0:R7C2B.C1:0.880"> R7C2B.Q0 to R7C2B.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R7C2B.C1 to R7C2B.F1 <A href="#@comp:SLICE_64">SLICE_64</A>
|
|
ROUTE 1 1.660<A href="#@net:RA_c_7:R7C2B.F1:100.PADDO:1.660"> R7C2B.F1 to 100.PADDO </A> <A href="#@net:RA_c_7">RA_c_7</A>
|
|
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD <A href="#@comp:RA[7]">RA[7]</A>
|
|
--------
|
|
7.107 (64.3% logic, 35.7% route), 3 logic levels.
|
|
|
|
Report: 9.523ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.063ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[7]">RA[7]</A>
|
|
|
|
Data Path Delay: 6.466ns (68.9% logic, 31.1% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.466ns delay SLICE_64 to RA[7] (totaling 8.063ns) meets
|
|
0.000ns hold offset RCLK to RA[7] by 8.063ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.726,R7C2B.Q0,R7C2B.C1,nRowColSel:CTOF_DEL, 0.301,R7C2B.C1,R7C2B.F1,SLICE_64:ROUTE, 1.288,R7C2B.F1,100.PADDO,RA_c_7:DOPAD_DEL, 3.636,100.PADDO,100.PAD,RA[7]">Data path</A> SLICE_64 to RA[7]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 0.726<A href="#@net:nRowColSel:R7C2B.Q0:R7C2B.C1:0.726"> R7C2B.Q0 to R7C2B.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R7C2B.C1 to R7C2B.F1 <A href="#@comp:SLICE_64">SLICE_64</A>
|
|
ROUTE 1 1.288<A href="#@net:RA_c_7:R7C2B.F1:100.PADDO:1.288"> R7C2B.F1 to 100.PADDO </A> <A href="#@net:RA_c_7">RA_c_7</A>
|
|
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD <A href="#@comp:RA[7]">RA[7]</A>
|
|
--------
|
|
6.466 (68.9% logic, 31.1% route), 3 logic levels.
|
|
|
|
Report: 8.063ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 1.822ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[6]">RA[6]</A>
|
|
|
|
Data Path Delay: 8.262ns (55.3% logic, 44.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
8.262ns delay SLICE_64 to RA[6] (totaling 10.678ns) meets
|
|
12.500ns offset RCLK to RA[6] by 1.822ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.712,R7C2B.Q0,R2C2C.D1,nRowColSel:CTOF_DEL, 0.371,R2C2C.D1,R2C2C.F1,SLICE_98:ROUTE, 1.983,R2C2C.F1,91.PADDO,RA_c_6:DOPAD_DEL, 3.636,91.PADDO,91.PAD,RA[6]">Data path</A> SLICE_64 to RA[6]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.712<A href="#@net:nRowColSel:R7C2B.Q0:R2C2C.D1:1.712"> R7C2B.Q0 to R2C2C.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C2C.D1 to R2C2C.F1 <A href="#@comp:SLICE_98">SLICE_98</A>
|
|
ROUTE 1 1.983<A href="#@net:RA_c_6:R2C2C.F1:91.PADDO:1.983"> R2C2C.F1 to 91.PADDO </A> <A href="#@net:RA_c_6">RA_c_6</A>
|
|
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD <A href="#@comp:RA[6]">RA[6]</A>
|
|
--------
|
|
8.262 (55.3% logic, 44.7% route), 3 logic levels.
|
|
|
|
Report: 10.678ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 9.044ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[6]">RA[6]</A>
|
|
|
|
Data Path Delay: 7.447ns (59.8% logic, 40.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
7.447ns delay SLICE_64 to RA[6] (totaling 9.044ns) meets
|
|
0.000ns hold offset RCLK to RA[6] by 9.044ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.424,R7C2B.Q0,R2C2C.D1,nRowColSel:CTOF_DEL, 0.301,R2C2C.D1,R2C2C.F1,SLICE_98:ROUTE, 1.571,R2C2C.F1,91.PADDO,RA_c_6:DOPAD_DEL, 3.636,91.PADDO,91.PAD,RA[6]">Data path</A> SLICE_64 to RA[6]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.424<A href="#@net:nRowColSel:R7C2B.Q0:R2C2C.D1:1.424"> R7C2B.Q0 to R2C2C.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C2C.D1 to R2C2C.F1 <A href="#@comp:SLICE_98">SLICE_98</A>
|
|
ROUTE 1 1.571<A href="#@net:RA_c_6:R2C2C.F1:91.PADDO:1.571"> R2C2C.F1 to 91.PADDO </A> <A href="#@net:RA_c_6">RA_c_6</A>
|
|
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD <A href="#@comp:RA[6]">RA[6]</A>
|
|
--------
|
|
7.447 (59.8% logic, 40.2% route), 3 logic levels.
|
|
|
|
Report: 9.044ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.738ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[5]">RA[5]</A>
|
|
|
|
Data Path Delay: 7.346ns (62.2% logic, 37.8% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.346ns delay SLICE_64 to RA[5] (totaling 9.762ns) meets
|
|
12.500ns offset RCLK to RA[5] by 2.738ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.119,R7C2B.Q0,R6C2A.A1,nRowColSel:CTOF_DEL, 0.371,R6C2A.A1,R6C2A.F1,SLICE_95:ROUTE, 1.660,R6C2A.F1,95.PADDO,RA_c_5:DOPAD_DEL, 3.636,95.PADDO,95.PAD,RA[5]">Data path</A> SLICE_64 to RA[5]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.119<A href="#@net:nRowColSel:R7C2B.Q0:R6C2A.A1:1.119"> R7C2B.Q0 to R6C2A.A1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R6C2A.A1 to R6C2A.F1 <A href="#@comp:SLICE_95">SLICE_95</A>
|
|
ROUTE 1 1.660<A href="#@net:RA_c_5:R6C2A.F1:95.PADDO:1.660"> R6C2A.F1 to 95.PADDO </A> <A href="#@net:RA_c_5">RA_c_5</A>
|
|
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD <A href="#@comp:RA[5]">RA[5]</A>
|
|
--------
|
|
7.346 (62.2% logic, 37.8% route), 3 logic levels.
|
|
|
|
Report: 9.762ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.252ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[5]">RA[5]</A>
|
|
|
|
Data Path Delay: 6.655ns (66.9% logic, 33.1% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.655ns delay SLICE_64 to RA[5] (totaling 8.252ns) meets
|
|
0.000ns hold offset RCLK to RA[5] by 8.252ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.915,R7C2B.Q0,R6C2A.A1,nRowColSel:CTOF_DEL, 0.301,R6C2A.A1,R6C2A.F1,SLICE_95:ROUTE, 1.288,R6C2A.F1,95.PADDO,RA_c_5:DOPAD_DEL, 3.636,95.PADDO,95.PAD,RA[5]">Data path</A> SLICE_64 to RA[5]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 0.915<A href="#@net:nRowColSel:R7C2B.Q0:R6C2A.A1:0.915"> R7C2B.Q0 to R6C2A.A1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R6C2A.A1 to R6C2A.F1 <A href="#@comp:SLICE_95">SLICE_95</A>
|
|
ROUTE 1 1.288<A href="#@net:RA_c_5:R6C2A.F1:95.PADDO:1.288"> R6C2A.F1 to 95.PADDO </A> <A href="#@net:RA_c_5">RA_c_5</A>
|
|
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD <A href="#@comp:RA[5]">RA[5]</A>
|
|
--------
|
|
6.655 (66.9% logic, 33.1% route), 3 logic levels.
|
|
|
|
Report: 8.252ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.279ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[4]">RA[4]</A>
|
|
|
|
Data Path Delay: 7.805ns (58.5% logic, 41.5% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.805ns delay SLICE_64 to RA[4] (totaling 10.221ns) meets
|
|
12.500ns offset RCLK to RA[4] by 2.279ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.712,R7C2B.Q0,R2C2B.D1,nRowColSel:CTOF_DEL, 0.371,R2C2B.D1,R2C2B.F1,SLICE_93:ROUTE, 1.526,R2C2B.F1,99.PADDO,RA_c_4:DOPAD_DEL, 3.636,99.PADDO,99.PAD,RA[4]">Data path</A> SLICE_64 to RA[4]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.712<A href="#@net:nRowColSel:R7C2B.Q0:R2C2B.D1:1.712"> R7C2B.Q0 to R2C2B.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C2B.D1 to R2C2B.F1 <A href="#@comp:SLICE_93">SLICE_93</A>
|
|
ROUTE 1 1.526<A href="#@net:RA_c_4:R2C2B.F1:99.PADDO:1.526"> R2C2B.F1 to 99.PADDO </A> <A href="#@net:RA_c_4">RA_c_4</A>
|
|
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD <A href="#@comp:RA[4]">RA[4]</A>
|
|
--------
|
|
7.805 (58.5% logic, 41.5% route), 3 logic levels.
|
|
|
|
Report: 10.221ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.638ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[4]">RA[4]</A>
|
|
|
|
Data Path Delay: 7.041ns (63.2% logic, 36.8% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
7.041ns delay SLICE_64 to RA[4] (totaling 8.638ns) meets
|
|
0.000ns hold offset RCLK to RA[4] by 8.638ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.424,R7C2B.Q0,R2C2B.D1,nRowColSel:CTOF_DEL, 0.301,R2C2B.D1,R2C2B.F1,SLICE_93:ROUTE, 1.165,R2C2B.F1,99.PADDO,RA_c_4:DOPAD_DEL, 3.636,99.PADDO,99.PAD,RA[4]">Data path</A> SLICE_64 to RA[4]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.424<A href="#@net:nRowColSel:R7C2B.Q0:R2C2B.D1:1.424"> R7C2B.Q0 to R2C2B.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C2B.D1 to R2C2B.F1 <A href="#@comp:SLICE_93">SLICE_93</A>
|
|
ROUTE 1 1.165<A href="#@net:RA_c_4:R2C2B.F1:99.PADDO:1.165"> R2C2B.F1 to 99.PADDO </A> <A href="#@net:RA_c_4">RA_c_4</A>
|
|
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD <A href="#@comp:RA[4]">RA[4]</A>
|
|
--------
|
|
7.041 (63.2% logic, 36.8% route), 3 logic levels.
|
|
|
|
Report: 8.638ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 1.800ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[3]">RA[3]</A>
|
|
|
|
Data Path Delay: 8.284ns (55.1% logic, 44.9% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
8.284ns delay SLICE_64 to RA[3] (totaling 10.700ns) meets
|
|
12.500ns offset RCLK to RA[3] by 1.800ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.733,R7C2B.Q0,R2C3B.D1,nRowColSel:CTOF_DEL, 0.371,R2C3B.D1,R2C3B.F1,SLICE_92:ROUTE, 1.984,R2C3B.F1,97.PADDO,RA_c_3:DOPAD_DEL, 3.636,97.PADDO,97.PAD,RA[3]">Data path</A> SLICE_64 to RA[3]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.733<A href="#@net:nRowColSel:R7C2B.Q0:R2C3B.D1:1.733"> R7C2B.Q0 to R2C3B.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C3B.D1 to R2C3B.F1 <A href="#@comp:SLICE_92">SLICE_92</A>
|
|
ROUTE 1 1.984<A href="#@net:RA_c_3:R2C3B.F1:97.PADDO:1.984"> R2C3B.F1 to 97.PADDO </A> <A href="#@net:RA_c_3">RA_c_3</A>
|
|
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD <A href="#@comp:RA[3]">RA[3]</A>
|
|
--------
|
|
8.284 (55.1% logic, 44.9% route), 3 logic levels.
|
|
|
|
Report: 10.700ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 9.042ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[3]">RA[3]</A>
|
|
|
|
Data Path Delay: 7.445ns (59.8% logic, 40.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
7.445ns delay SLICE_64 to RA[3] (totaling 9.042ns) meets
|
|
0.000ns hold offset RCLK to RA[3] by 9.042ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.461,R7C2B.Q0,R2C3B.D1,nRowColSel:CTOF_DEL, 0.301,R2C3B.D1,R2C3B.F1,SLICE_92:ROUTE, 1.532,R2C3B.F1,97.PADDO,RA_c_3:DOPAD_DEL, 3.636,97.PADDO,97.PAD,RA[3]">Data path</A> SLICE_64 to RA[3]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.461<A href="#@net:nRowColSel:R7C2B.Q0:R2C3B.D1:1.461"> R7C2B.Q0 to R2C3B.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C3B.D1 to R2C3B.F1 <A href="#@comp:SLICE_92">SLICE_92</A>
|
|
ROUTE 1 1.532<A href="#@net:RA_c_3:R2C3B.F1:97.PADDO:1.532"> R2C3B.F1 to 97.PADDO </A> <A href="#@net:RA_c_3">RA_c_3</A>
|
|
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD <A href="#@comp:RA[3]">RA[3]</A>
|
|
--------
|
|
7.445 (59.8% logic, 40.2% route), 3 logic levels.
|
|
|
|
Report: 9.042ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.967ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[2]">RA[2]</A>
|
|
|
|
Data Path Delay: 7.117ns (64.2% logic, 35.8% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.117ns delay SLICE_64 to RA[2] (totaling 9.533ns) meets
|
|
12.500ns offset RCLK to RA[2] by 2.967ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.733,R7C2B.Q0,R2C3A.D0,nRowColSel:CTOF_DEL, 0.371,R2C3A.D0,R2C3A.F0,SLICE_90:ROUTE, 0.817,R2C3A.F0,94.PADDO,RA_c_2:DOPAD_DEL, 3.636,94.PADDO,94.PAD,RA[2]">Data path</A> SLICE_64 to RA[2]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.733<A href="#@net:nRowColSel:R7C2B.Q0:R2C3A.D0:1.733"> R7C2B.Q0 to R2C3A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C3A.D0 to R2C3A.F0 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 0.817<A href="#@net:RA_c_2:R2C3A.F0:94.PADDO:0.817"> R2C3A.F0 to 94.PADDO </A> <A href="#@net:RA_c_2">RA_c_2</A>
|
|
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD <A href="#@comp:RA[2]">RA[2]</A>
|
|
--------
|
|
7.117 (64.2% logic, 35.8% route), 3 logic levels.
|
|
|
|
Report: 9.533ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.156ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[2]">RA[2]</A>
|
|
|
|
Data Path Delay: 6.559ns (67.9% logic, 32.1% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.559ns delay SLICE_64 to RA[2] (totaling 8.156ns) meets
|
|
0.000ns hold offset RCLK to RA[2] by 8.156ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.461,R7C2B.Q0,R2C3A.D0,nRowColSel:CTOF_DEL, 0.301,R2C3A.D0,R2C3A.F0,SLICE_90:ROUTE, 0.646,R2C3A.F0,94.PADDO,RA_c_2:DOPAD_DEL, 3.636,94.PADDO,94.PAD,RA[2]">Data path</A> SLICE_64 to RA[2]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.461<A href="#@net:nRowColSel:R7C2B.Q0:R2C3A.D0:1.461"> R7C2B.Q0 to R2C3A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C3A.D0 to R2C3A.F0 <A href="#@comp:SLICE_90">SLICE_90</A>
|
|
ROUTE 1 0.646<A href="#@net:RA_c_2:R2C3A.F0:94.PADDO:0.646"> R2C3A.F0 to 94.PADDO </A> <A href="#@net:RA_c_2">RA_c_2</A>
|
|
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD <A href="#@comp:RA[2]">RA[2]</A>
|
|
--------
|
|
6.559 (67.9% logic, 32.1% route), 3 logic levels.
|
|
|
|
Report: 8.156ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.967ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[1]">RA[1]</A>
|
|
|
|
Data Path Delay: 7.117ns (64.2% logic, 35.8% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.117ns delay SLICE_64 to RA[1] (totaling 9.533ns) meets
|
|
12.500ns offset RCLK to RA[1] by 2.967ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.733,R7C2B.Q0,R2C3B.D0,nRowColSel:CTOF_DEL, 0.371,R2C3B.D0,R2C3B.F0,SLICE_92:ROUTE, 0.817,R2C3B.F0,89.PADDO,RA_c_1:DOPAD_DEL, 3.636,89.PADDO,89.PAD,RA[1]">Data path</A> SLICE_64 to RA[1]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.733<A href="#@net:nRowColSel:R7C2B.Q0:R2C3B.D0:1.733"> R7C2B.Q0 to R2C3B.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C3B.D0 to R2C3B.F0 <A href="#@comp:SLICE_92">SLICE_92</A>
|
|
ROUTE 1 0.817<A href="#@net:RA_c_1:R2C3B.F0:89.PADDO:0.817"> R2C3B.F0 to 89.PADDO </A> <A href="#@net:RA_c_1">RA_c_1</A>
|
|
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD <A href="#@comp:RA[1]">RA[1]</A>
|
|
--------
|
|
7.117 (64.2% logic, 35.8% route), 3 logic levels.
|
|
|
|
Report: 9.533ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.156ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[1]">RA[1]</A>
|
|
|
|
Data Path Delay: 6.559ns (67.9% logic, 32.1% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.559ns delay SLICE_64 to RA[1] (totaling 8.156ns) meets
|
|
0.000ns hold offset RCLK to RA[1] by 8.156ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.461,R7C2B.Q0,R2C3B.D0,nRowColSel:CTOF_DEL, 0.301,R2C3B.D0,R2C3B.F0,SLICE_92:ROUTE, 0.646,R2C3B.F0,89.PADDO,RA_c_1:DOPAD_DEL, 3.636,89.PADDO,89.PAD,RA[1]">Data path</A> SLICE_64 to RA[1]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.461<A href="#@net:nRowColSel:R7C2B.Q0:R2C3B.D0:1.461"> R7C2B.Q0 to R2C3B.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C3B.D0 to R2C3B.F0 <A href="#@comp:SLICE_92">SLICE_92</A>
|
|
ROUTE 1 0.646<A href="#@net:RA_c_1:R2C3B.F0:89.PADDO:0.646"> R2C3B.F0 to 89.PADDO </A> <A href="#@net:RA_c_1">RA_c_1</A>
|
|
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD <A href="#@comp:RA[1]">RA[1]</A>
|
|
--------
|
|
6.559 (67.9% logic, 32.1% route), 3 logic levels.
|
|
|
|
Report: 8.156ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.988ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[0]">RA[0]</A>
|
|
|
|
Data Path Delay: 7.096ns (64.4% logic, 35.6% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.096ns delay SLICE_64 to RA[0] (totaling 9.512ns) meets
|
|
12.500ns offset RCLK to RA[0] by 2.988ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.712,R7C2B.Q0,R2C2B.D0,nRowColSel:CTOF_DEL, 0.371,R2C2B.D0,R2C2B.F0,SLICE_93:ROUTE, 0.817,R2C2B.F0,98.PADDO,RA_c_0:DOPAD_DEL, 3.636,98.PADDO,98.PAD,RA[0]">Data path</A> SLICE_64 to RA[0]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.712<A href="#@net:nRowColSel:R7C2B.Q0:R2C2B.D0:1.712"> R7C2B.Q0 to R2C2B.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R2C2B.D0 to R2C2B.F0 <A href="#@comp:SLICE_93">SLICE_93</A>
|
|
ROUTE 1 0.817<A href="#@net:RA_c_0:R2C2B.F0:98.PADDO:0.817"> R2C2B.F0 to 98.PADDO </A> <A href="#@net:RA_c_0">RA_c_0</A>
|
|
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD <A href="#@comp:RA[0]">RA[0]</A>
|
|
--------
|
|
7.096 (64.4% logic, 35.6% route), 3 logic levels.
|
|
|
|
Report: 9.512ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.119ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RA[0]">RA[0]</A>
|
|
|
|
Data Path Delay: 6.522ns (68.3% logic, 31.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.522ns delay SLICE_64 to RA[0] (totaling 8.119ns) meets
|
|
0.000ns hold offset RCLK to RA[0] by 8.119ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.424,R7C2B.Q0,R2C2B.D0,nRowColSel:CTOF_DEL, 0.301,R2C2B.D0,R2C2B.F0,SLICE_93:ROUTE, 0.646,R2C2B.F0,98.PADDO,RA_c_0:DOPAD_DEL, 3.636,98.PADDO,98.PAD,RA[0]">Data path</A> SLICE_64 to RA[0]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.424<A href="#@net:nRowColSel:R7C2B.Q0:R2C2B.D0:1.424"> R7C2B.Q0 to R2C2B.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R2C2B.D0 to R2C2B.F0 <A href="#@comp:SLICE_93">SLICE_93</A>
|
|
ROUTE 1 0.646<A href="#@net:RA_c_0:R2C2B.F0:98.PADDO:0.646"> R2C2B.F0 to 98.PADDO </A> <A href="#@net:RA_c_0">RA_c_0</A>
|
|
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD <A href="#@comp:RA[0]">RA[0]</A>
|
|
--------
|
|
6.522 (68.3% logic, 31.7% route), 3 logic levels.
|
|
|
|
Report: 8.119ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 5.071ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_60">nRCS_364</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRCS">nRCS</A>
|
|
|
|
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_60 and
|
|
5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
|
|
12.500ns offset RCLK to nRCS by 5.071ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R2C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_60:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R2C5B.CLK:1.353"> 86.PADDI to R2C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C5B.CLK,R2C5B.Q0,SLICE_60:ROUTE, 0.817,R2C5B.Q0,77.PADDO,nRCS_c:DOPAD_DEL, 3.636,77.PADDO,77.PAD,nRCS">Data path</A> SLICE_60 to nRCS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C5B.CLK to R2C5B.Q0 <A href="#@comp:SLICE_60">SLICE_60</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 0.817<A href="#@net:nRCS_c:R2C5B.Q0:77.PADDO:0.817"> R2C5B.Q0 to 77.PADDO </A> <A href="#@net:nRCS_c">nRCS_c</A>
|
|
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD <A href="#@comp:nRCS">nRCS</A>
|
|
--------
|
|
5.013 (83.7% logic, 16.3% route), 2 logic levels.
|
|
|
|
Report: 7.429ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 6.394ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_60">nRCS_364</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRCS">nRCS</A>
|
|
|
|
Data Path Delay: 4.797ns (86.5% logic, 13.5% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_60 and
|
|
4.797ns delay SLICE_60 to nRCS (totaling 6.394ns) meets
|
|
0.000ns hold offset RCLK to nRCS by 6.394ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R2C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_60:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R2C5B.CLK:0.730"> 86.PADDI to R2C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C5B.CLK,R2C5B.Q0,SLICE_60:ROUTE, 0.646,R2C5B.Q0,77.PADDO,nRCS_c:DOPAD_DEL, 3.636,77.PADDO,77.PAD,nRCS">Data path</A> SLICE_60 to nRCS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R2C5B.CLK to R2C5B.Q0 <A href="#@comp:SLICE_60">SLICE_60</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 0.646<A href="#@net:nRCS_c:R2C5B.Q0:77.PADDO:0.646"> R2C5B.Q0 to 77.PADDO </A> <A href="#@net:nRCS_c">nRCS_c</A>
|
|
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD <A href="#@comp:nRCS">nRCS</A>
|
|
--------
|
|
4.797 (86.5% logic, 13.5% route), 2 logic levels.
|
|
|
|
Report: 6.394ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.806ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_34">RCKE_363</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RCKE">RCKE</A>
|
|
|
|
Data Path Delay: 6.278ns (66.8% logic, 33.2% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_34 and
|
|
6.278ns delay SLICE_34 to RCKE (totaling 8.694ns) meets
|
|
12.500ns offset RCLK to RCKE by 3.806ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R6C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R6C5B.CLK:1.353"> 86.PADDI to R6C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R6C5B.CLK,R6C5B.Q0,SLICE_34:ROUTE, 2.082,R6C5B.Q0,82.PADDO,RCKE_c:DOPAD_DEL, 3.636,82.PADDO,82.PAD,RCKE">Data path</A> SLICE_34 to RCKE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R6C5B.CLK to R6C5B.Q0 <A href="#@comp:SLICE_34">SLICE_34</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 4 2.082<A href="#@net:RCKE_c:R6C5B.Q0:82.PADDO:2.082"> R6C5B.Q0 to 82.PADDO </A> <A href="#@net:RCKE_c">RCKE_c</A>
|
|
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD <A href="#@comp:RCKE">RCKE</A>
|
|
--------
|
|
6.278 (66.8% logic, 33.2% route), 2 logic levels.
|
|
|
|
Report: 8.694ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 7.385ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_34">RCKE_363</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RCKE">RCKE</A>
|
|
|
|
Data Path Delay: 5.788ns (71.7% logic, 28.3% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_34 and
|
|
5.788ns delay SLICE_34 to RCKE (totaling 7.385ns) meets
|
|
0.000ns hold offset RCLK to RCKE by 7.385ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R6C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R6C5B.CLK:0.730"> 86.PADDI to R6C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R6C5B.CLK,R6C5B.Q0,SLICE_34:ROUTE, 1.637,R6C5B.Q0,82.PADDO,RCKE_c:DOPAD_DEL, 3.636,82.PADDO,82.PAD,RCKE">Data path</A> SLICE_34 to RCKE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R6C5B.CLK to R6C5B.Q0 <A href="#@comp:SLICE_34">SLICE_34</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 4 1.637<A href="#@net:RCKE_c:R6C5B.Q0:82.PADDO:1.637"> R6C5B.Q0 to 82.PADDO </A> <A href="#@net:RCKE_c">RCKE_c</A>
|
|
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD <A href="#@comp:RCKE">RCKE</A>
|
|
--------
|
|
5.788 (71.7% logic, 28.3% route), 2 logic levels.
|
|
|
|
Report: 7.385ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 5.071ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_63">nRWE_367</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRWE">nRWE</A>
|
|
|
|
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_63 and
|
|
5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
|
|
12.500ns offset RCLK to nRWE by 5.071ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R3C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_63:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R3C5B.CLK:1.353"> 86.PADDI to R3C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R3C5B.CLK,R3C5B.Q0,SLICE_63:ROUTE, 0.817,R3C5B.Q0,72.PADDO,nRWE_c:DOPAD_DEL, 3.636,72.PADDO,72.PAD,nRWE">Data path</A> SLICE_63 to nRWE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R3C5B.CLK to R3C5B.Q0 <A href="#@comp:SLICE_63">SLICE_63</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 0.817<A href="#@net:nRWE_c:R3C5B.Q0:72.PADDO:0.817"> R3C5B.Q0 to 72.PADDO </A> <A href="#@net:nRWE_c">nRWE_c</A>
|
|
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD <A href="#@comp:nRWE">nRWE</A>
|
|
--------
|
|
5.013 (83.7% logic, 16.3% route), 2 logic levels.
|
|
|
|
Report: 7.429ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 6.394ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_63">nRWE_367</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRWE">nRWE</A>
|
|
|
|
Data Path Delay: 4.797ns (86.5% logic, 13.5% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_63 and
|
|
4.797ns delay SLICE_63 to nRWE (totaling 6.394ns) meets
|
|
0.000ns hold offset RCLK to nRWE by 6.394ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R3C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_63:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R3C5B.CLK:0.730"> 86.PADDI to R3C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R3C5B.CLK,R3C5B.Q0,SLICE_63:ROUTE, 0.646,R3C5B.Q0,72.PADDO,nRWE_c:DOPAD_DEL, 3.636,72.PADDO,72.PAD,nRWE">Data path</A> SLICE_63 to nRWE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R3C5B.CLK to R3C5B.Q0 <A href="#@comp:SLICE_63">SLICE_63</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 0.646<A href="#@net:nRWE_c:R3C5B.Q0:72.PADDO:0.646"> R3C5B.Q0 to 72.PADDO </A> <A href="#@net:nRWE_c">nRWE_c</A>
|
|
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD <A href="#@comp:nRWE">nRWE</A>
|
|
--------
|
|
4.797 (86.5% logic, 13.5% route), 2 logic levels.
|
|
|
|
Report: 6.394ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.360ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_61">nRRAS_365</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRRAS">nRRAS</A>
|
|
|
|
Data Path Delay: 5.724ns (73.3% logic, 26.7% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_61 and
|
|
5.724ns delay SLICE_61 to nRRAS (totaling 8.140ns) meets
|
|
12.500ns offset RCLK to nRRAS by 4.360ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R2C4C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_61:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R2C4C.CLK:1.353"> 86.PADDI to R2C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C4C.CLK,R2C4C.Q0,SLICE_61:ROUTE, 1.528,R2C4C.Q0,73.PADDO,nRRAS_c:DOPAD_DEL, 3.636,73.PADDO,73.PAD,nRRAS">Data path</A> SLICE_61 to nRRAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 <A href="#@comp:SLICE_61">SLICE_61</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 2 1.528<A href="#@net:nRRAS_c:R2C4C.Q0:73.PADDO:1.528"> R2C4C.Q0 to 73.PADDO </A> <A href="#@net:nRRAS_c">nRRAS_c</A>
|
|
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD <A href="#@comp:nRRAS">nRRAS</A>
|
|
--------
|
|
5.724 (73.3% logic, 26.7% route), 2 logic levels.
|
|
|
|
Report: 8.140ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 6.920ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_61">nRRAS_365</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRRAS">nRRAS</A>
|
|
|
|
Data Path Delay: 5.323ns (78.0% logic, 22.0% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_61 and
|
|
5.323ns delay SLICE_61 to nRRAS (totaling 6.920ns) meets
|
|
0.000ns hold offset RCLK to nRRAS by 6.920ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R2C4C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_61:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R2C4C.CLK:0.730"> 86.PADDI to R2C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C4C.CLK,R2C4C.Q0,SLICE_61:ROUTE, 1.172,R2C4C.Q0,73.PADDO,nRRAS_c:DOPAD_DEL, 3.636,73.PADDO,73.PAD,nRRAS">Data path</A> SLICE_61 to nRRAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R2C4C.CLK to R2C4C.Q0 <A href="#@comp:SLICE_61">SLICE_61</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 2 1.172<A href="#@net:nRRAS_c:R2C4C.Q0:73.PADDO:1.172"> R2C4C.Q0 to 73.PADDO </A> <A href="#@net:nRRAS_c">nRRAS_c</A>
|
|
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD <A href="#@comp:nRRAS">nRRAS</A>
|
|
--------
|
|
5.323 (78.0% logic, 22.0% route), 2 logic levels.
|
|
|
|
Report: 6.920ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.904ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_58">nRCAS_366</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRCAS">nRCAS</A>
|
|
|
|
Data Path Delay: 6.180ns (67.9% logic, 32.1% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_58 and
|
|
6.180ns delay SLICE_58 to nRCAS (totaling 8.596ns) meets
|
|
12.500ns offset RCLK to nRCAS by 3.904ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R2C4A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_58:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R2C4A.CLK:1.353"> 86.PADDI to R2C4A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C4A.CLK,R2C4A.Q0,SLICE_58:ROUTE, 1.984,R2C4A.Q0,78.PADDO,nRCAS_c:DOPAD_DEL, 3.636,78.PADDO,78.PAD,nRCAS">Data path</A> SLICE_58 to nRCAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R2C4A.CLK to R2C4A.Q0 <A href="#@comp:SLICE_58">SLICE_58</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 1.984<A href="#@net:nRCAS_c:R2C4A.Q0:78.PADDO:1.984"> R2C4A.Q0 to 78.PADDO </A> <A href="#@net:nRCAS_c">nRCAS_c</A>
|
|
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD <A href="#@comp:nRCAS">nRCAS</A>
|
|
--------
|
|
6.180 (67.9% logic, 32.1% route), 2 logic levels.
|
|
|
|
Report: 8.596ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 7.280ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_58">nRCAS_366</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:nRCAS">nRCAS</A>
|
|
|
|
Data Path Delay: 5.683ns (73.0% logic, 27.0% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_58 and
|
|
5.683ns delay SLICE_58 to nRCAS (totaling 7.280ns) meets
|
|
0.000ns hold offset RCLK to nRCAS by 7.280ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R2C4A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_58:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R2C4A.CLK:0.730"> 86.PADDI to R2C4A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C4A.CLK,R2C4A.Q0,SLICE_58:ROUTE, 1.532,R2C4A.Q0,78.PADDO,nRCAS_c:DOPAD_DEL, 3.636,78.PADDO,78.PAD,nRCAS">Data path</A> SLICE_58 to nRCAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R2C4A.CLK to R2C4A.Q0 <A href="#@comp:SLICE_58">SLICE_58</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 1 1.532<A href="#@net:nRCAS_c:R2C4A.Q0:78.PADDO:1.532"> R2C4A.Q0 to 78.PADDO </A> <A href="#@net:nRCAS_c">nRCAS_c</A>
|
|
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD <A href="#@comp:nRCAS">nRCAS</A>
|
|
--------
|
|
5.683 (73.0% logic, 27.0% route), 2 logic levels.
|
|
|
|
Report: 7.280ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.919ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RDQMH">RDQMH</A>
|
|
|
|
Data Path Delay: 7.165ns (63.7% logic, 36.3% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.165ns delay SLICE_64 to RDQMH (totaling 9.581ns) meets
|
|
12.500ns offset RCLK to RDQMH by 2.919ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.781,R7C2B.Q0,R3C5A.D0,nRowColSel:CTOF_DEL, 0.371,R3C5A.D0,R3C5A.F0,SLICE_87:ROUTE, 0.817,R3C5A.F0,76.PADDO,RDQMH_c:DOPAD_DEL, 3.636,76.PADDO,76.PAD,RDQMH">Data path</A> SLICE_64 to RDQMH:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.781<A href="#@net:nRowColSel:R7C2B.Q0:R3C5A.D0:1.781"> R7C2B.Q0 to R3C5A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R3C5A.D0 to R3C5A.F0 <A href="#@comp:SLICE_87">SLICE_87</A>
|
|
ROUTE 1 0.817<A href="#@net:RDQMH_c:R3C5A.F0:76.PADDO:0.817"> R3C5A.F0 to 76.PADDO </A> <A href="#@net:RDQMH_c">RDQMH_c</A>
|
|
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD <A href="#@comp:RDQMH">RDQMH</A>
|
|
--------
|
|
7.165 (63.7% logic, 36.3% route), 3 logic levels.
|
|
|
|
Report: 9.581ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.229ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RDQMH">RDQMH</A>
|
|
|
|
Data Path Delay: 6.632ns (67.1% logic, 32.9% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.632ns delay SLICE_64 to RDQMH (totaling 8.229ns) meets
|
|
0.000ns hold offset RCLK to RDQMH by 8.229ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.534,R7C2B.Q0,R3C5A.D0,nRowColSel:CTOF_DEL, 0.301,R3C5A.D0,R3C5A.F0,SLICE_87:ROUTE, 0.646,R3C5A.F0,76.PADDO,RDQMH_c:DOPAD_DEL, 3.636,76.PADDO,76.PAD,RDQMH">Data path</A> SLICE_64 to RDQMH:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.534<A href="#@net:nRowColSel:R7C2B.Q0:R3C5A.D0:1.534"> R7C2B.Q0 to R3C5A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R3C5A.D0 to R3C5A.F0 <A href="#@comp:SLICE_87">SLICE_87</A>
|
|
ROUTE 1 0.646<A href="#@net:RDQMH_c:R3C5A.F0:76.PADDO:0.646"> R3C5A.F0 to 76.PADDO </A> <A href="#@net:RDQMH_c">RDQMH_c</A>
|
|
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD <A href="#@comp:RDQMH">RDQMH</A>
|
|
--------
|
|
6.632 (67.1% logic, 32.9% route), 3 logic levels.
|
|
|
|
Report: 8.229ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.415ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RDQML">RDQML</A>
|
|
|
|
Data Path Delay: 7.669ns (59.6% logic, 40.4% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.416ns delay RCLK to SLICE_64 and
|
|
7.669ns delay SLICE_64 to RDQML (totaling 10.085ns) meets
|
|
12.500ns offset RCLK to RDQML by 2.415ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.353,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 1.353<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:1.353"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
2.416 (44.0% logic, 56.0% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 1.119,R7C2B.Q0,R6C2A.A0,nRowColSel:CTOF_DEL, 0.371,R6C2A.A0,R6C2A.F0,SLICE_95:ROUTE, 1.983,R6C2A.F0,61.PADDO,RDQML_c:DOPAD_DEL, 3.636,61.PADDO,61.PAD,RDQML">Data path</A> SLICE_64 to RDQML:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 1.119<A href="#@net:nRowColSel:R7C2B.Q0:R6C2A.A0:1.119"> R7C2B.Q0 to R6C2A.A0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.371 R6C2A.A0 to R6C2A.F0 <A href="#@comp:SLICE_95">SLICE_95</A>
|
|
ROUTE 1 1.983<A href="#@net:RDQML_c:R6C2A.F0:61.PADDO:1.983"> R6C2A.F0 to 61.PADDO </A> <A href="#@net:RDQML_c">RDQML_c</A>
|
|
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD <A href="#@comp:RDQML">RDQML</A>
|
|
--------
|
|
7.669 (59.6% logic, 40.4% route), 3 logic levels.
|
|
|
|
Report: 10.085ns is the minimum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 8.535ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
|
|
Destination: Port Pad <A href="#@comp:RDQML">RDQML</A>
|
|
|
|
Data Path Delay: 6.938ns (64.2% logic, 35.8% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 1.597ns (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
1.597ns delay RCLK to SLICE_64 and
|
|
6.938ns delay SLICE_64 to RDQML (totaling 8.535ns) meets
|
|
0.000ns hold offset RCLK to RDQML by 8.535ns
|
|
|
|
Physical Path Details:
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.730,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
|
|
ROUTE 39 0.730<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.730"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
|
|
--------
|
|
1.597 (54.3% logic, 45.7% route), 1 logic levels.
|
|
|
|
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.915,R7C2B.Q0,R6C2A.A0,nRowColSel:CTOF_DEL, 0.301,R6C2A.A0,R6C2A.F0,SLICE_95:ROUTE, 1.571,R6C2A.F0,61.PADDO,RDQML_c:DOPAD_DEL, 3.636,61.PADDO,61.PAD,RDQML">Data path</A> SLICE_64 to RDQML:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.515 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
|
|
ROUTE 13 0.915<A href="#@net:nRowColSel:R7C2B.Q0:R6C2A.A0:0.915"> R7C2B.Q0 to R6C2A.A0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
|
|
CTOF_DEL --- 0.301 R6C2A.A0 to R6C2A.F0 <A href="#@comp:SLICE_95">SLICE_95</A>
|
|
ROUTE 1 1.571<A href="#@net:RDQML_c:R6C2A.F0:61.PADDO:1.571"> R6C2A.F0 to 61.PADDO </A> <A href="#@net:RDQML_c">RDQML_c</A>
|
|
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD <A href="#@comp:RDQML">RDQML</A>
|
|
--------
|
|
6.938 (64.2% logic, 35.8% route), 3 logic levels.
|
|
|
|
Report: 8.535ns is the maximum offset for this preference.
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
</A><A name="CLOCK_TO_OUT PORT 'RD[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
|
|
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 24.062 ns| 7
|
|
| | |
|
|
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
|
|
| | |
|
|
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
|
|
| | |
|
|
PERIOD NET "RCLK_c" 15.000000 ns ; | 15.000 ns| 8.725 ns| 6
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 8.596 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 7.280 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.816 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 9.193 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.512 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.119 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.523 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.063 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.678 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 9.044 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.762 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.252 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.221 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.638 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.700 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 9.042 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.533 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.156 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.533 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.156 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.512 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.119 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 7.429 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.394 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 8.694 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 7.385 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 7.429 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.394 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 8.140 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.920 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 8.596 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 7.280 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.581 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.229 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.085 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.535 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
All preferences were met.
|
|
|
|
|
|
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
|
------------------------
|
|
|
|
Found 4 clocks:
|
|
|
|
Clock Domain: <A href="#@net:nCRAS_c">nCRAS_c</A> Source: nCRAS.PAD Loads: 9
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: <A href="#@net:nCCAS_c">nCCAS_c</A> Source: nCCAS.PAD Loads: 7
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD Loads: 39
|
|
Covered under: PERIOD NET "RCLK_c" 15.000000 ns ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:nCRAS_c">nCRAS_c</A> Source: nCRAS.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: <A href="#@net:PHI2_c">PHI2_c</A> Source: PHI2.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: <A href="#@net:PHI2_c">PHI2_c</A> Source: PHI2.PAD Loads: 14
|
|
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
|
|
Timing summary (Setup):
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
Cumulative negative slack: 0
|
|
|
|
Constraints cover 538 paths, 6 nets, and 436 connections (70.89% coverage)
|
|
|