426 lines
16 KiB
HTML
426 lines
16 KiB
HTML
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<HEAD><TITLE>Project Summary</TITLE>
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<PRE><A name="Mrp"></A>
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Lattice Mapping Report File for Design Module 'RAM2GS'
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<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
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Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
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RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
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RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O
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neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200
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HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA
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M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset
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D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
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Target Vendor: LATTICE
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Target Device: LCMXO2-1200HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
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Mapped on: 08/15/23 05:22:05
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<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
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Number of registers: 102 out of 1520 (7%)
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PFU registers: 102 out of 1280 (8%)
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PIO registers: 0 out of 240 (0%)
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Number of SLICEs: 75 out of 640 (12%)
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SLICEs as Logic/ROM: 75 out of 640 (12%)
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SLICEs as RAM: 0 out of 480 (0%)
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SLICEs as Carry: 10 out of 640 (2%)
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Number of LUT4s: 143 out of 1280 (11%)
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Number used as logic LUTs: 123
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Number used as distributed RAM: 0
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Number used as ripple logic: 20
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Number used as shift registers: 0
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Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
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Number of block RAMs: 0 out of 7 (0%)
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Number of GSRs: 0 out of 1 (0%)
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EFB used : No
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JTAG used : No
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Readback used : No
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Oscillator used : No
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Startup used : No
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POR : On
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Bandgap : On
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Number of Power Controller: 0 out of 1 (0%)
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
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Number of DCCA: 0 out of 8 (0%)
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Number of DCMA: 0 out of 2 (0%)
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Number of PLLs: 0 out of 1 (0%)
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Number of DQSDLLs: 0 out of 2 (0%)
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Number of CLKDIVC: 0 out of 4 (0%)
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Number of ECLKSYNCA: 0 out of 4 (0%)
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Number of ECLKBRIDGECS: 0 out of 2 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 4
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Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
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Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
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Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
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Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
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Number of Clock Enables: 14
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Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
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Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
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Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
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Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
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Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
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Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
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Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
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Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
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Net Ready_N_292: 1 loads, 1 LSLICEs
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Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
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Number of LSRs: 7
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Net RASr2: 1 loads, 1 LSLICEs
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Net nRowColSel_N_35: 1 loads, 1 LSLICEs
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Net Ready: 7 loads, 7 LSLICEs
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Net nRWE_N_177: 1 loads, 1 LSLICEs
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Net C1Submitted_N_237: 2 loads, 2 LSLICEs
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Net n2366: 2 loads, 2 LSLICEs
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Net nRowColSel_N_34: 1 loads, 1 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net Ready: 18 loads
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Net InitReady: 15 loads
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Net RASr2: 15 loads
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Net nRowColSel_N_35: 13 loads
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Net nRowColSel: 12 loads
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Net Din_c_4: 10 loads
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Net MAin_c_1: 10 loads
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Net Din_c_5: 9 loads
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Net MAin_c_0: 9 loads
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Net Din_c_0: 8 loads
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Number of warnings: 0
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Number of errors: 0
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<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
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No errors or warnings present.
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<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| RD[7] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[6] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[5] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[4] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[3] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[2] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[1] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RD[0] | BIDIR | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[7] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[6] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[5] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[4] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[3] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[2] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[1] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Dout[0] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| LED | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RBA[1] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RBA[0] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[11] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[10] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[9] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[8] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[7] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[6] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[5] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[4] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[3] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[2] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[1] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RA[0] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nRCS | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RCKE | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nRWE | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nRRAS | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nRCAS | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RDQMH | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RDQML | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nUFMCS | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| UFMCLK | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| UFMSDI | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| PHI2 | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[9] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[8] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[7] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[6] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[5] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[4] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[3] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[2] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[1] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| MAin[0] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| CROW[1] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| CROW[0] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[7] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[6] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[5] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[4] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[3] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[2] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[1] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| Din[0] | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nCCAS | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nCRAS | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| nFWE | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| RCLK | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| UFMSDO | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
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Block i2 undriven or does not drive anything - clipped.
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Block GSR_INST undriven or does not drive anything - clipped.
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Signal PHI2_N_120 was merged into signal PHI2_c
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Signal n1407 was merged into signal nRowColSel_N_34
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Signal n2380 was merged into signal Ready
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Signal n1408 was merged into signal nRowColSel_N_35
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Signal nRWE_N_176 was merged into signal nRWE_N_177
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Signal GND_net undriven or does not drive anything - clipped.
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Signal VCC_net undriven or does not drive anything - clipped.
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Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
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Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
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Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
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Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
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Block i2046 was optimized away.
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Block i1118_1_lut was optimized away.
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Block i637_1_lut_rep_31 was optimized away.
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Block i1119_1_lut was optimized away.
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Block nRWE_I_50_1_lut was optimized away.
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Block i1 was optimized away.
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<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 41 MB
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
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reserved.
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