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363 lines
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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Tue Aug 15 05:03:26 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: RAM2GS
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
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122 items scored, 119 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 7.418ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i1 (from PHI2_c +)
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Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
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Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels.
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Constraint Details:
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9.633ns data_path Bank_i1 to CmdEnable_405 violates
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2.500ns delay constraint less
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0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
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Path Details: Bank_i1 to CmdEnable_405
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c)
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Route 1 e 0.941 Bank[1]
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LUT4 --- 0.493 D to Z i8_4_lut
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Route 2 e 1.141 n22
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LUT4 --- 0.493 B to Z i11_3_lut_rep_20
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Route 7 e 1.502 n2369
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LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut
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Route 1 e 0.941 n2362
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LUT4 --- 0.493 D to Z i1_4_lut_adj_13
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Route 3 e 1.258 C1Submitted_N_237
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LUT4 --- 0.493 C to Z i34_4_lut
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Route 1 e 0.941 PHI2_N_120_enable_1
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--------
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9.633 (30.2% logic, 69.8% route), 6 logic levels.
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Error: The following path violates requirements by 7.418ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
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Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
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Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels.
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Constraint Details:
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9.633ns data_path Bank_i4 to CmdEnable_405 violates
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2.500ns delay constraint less
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0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
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Path Details: Bank_i4 to CmdEnable_405
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
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Route 1 e 0.941 Bank[4]
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LUT4 --- 0.493 C to Z i8_4_lut
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Route 2 e 1.141 n22
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LUT4 --- 0.493 B to Z i11_3_lut_rep_20
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Route 7 e 1.502 n2369
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LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut
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Route 1 e 0.941 n2362
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LUT4 --- 0.493 D to Z i1_4_lut_adj_13
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Route 3 e 1.258 C1Submitted_N_237
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LUT4 --- 0.493 C to Z i34_4_lut
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Route 1 e 0.941 PHI2_N_120_enable_1
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--------
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9.633 (30.2% logic, 69.8% route), 6 logic levels.
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Error: The following path violates requirements by 7.256ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
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Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
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Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels.
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Constraint Details:
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9.471ns data_path Bank_i3 to CmdEnable_405 violates
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2.500ns delay constraint less
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0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
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Path Details: Bank_i3 to CmdEnable_405
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c)
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Route 1 e 0.941 Bank[3]
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LUT4 --- 0.493 B to Z i1989_2_lut
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Route 1 e 0.941 n2287
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LUT4 --- 0.493 C to Z i12_4_lut
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Route 8 e 1.540 n26
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LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut
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Route 1 e 0.941 n2362
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LUT4 --- 0.493 D to Z i1_4_lut_adj_13
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Route 3 e 1.258 C1Submitted_N_237
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LUT4 --- 0.493 C to Z i34_4_lut
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Route 1 e 0.941 PHI2_N_120_enable_1
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--------
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9.471 (30.7% logic, 69.3% route), 6 logic levels.
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Warning: 9.918 ns is the maximum delay for this constraint.
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
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498 items scored, 186 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 3.319ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_610__i13 (from RCLK_c +)
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Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
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Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
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Constraint Details:
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8.159ns data_path FS_610__i13 to nUFMCS_415 violates
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5.000ns delay constraint less
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0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
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Path Details: FS_610__i13 to nUFMCS_415
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c)
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Route 3 e 1.315 FS[13]
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LUT4 --- 0.493 B to Z i3_4_lut_adj_7
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Route 5 e 1.405 n10
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LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
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Route 2 e 1.141 n2368
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LUT4 --- 0.493 B to Z i1_2_lut_4_lut
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Route 1 e 0.941 n64
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LUT4 --- 0.493 B to Z i1448_4_lut
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Route 1 e 0.941 nUFMCS_N_199
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--------
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8.159 (29.6% logic, 70.4% route), 5 logic levels.
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Error: The following path violates requirements by 3.319ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_610__i15 (from RCLK_c +)
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Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
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Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
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Constraint Details:
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8.159ns data_path FS_610__i15 to nUFMCS_415 violates
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5.000ns delay constraint less
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0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
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Path Details: FS_610__i15 to nUFMCS_415
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c)
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Route 3 e 1.315 FS[15]
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LUT4 --- 0.493 C to Z i3_4_lut_adj_7
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Route 5 e 1.405 n10
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LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
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Route 2 e 1.141 n2368
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LUT4 --- 0.493 B to Z i1_2_lut_4_lut
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Route 1 e 0.941 n64
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LUT4 --- 0.493 B to Z i1448_4_lut
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Route 1 e 0.941 nUFMCS_N_199
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--------
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8.159 (29.6% logic, 70.4% route), 5 logic levels.
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Error: The following path violates requirements by 3.319ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_610__i16 (from RCLK_c +)
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Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
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Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
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Constraint Details:
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8.159ns data_path FS_610__i16 to nUFMCS_415 violates
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5.000ns delay constraint less
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0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
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Path Details: FS_610__i16 to nUFMCS_415
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c)
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Route 3 e 1.315 FS[16]
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LUT4 --- 0.493 D to Z i3_4_lut_adj_7
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Route 5 e 1.405 n10
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LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
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Route 2 e 1.141 n2368
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LUT4 --- 0.493 B to Z i1_2_lut_4_lut
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Route 1 e 0.941 n64
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LUT4 --- 0.493 B to Z i1448_4_lut
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Route 1 e 0.941 nUFMCS_N_199
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--------
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8.159 (29.6% logic, 70.4% route), 5 logic levels.
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Warning: 8.319 ns is the maximum delay for this constraint.
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 5.000000 -name | | |
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clk3 [get_nets nCCAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk2 [get_nets nCRAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 *
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create_clock -period 5.000000 -name | | |
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clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 *
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--------------------------------------------------------------------------------
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2 constraints not met.
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--------------------------------------------------------------------------------
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Critical Nets | Loads| Errors| % of total
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--------------------------------------------------------------------------------
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n26 | 8| 84| 27.54%
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n1997 | 1| 36| 11.80%
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n1996 | 1| 35| 11.48%
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n1995 | 1| 33| 10.82%
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n10 | 5| 32| 10.49%
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n1998 | 1| 32| 10.49%
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--------------------------------------------------------------------------------
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 305 Score: 1313492
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Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage)
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Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes
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CPU_TIME_REPORT: 0 secs
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