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RAM2GS/CPLD/LCMXO2-1200HC/impl1/automake.log

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map -a "MachXO2" -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_1200HC_impl1.ngd" -o "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_1200HC_impl1.prf" -mp "RAM2GS_LCMXO2_1200HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf" -c 0
map: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Process the file: RAM2GS_LCMXO2_1200HC_impl1.ngd
Picdevice="LCMXO2-1200HC"
Pictype="TQFP100"
Picspeed=4
Remove unused logic
Do not produce over sized NCDs.
Part used: LCMXO2-1200HCTQFP100, Performance used: 4.
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Running general design DRC...
Removing unused logic...
Optimizing...
Design Summary:
Number of registers: 102 out of 1520 (7%)
PFU registers: 102 out of 1280 (8%)
PIO registers: 0 out of 240 (0%)
Number of SLICEs: 75 out of 640 (12%)
SLICEs as Logic/ROM: 75 out of 640 (12%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 10 out of 640 (2%)
Number of LUT4s: 143 out of 1280 (11%)
Number used as logic LUTs: 123
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 4
Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
Number of Clock Enables: 14
Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
Net Ready_N_292: 1 loads, 1 LSLICEs
Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
Number of LSRs: 7
Net RASr2: 1 loads, 1 LSLICEs
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
Net Ready: 7 loads, 7 LSLICEs
Net nRWE_N_177: 1 loads, 1 LSLICEs
Net C1Submitted_N_237: 2 loads, 2 LSLICEs
Net n2366: 2 loads, 2 LSLICEs
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net Ready: 18 loads
Net InitReady: 15 loads
Net RASr2: 15 loads
Net nRowColSel_N_35: 13 loads
Net nRowColSel: 12 loads
Net Din_c_4: 10 loads
Net MAin_c_1: 10 loads
Net Din_c_5: 9 loads
Net MAin_c_0: 9 loads
Net Din_c_0: 8 loads
Number of warnings: 0
Number of errors: 0
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 41 MB
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
ncd2vdb "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb"
Loading device for application ncd2vdb from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
trce -f "RAM2GS_LCMXO2_1200HC_impl1.mt" -o "RAM2GS_LCMXO2_1200HC_impl1.tw1" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf"
trce: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Tue Aug 15 05:22:07 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Setup):
---------------
Timing errors: 349 Score: 848079
Cumulative negative slack: 584487
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Tue Aug 15 05:22:07 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
Device,speed: LCMXO2-1200HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 349 (setup), 0 (hold)
Score: 848079 (setup), 0 (hold)
Cumulative negative slack: 584487 (584487+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 48 MB
ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo" -w -neg
ldbanno: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file.
Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format.
Writing Verilog netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
<postMsg mid="35400250" type="Info" dynamic="1" navigation="0" arg0="0" />
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 40 MB
ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho" -w -neg
ldbanno: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file.
Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format.
Writing VHDL netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
<postMsg mid="35400250" type="Info" dynamic="1" navigation="0" arg0="0" />
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 41 MB
mpartrce -p "RAM2GS_LCMXO2_1200HC_impl1.p2t" -f "RAM2GS_LCMXO2_1200HC_impl1.p3t" -tf "RAM2GS_LCMXO2_1200HC_impl1.pt" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.ncd"
---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
Running par. Please wait . . .
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
Tue Aug 15 05:22:08 2023
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 67+4(JTAG)/108 66% used
67+4(JTAG)/80 89% bonded
SLICE 75/640 11% used
Number of Signals: 285
Number of Connections: 674
<postMsg mid="61001101" type="Warning" dynamic="0" navigation="0" />
Pin Constraint Summary:
66 out of 67 pins locked (98% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 40)
PHI2_c (driver: PHI2, clk load #: 13)
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="RCLK_c" arg1="Primary" arg2="RCLK" arg3="62" arg4="Primary" />
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="PHI2_c" arg1="Primary" arg2="PHI2" arg3="8" arg4="Primary" />
The following 1 signal is selected to use the secondary clock routing resources:
nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCRAS_c" arg1="Secondary" arg2="nCRAS" arg3="17" arg4="Secondary" />
No signal is selected as Global Set/Reset.
.
Starting Placer Phase 0.
..........
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...................
Placer score = 143529.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 143450
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 3 out of 108 (2%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
PRIMARY : 2 out of 8 (25%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
Number of PIO comps: 67; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 2.5V | - |
| 1 | 20 / 21 ( 95%) | 2.5V | - |
| 2 | 17 / 20 ( 85%) | 2.5V | - |
| 3 | 17 / 20 ( 85%) | 2.5V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 3 secs
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
0 connections routed; 674 unrouted.
Starting router resource preassignment
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="RCLK_c" />
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="PHI2_c" />
<postMsg mid="66011008" type="Warning" dynamic="1" navigation="0" arg0="&#xA; Signal=nCCAS_c loads=6 clock_loads=4" />
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 05:22:14 08/15/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 05:22:14 08/15/23
Start NBR section for initial routing at 05:22:14 08/15/23
Level 1, iteration 1
2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score;
Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 6 secs
Level 2, iteration 1
11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 7 secs
Level 3, iteration 1
20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 7 secs
Level 4, iteration 1
11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 7 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 05:22:15 08/15/23
Level 1, iteration 1
7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 7 secs
Level 4, iteration 1
9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 7 secs
Level 4, iteration 2
6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 7 secs
Level 4, iteration 3
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 7 secs
Level 4, iteration 4
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 7 secs
Level 4, iteration 5
4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 7 secs
Level 4, iteration 6
3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 7 secs
Level 4, iteration 7
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 7 secs
Level 4, iteration 8
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 7 secs
Level 4, iteration 9
2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 7 secs
Level 4, iteration 10
3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 7 secs
Level 4, iteration 11
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 7 secs
Level 4, iteration 12
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 7 secs
Level 4, iteration 13
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 7 secs
Level 4, iteration 14
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 7 secs
Level 4, iteration 15
2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs
Level 4, iteration 16
3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs
Level 4, iteration 17
2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 7 secs
Level 4, iteration 18
1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 7 secs
Level 4, iteration 19
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs
Level 4, iteration 20
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs
Level 4, iteration 21
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs
Level 4, iteration 22
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 7 secs
Level 4, iteration 23
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 7 secs
Level 4, iteration 24
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 7 secs
Level 4, iteration 25
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs
Start NBR section for performance tuning (iteration 1) at 05:22:15 08/15/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 7 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs
Start NBR section for re-routing at 05:22:15 08/15/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 7 secs
Start NBR section for post-routing at 05:22:15 08/15/23
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 254 (37.69%)
Estimated worst slack<setup> : -4.650ns
Timing score<setup> : 391939
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
<postMsg mid="66011008" type="Warning" dynamic="1" navigation="0" arg0="&#xA; Signal=nCCAS_c loads=6 clock_loads=4" />
Total CPU time 6 secs
Total REAL time: 7 secs
Completely routed.
End of route. 674 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 391939
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = -4.650
PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Exiting par with exit code 0
Exiting mpartrce with exit code 0
trce -f "RAM2GS_LCMXO2_1200HC_impl1.pt" -o "RAM2GS_LCMXO2_1200HC_impl1.twr" "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf"
trce: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Tue Aug 15 05:22:16 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Design file: ram2gs_lcmxo2_1200hc_impl1.ncd
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Setup):
---------------
Timing errors: 335 Score: 391939
Cumulative negative slack: 304509
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Tue Aug 15 05:22:16 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Design file: ram2gs_lcmxo2_1200hc_impl1.ncd
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 335 (setup), 0 (hold)
Score: 391939 (setup), 0 (hold)
Cumulative negative slack: 304509 (304509+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 46 MB
iotiming "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf"
I/O Timing Report:
: version Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application iotiming from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: 4
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 5
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: 5
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 6
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: 6
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: M
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: M
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Done.
tmcheck -par "RAM2GS_LCMXO2_1200HC_impl1.par"
bitgen -f "RAM2GS_LCMXO2_1200HC_impl1.t2b" -w "RAM2GS_LCMXO2_1200HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_1200HC_impl1.prf"
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 0 Page.
Total CPU Time: 1 secs
Total REAL Time: 2 secs
Peak Memory Usage: 253 MB
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