140 lines
6.6 KiB
Plaintext
140 lines
6.6 KiB
Plaintext
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: 5
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: 6
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-1200HC
|
|
Package: TQFP100
|
|
Performance: M
|
|
Package Status: Final Version 1.44.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
// Design: RAM2GS
|
|
// Package: TQFP100
|
|
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
|
// Version: Diamond (64-bit) 3.12.1.454
|
|
// Written on Tue Aug 15 05:22:17 2023
|
|
// M: Minimum Performance Grade
|
|
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
|
|
|
I/O Timing Report (All units are in ns)
|
|
|
|
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|
|
|
// Input Setup and Hold Times
|
|
|
|
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
|
----------------------------------------------------------------------
|
|
CROW[0] nCRAS F 0.891 4 0.676 4
|
|
CROW[1] nCRAS F 0.281 4 1.216 4
|
|
Din[0] PHI2 F 7.907 4 0.089 6
|
|
Din[0] nCCAS F 1.465 4 0.158 4
|
|
Din[1] PHI2 F 7.300 4 1.026 4
|
|
Din[1] nCCAS F 1.035 4 0.527 4
|
|
Din[2] PHI2 F 6.237 4 1.467 4
|
|
Din[2] nCCAS F 1.719 4 -0.108 M
|
|
Din[3] PHI2 F 6.623 4 0.176 6
|
|
Din[3] nCCAS F 0.339 4 0.916 4
|
|
Din[4] PHI2 F 6.902 4 1.033 4
|
|
Din[4] nCCAS F 0.687 4 0.951 4
|
|
Din[5] PHI2 F 6.837 4 1.369 4
|
|
Din[5] nCCAS F 2.810 4 -0.220 M
|
|
Din[6] PHI2 F 7.648 4 -0.050 M
|
|
Din[6] nCCAS F 1.281 4 0.266 4
|
|
Din[7] PHI2 F 7.823 4 -0.159 M
|
|
Din[7] nCCAS F 1.810 4 -0.096 M
|
|
MAin[0] PHI2 F 6.751 4 -0.273 M
|
|
MAin[0] nCRAS F 1.765 4 -0.033 4
|
|
MAin[1] PHI2 F 5.718 4 0.117 M
|
|
MAin[1] nCRAS F 1.814 4 -0.051 M
|
|
MAin[2] PHI2 F 5.759 4 -0.021 M
|
|
MAin[2] nCRAS F 1.323 4 0.309 4
|
|
MAin[3] PHI2 F 6.165 4 -0.235 M
|
|
MAin[3] nCRAS F 0.694 4 0.836 4
|
|
MAin[4] PHI2 F 5.236 4 -0.147 M
|
|
MAin[4] nCRAS F 0.730 4 0.835 4
|
|
MAin[5] PHI2 F 6.024 4 0.135 M
|
|
MAin[5] nCRAS F 0.734 4 0.868 4
|
|
MAin[6] PHI2 F 5.689 4 -0.277 M
|
|
MAin[6] nCRAS F 0.288 4 1.210 4
|
|
MAin[7] PHI2 F 6.398 4 -0.307 M
|
|
MAin[7] nCRAS F 1.215 4 0.401 4
|
|
MAin[8] nCRAS F 0.817 4 0.727 4
|
|
MAin[9] nCRAS F 0.941 4 0.601 4
|
|
PHI2 RCLK R 0.771 4 1.143 4
|
|
UFMSDO RCLK R -0.238 M 2.305 4
|
|
nCCAS RCLK R 1.651 4 0.388 4
|
|
nCCAS nCRAS F 5.028 4 -0.828 M
|
|
nCRAS RCLK R 0.593 4 1.309 4
|
|
nFWE PHI2 F 5.741 4 0.781 4
|
|
nFWE nCRAS F 0.578 4 0.996 4
|
|
|
|
|
|
// Clock to Output Delay
|
|
|
|
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
|
------------------------------------------------------------------------
|
|
LED RCLK R 14.758 4 4.129 M
|
|
LED nCRAS F 12.396 4 3.434 M
|
|
RA[0] RCLK R 13.780 4 3.894 M
|
|
RA[0] nCRAS F 11.795 4 3.277 M
|
|
RA[10] RCLK R 12.425 4 3.587 M
|
|
RA[11] PHI2 R 10.432 4 3.084 M
|
|
RA[1] RCLK R 15.081 4 4.198 M
|
|
RA[1] nCRAS F 12.364 4 3.447 M
|
|
RA[2] RCLK R 14.518 4 4.082 M
|
|
RA[2] nCRAS F 11.696 4 3.275 M
|
|
RA[3] RCLK R 13.789 4 3.897 M
|
|
RA[3] nCRAS F 12.223 4 3.392 M
|
|
RA[4] RCLK R 15.175 4 4.228 M
|
|
RA[4] nCRAS F 12.424 4 3.464 M
|
|
RA[5] RCLK R 13.789 4 3.897 M
|
|
RA[5] nCRAS F 12.359 4 3.437 M
|
|
RA[6] RCLK R 15.420 4 4.299 M
|
|
RA[6] nCRAS F 12.865 4 3.560 M
|
|
RA[7] RCLK R 14.672 4 4.127 M
|
|
RA[7] nCRAS F 12.253 4 3.386 M
|
|
RA[8] RCLK R 14.952 4 4.191 M
|
|
RA[8] nCRAS F 12.244 4 3.383 M
|
|
RA[9] RCLK R 14.092 4 3.978 M
|
|
RA[9] nCRAS F 13.164 4 3.653 M
|
|
RBA[0] nCRAS F 10.278 4 2.970 M
|
|
RBA[1] nCRAS F 10.474 4 3.030 M
|
|
RCKE RCLK R 12.407 4 3.610 M
|
|
RDQMH RCLK R 13.754 4 3.857 M
|
|
RDQML RCLK R 13.482 4 3.833 M
|
|
RD[0] nCCAS F 10.515 4 3.076 M
|
|
RD[1] nCCAS F 10.118 4 2.965 M
|
|
RD[2] nCCAS F 9.759 4 2.886 M
|
|
RD[3] nCCAS F 9.798 4 2.878 M
|
|
RD[4] nCCAS F 10.979 4 3.178 M
|
|
RD[5] nCCAS F 11.063 4 3.207 M
|
|
RD[6] nCCAS F 10.317 4 3.018 M
|
|
RD[7] nCCAS F 10.232 4 2.986 M
|
|
UFMCLK RCLK R 12.402 4 3.606 M
|
|
UFMSDI RCLK R 11.975 4 3.501 M
|
|
nRCAS RCLK R 12.350 4 3.564 M
|
|
nRCS RCLK R 11.923 4 3.459 M
|
|
nRRAS RCLK R 11.995 4 3.494 M
|
|
nRWE RCLK R 11.975 4 3.501 M
|
|
nUFMCS RCLK R 11.818 4 3.434 M
|
|
WARNING: you must also run trce with hold speed: 4
|
|
WARNING: you must also run trce with hold speed: 6
|
|
WARNING: you must also run trce with setup speed: M
|