mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-26 08:49:57 +00:00
125 lines
2.8 KiB
Tcl
125 lines
2.8 KiB
Tcl
#!/usr/local/bin/wish
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proc GetPlatform {} {
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global tcl_platform
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set cpu $tcl_platform(machine)
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switch $cpu {
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intel -
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i*86* {
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set cpu ix86
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}
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x86_64 {
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if {$tcl_platform(wordSize) == 4} {
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set cpu ix86
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}
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}
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}
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switch $tcl_platform(platform) {
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windows {
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if {$cpu == "amd64"} {
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# Do not check wordSize, win32-x64 is an IL32P64 platform.
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set cpu x86_64
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}
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if {$cpu == "x86_64"} {
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return "nt64"
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} else {
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return "nt"
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}
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}
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unix {
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if {$tcl_platform(os) == "Linux"} {
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if {$cpu == "x86_64"} {
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return "lin64"
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} else {
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return "lin"
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}
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} else {
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return "sol"
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}
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}
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}
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return "nt"
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}
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set platformpath [GetPlatform]
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set Para(sbp_path) [file dirname [info script]]
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set Para(install_dir) $env(TOOLRTF)
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set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
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set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
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set Para(ModuleName) "EFB"
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set Para(Module) "EFB"
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set Para(libname) machxo2
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set Para(arch_name) xo2c00
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set Para(PartType) "LCMXO2-640HC"
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set Para(tech_syn) machxo2
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set Para(tech_cae) machxo2
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set Para(Package) "TQFP100"
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set Para(SpeedGrade) "4"
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set Para(FMax) "100"
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set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
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#create LSE project file(*.synproj)
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proc CreateSynprojFile {} {
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global Para
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if [catch {open $Para(ModuleName).synproj w} synprojFile] {
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puts "Cannot create LSE project file $Para(ModuleName).synproj."
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exit -1
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} else {
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puts $synprojFile "-a \"$Para(tech_syn)\"
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-d $Para(PartType)
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-t $Para(Package)
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-s $Para(SpeedGrade)
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-frequency 200
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-optimization_goal Balanced
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-bram_utilization 100
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-ramstyle auto
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-romstyle auto
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-use_carry_chain 1
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-carry_chain_length 0
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-force_gsr auto
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-resource_sharing 1
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-propagate_constants 1
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-remove_duplicate_regs 1
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-mux_style Auto
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-max_fanout 1000
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-fsm_encoding_style Auto
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-twr_paths 3
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-fix_gated_clocks 1
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-use_io_insertion 0
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-resolve_mixed_drivers 0
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-use_io_reg 1
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-lpf 1
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-p $Para(sbp_path)
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-ver \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\"
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\"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\"
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\"$Para(sbp_path)/$Para(ModuleName).v\"
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-top $Para(ModuleName)
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-ngo \"$Para(sbp_path)/$Para(ModuleName).ngo\"
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"
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close $synprojFile
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}
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}
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#LSE
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CreateSynprojFile
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set ldcfile "$Para(sbp_path)/$Para(ModuleName).ldc"
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set synthesis "$Para(FPGAPath)/synthesis"
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if {[file exists $ldcfile] == 0} {
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set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -gui} msg]
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} else {
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set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -sdc \"$ldcfile\" -gui} msg]
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}
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#puts $msg
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#ngdbuild
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set ngdbuild "$Para(FPGAPath)/ngdbuild"
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set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
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#puts $msg
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