mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2025-02-16 12:30:35 +00:00
77 lines
1.5 KiB
INI
77 lines
1.5 KiB
INI
[General]
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pin_sort_type=0
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pin_sort_ascending=true
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sig_sort_type=0
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sig_sort_ascending=true
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active_Sheet=Port Assignments
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[Port%20Assignments]
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Name="164,0"
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Group%20By="84,1"
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Pin="50,2"
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BANK="62,3"
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BANK_VCC="90,4"
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VREF="60,5"
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IO_TYPE="147,6"
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PULLMODE="97,7"
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DRIVE="67,8"
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SLEWRATE="92,9"
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CLAMP="71,10"
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OPENDRAIN="97,11"
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DIFFRESISTOR="114,12"
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DIFFDRIVE="92,13"
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HYSTERESIS="101,14"
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Outload%20%28pF%29="103,15"
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MaxSkew="87,16"
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Clock%20Load%20Only="121,17"
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SwitchingID="100,18"
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Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
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Power%20plane%20PCB%20noise%20%28mV%29="190,20"
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SSO%20Allowance%28%25%29="138,21"
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sort_columns="Name,Ascending"
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[Pin%20Assignments]
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Pin="90,0"
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Pad%20Name="89,1"
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Dual%20Function="158,2"
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Polarity="77,3"
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BANK="0,4"
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BANK_VCC="90,5"
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IO_TYPE="147,6"
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Signal%20Name="123,7"
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Signal%20Type="115,8"
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sort_columns="Pin,Ascending"
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[Clock%20Resource]
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Clock%20Type="100,ELLIPSIS"
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Clock%20Name="100,ELLIPSIS"
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Selection="100,ELLIPSIS"
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[Global%20Preferences]
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Preference%20Name="231,ELLIPSIS"
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Preference%20Value="236,ELLIPSIS"
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[Cell%20Mapping]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Din\Dout="100,ELLIPSIS"
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PIO%20Register="100,ELLIPSIS"
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[Route%20Priority]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Prioritize="100,ELLIPSIS"
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[Timing%20Preferences]
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Preference%20Name="129,ELLIPSIS"
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Preference%20Value="105,ELLIPSIS"
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Preference%20Unit="98,ELLIPSIS"
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[Group]
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Group%20Type\Name="134,ELLIPSIS"
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Value="39,ELLIPSIS"
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[Misc%20Preferences]
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Preference%20Name="117,ELLIPSIS"
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Preference%20Value="105,ELLIPSIS"
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