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RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html
Zane Kaminski 8cbf2f47ad RC?
2023-08-16 05:11:25 -04:00

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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO640C
Package: TQFP100
Performance: 3
Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.17.
Performance Hardware Data Status: Version 1.124.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Wed Aug 16 04:50:53 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf
Design file: ram2gs_lcmxo640c_impl1.ncd
Preference file: ram2gs_lcmxo640c_impl1.prf
Device,speed: LCMXO640C,3
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
Report: 42.550MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
Report: 115.420MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
129 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 160.663ns (weighted slack = 321.326ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[7] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 11.577ns (20.9% logic, 79.1% route), 6 logic levels.
Constraint Details:
11.577ns physical path delay SLICE_77 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 160.663ns
Physical Path Details:
Data path SLICE_77 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c)
ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7]
CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82
ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22
ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c)
--------
11.577 (20.9% logic, 79.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.013ns (weighted slack = 322.026ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[6] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 11.227ns (21.5% logic, 78.5% route), 6 logic levels.
Constraint Details:
11.227ns physical path delay SLICE_77 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 161.013ns
Physical Path Details:
Data path SLICE_77 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c)
ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6]
CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82
ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22
ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c)
--------
11.227 (21.5% logic, 78.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.212ns (weighted slack = 322.424ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[2] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 11.028ns (21.9% logic, 78.1% route), 6 logic levels.
Constraint Details:
11.028ns physical path delay SLICE_71 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 161.212ns
Physical Path Details:
Data path SLICE_71 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 SLICE_71 (from PHI2_c)
ROUTE 1 1.956 R7C4A.Q0 to R4C9B.C1 Bank[2]
CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82
ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22
ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c)
--------
11.028 (21.9% logic, 78.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_71:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C4A.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.405ns (weighted slack = 322.810ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[5] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 10.835ns (22.3% logic, 77.7% route), 6 logic levels.
Constraint Details:
10.835ns physical path delay SLICE_76 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 161.405ns
Physical Path Details:
Data path SLICE_76 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C4C.CLK to R7C4C.Q1 SLICE_76 (from PHI2_c)
ROUTE 1 1.763 R7C4C.Q1 to R4C9B.D1 Bank[5]
CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.867 R7C5D.F0 to R7C5C.C0 XOR8MEG18
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_82
ROUTE 1 2.090 R7C5C.F0 to R8C9D.D0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R8C9D.D0 to R8C9D.F0 SLICE_22
ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c)
--------
10.835 (22.3% logic, 77.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C4C.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C9D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 161.733ns (weighted slack = 323.466ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[7] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 10.416ns (19.6% logic, 80.4% route), 5 logic levels.
Constraint Details:
10.416ns physical path delay SLICE_77 to SLICE_74 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 161.733ns
Physical Path Details:
Data path SLICE_77 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c)
ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7]
CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18
CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67
ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
10.416 (19.6% logic, 80.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.083ns (weighted slack = 324.166ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[6] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 10.066ns (20.3% logic, 79.7% route), 5 logic levels.
Constraint Details:
10.066ns physical path delay SLICE_77 to SLICE_74 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 162.083ns
Physical Path Details:
Data path SLICE_77 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c)
ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6]
CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18
CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67
ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
10.066 (20.3% logic, 79.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.194ns (weighted slack = 324.388ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[7] (from PHI2_c +)
Destination: FF Data in CmdUFMCS (to PHI2_c -)
FF CmdUFMCLK
Delay: 9.955ns (20.5% logic, 79.5% route), 5 logic levels.
Constraint Details:
9.955ns physical path delay SLICE_77 to SLICE_73 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 162.194ns
Physical Path Details:
Data path SLICE_77 to SLICE_73:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q1 SLICE_77 (from PHI2_c)
ROUTE 1 2.505 R7C2B.Q1 to R4C9B.A1 Bank[7]
CTOF_DEL --- 0.371 R4C9B.A1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18
CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67
ROUTE 2 1.178 R7C5D.F1 to R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
9.955 (20.5% logic, 79.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C8A.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.282ns (weighted slack = 324.564ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[2] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 9.867ns (20.7% logic, 79.3% route), 5 logic levels.
Constraint Details:
9.867ns physical path delay SLICE_71 to SLICE_74 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 162.282ns
Physical Path Details:
Data path SLICE_71 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C4A.CLK to R7C4A.Q0 SLICE_71 (from PHI2_c)
ROUTE 1 1.956 R7C4A.Q0 to R4C9B.C1 Bank[2]
CTOF_DEL --- 0.371 R4C9B.C1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18
CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67
ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
9.867 (20.7% logic, 79.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_71:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C4A.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.475ns (weighted slack = 324.950ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[5] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 9.674ns (21.1% logic, 78.9% route), 5 logic levels.
Constraint Details:
9.674ns physical path delay SLICE_76 to SLICE_74 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 162.475ns
Physical Path Details:
Data path SLICE_76 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C4C.CLK to R7C4C.Q1 SLICE_76 (from PHI2_c)
ROUTE 1 1.763 R7C4C.Q1 to R4C9B.D1 Bank[5]
CTOF_DEL --- 0.371 R4C9B.D1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18
CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67
ROUTE 2 1.639 R7C5D.F1 to R8C7D.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
9.674 (21.1% logic, 78.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C4C.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R8C7D.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.544ns (weighted slack = 325.088ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[6] (from PHI2_c +)
Destination: FF Data in CmdUFMCS (to PHI2_c -)
FF CmdUFMCLK
Delay: 9.605ns (21.3% logic, 78.7% route), 5 logic levels.
Constraint Details:
9.605ns physical path delay SLICE_77 to SLICE_73 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 162.544ns
Physical Path Details:
Data path SLICE_77 to SLICE_73:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R7C2B.CLK to R7C2B.Q0 SLICE_77 (from PHI2_c)
ROUTE 1 2.155 R7C2B.Q0 to R4C9B.B1 Bank[6]
CTOF_DEL --- 0.371 R4C9B.B1 to R4C9B.F1 SLICE_56
ROUTE 1 2.155 R4C9B.F1 to R7C2A.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R7C2A.B1 to R7C2A.F1 SLICE_70
ROUTE 6 1.545 R7C2A.F1 to R7C5D.A0 N_147
CTOF_DEL --- 0.371 R7C5D.A0 to R7C5D.F0 SLICE_67
ROUTE 5 0.528 R7C5D.F0 to R7C5D.C1 XOR8MEG18
CTOF_DEL --- 0.371 R7C5D.C1 to R7C5D.F1 SLICE_67
ROUTE 2 1.178 R7C5D.F1 to R7C8A.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
9.605 (21.3% logic, 78.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C2B.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.682 39.PADDI to R7C8A.CLK PHI2_c
--------
3.682 (0.0% logic, 100.0% route), 0 logic levels.
Report: 42.550MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 342.328ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 400.000MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 342.328ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 400.000MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
388 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.336ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.420ns (28.7% logic, 71.3% route), 6 logic levels.
Constraint Details:
8.420ns physical path delay SLICE_2 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.336ns
Physical Path Details:
Data path SLICE_2 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15]
CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8
CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68
ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c)
--------
8.420 (28.7% logic, 71.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.414ns (28.7% logic, 71.3% route), 6 logic levels.
Constraint Details:
8.414ns physical path delay SLICE_2 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.342ns
Physical Path Details:
Data path SLICE_2 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15]
CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8
CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69
ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c)
--------
8.414 (28.7% logic, 71.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.396ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.360ns (28.9% logic, 71.1% route), 6 logic levels.
Constraint Details:
8.360ns physical path delay SLICE_3 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.396ns
Physical Path Details:
Data path SLICE_3 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13]
CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8
CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68
ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c)
--------
8.360 (28.9% logic, 71.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.402ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.354ns (28.9% logic, 71.1% route), 6 logic levels.
Constraint Details:
8.354ns physical path delay SLICE_3 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.402ns
Physical Path Details:
Data path SLICE_3 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13]
CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8
CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69
ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c)
--------
8.354 (28.9% logic, 71.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.475ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in UFMSDI (to RCLK_c +)
Delay: 8.344ns (28.9% logic, 71.1% route), 6 logic levels.
Constraint Details:
8.344ns physical path delay SLICE_2 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 7.475ns
Physical Path Details:
Data path SLICE_2 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 1.571 R8C5D.Q1 to R7C6A.B1 FS[15]
CTOF_DEL --- 0.371 R7C6A.B1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151
CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87
ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1
CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52
ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
--------
8.344 (28.9% logic, 71.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.535ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in UFMSDI (to RCLK_c +)
Delay: 8.284ns (29.2% logic, 70.8% route), 6 logic levels.
Constraint Details:
8.284ns physical path delay SLICE_3 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 7.535ns
Physical Path Details:
Data path SLICE_3 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 1.511 R8C5C.Q1 to R7C6A.A1 FS[13]
CTOF_DEL --- 0.371 R7C6A.A1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151
CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87
ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1
CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52
ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
--------
8.284 (29.2% logic, 70.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.721ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.035ns (30.1% logic, 69.9% route), 6 logic levels.
Constraint Details:
8.035ns physical path delay SLICE_2 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.721ns
Physical Path Details:
Data path SLICE_2 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c)
ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14]
CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8
CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68
ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c)
--------
8.035 (30.1% logic, 69.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.727ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.029ns (30.1% logic, 69.9% route), 6 logic levels.
Constraint Details:
8.029ns physical path delay SLICE_2 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.727ns
Physical Path Details:
Data path SLICE_2 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c)
ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14]
CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.716 R8C7B.F0 to R8C6B.D0 N_137_8
CTOF_DEL --- 0.371 R8C6B.D0 to R8C6B.F0 SLICE_69
ROUTE 1 1.260 R8C6B.F0 to R9C9B.CE N_33 (to RCLK_c)
--------
8.029 (30.1% logic, 69.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R9C9B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.860ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in UFMSDI (to RCLK_c +)
Delay: 7.959ns (30.3% logic, 69.7% route), 6 logic levels.
Constraint Details:
7.959ns physical path delay SLICE_2 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 7.860ns
Physical Path Details:
Data path SLICE_2 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C5D.CLK to R8C5D.Q0 SLICE_2 (from RCLK_c)
ROUTE 3 1.186 R8C5D.Q0 to R7C6A.D1 FS[14]
CTOF_DEL --- 0.371 R7C6A.D1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.919 R7C6B.F1 to R8C7B.B1 N_151
CTOF_DEL --- 0.371 R8C7B.B1 to R8C7B.F1 SLICE_87
ROUTE 1 1.156 R8C7B.F1 to R9C9C.D0 UFMSDI_r_xx_mm_1
CTOF_DEL --- 0.371 R9C9C.D0 to R9C9C.F0 SLICE_52
ROUTE 1 0.000 R9C9C.F0 to R9C9C.DI0 UFMSDI_RNO (to RCLK_c)
--------
7.959 (30.3% logic, 69.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C5D.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R9C9C.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.998ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 7.758ns (31.1% logic, 68.9% route), 6 logic levels.
Constraint Details:
7.758ns physical path delay SLICE_1 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.998ns
Physical Path Details:
Data path SLICE_1 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C6A.CLK to R8C6A.Q1 SLICE_1 (from RCLK_c)
ROUTE 3 0.909 R8C6A.Q1 to R7C6A.C1 FS[17]
CTOF_DEL --- 0.371 R7C6A.C1 to R7C6A.F1 SLICE_81
ROUTE 1 0.626 R7C6A.F1 to R7C6D.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C6D.D1 to R7C6D.F1 SLICE_72
ROUTE 4 0.657 R7C6D.F1 to R7C6B.D1 N_51
CTOF_DEL --- 0.371 R7C6B.D1 to R7C6B.F1 SLICE_58
ROUTE 2 1.169 R7C6B.F1 to R8C7B.D0 N_151
CTOF_DEL --- 0.371 R8C7B.D0 to R8C7B.F0 SLICE_87
ROUTE 2 0.909 R8C7B.F0 to R8C6C.C0 N_137_8
CTOF_DEL --- 0.371 R8C6C.C0 to R8C6C.F0 SLICE_68
ROUTE 1 1.073 R8C6C.F0 to R7C6B.CE N_31 (to RCLK_c)
--------
7.758 (31.1% logic, 68.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R8C6A.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.425 86.PADDI to R7C6B.CLK RCLK_c
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Report: 115.420MHz is the maximum frequency for this preference.
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 42.550 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 115.420 MHz| 6
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 10
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 8
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 32
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Wed Aug 16 04:50:53 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf
Design file: ram2gs_lcmxo640c_impl1.ncd
Preference file: ram2gs_lcmxo640c_impl1.prf
Device,speed: LCMXO640C,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
129 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.358ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.339ns (62.2% logic, 37.8% route), 2 logic levels.
Constraint Details:
0.339ns physical path delay SLICE_9 to SLICE_9 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.358ns
Physical Path Details:
Data path SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C2A.CLK to R6C2A.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.128 R6C2A.Q0 to R6C2A.D0 ADSubmitted
CTOF_DEL --- 0.074 R6C2A.D0 to R6C2A.F0 SLICE_9
ROUTE 1 0.000 R6C2A.F0 to R6C2A.DI0 ADSubmitted_r (to PHI2_c)
--------
0.339 (62.2% logic, 37.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.361ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels.
Constraint Details:
0.342ns physical path delay SLICE_14 to SLICE_14 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.361ns
Physical Path Details:
Data path SLICE_14 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R7C3C.CLK to R7C3C.Q0 SLICE_14 (from PHI2_c)
ROUTE 2 0.131 R7C3C.Q0 to R7C3C.A0 C1Submitted
CTOF_DEL --- 0.074 R7C3C.A0 to R7C3C.F0 SLICE_14
ROUTE 1 0.000 R7C3C.F0 to R7C3C.DI0 C1Submitted_RNO (to PHI2_c)
--------
0.342 (61.7% logic, 38.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.364ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdSubmitted (from PHI2_c -)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 0.345ns (61.2% logic, 38.8% route), 2 logic levels.
Constraint Details:
0.345ns physical path delay SLICE_22 to SLICE_22 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.364ns
Physical Path Details:
Data path SLICE_22 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R8C9D.CLK to R8C9D.Q0 SLICE_22 (from PHI2_c)
ROUTE 3 0.134 R8C9D.Q0 to R8C9D.A0 CmdSubmitted
CTOF_DEL --- 0.074 R8C9D.A0 to R8C9D.F0 SLICE_22
ROUTE 1 0.000 R8C9D.F0 to R8C9D.DI0 N_460_0 (to PHI2_c)
--------
0.345 (61.2% logic, 38.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R8C9D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R8C9D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.411ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.392ns (65.8% logic, 34.2% route), 2 logic levels.
Constraint Details:
0.392ns physical path delay SLICE_20 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.411ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.134 R6C2D.Q0 to R6C2D.D1 CmdEnable
CTOOFX_DEL --- 0.121 R6C2D.D1 to R6C2D.OFX0 SLICE_20
ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c)
--------
0.392 (65.8% logic, 34.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.415ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.396ns (66.2% logic, 33.8% route), 2 logic levels.
Constraint Details:
0.396ns physical path delay SLICE_20 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.415ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.134 R6C2D.Q0 to R6C2D.A0 CmdEnable
CTOOFX_DEL --- 0.125 R6C2D.A0 to R6C2D.OFX0 SLICE_20
ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c)
--------
0.396 (66.2% logic, 33.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.452ns (57.1% logic, 42.9% route), 2 logic levels.
Constraint Details:
0.452ns physical path delay SLICE_9 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.471ns
Physical Path Details:
Data path SLICE_9 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C2A.CLK to R6C2A.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.194 R6C2A.Q0 to R6C2D.A1 ADSubmitted
CTOOFX_DEL --- 0.121 R6C2D.A1 to R6C2D.OFX0 SLICE_20
ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c)
--------
0.452 (57.1% logic, 42.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2A.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.611ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Cmdn8MEGEN (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 0.592ns (48.1% logic, 51.9% route), 3 logic levels.
Constraint Details:
0.592ns physical path delay SLICE_26 to SLICE_26 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.611ns
Physical Path Details:
Data path SLICE_26 to SLICE_26:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R7C5B.CLK to R7C5B.Q0 SLICE_26 (from PHI2_c)
ROUTE 2 0.208 R7C5B.Q0 to R7C5B.B1 Cmdn8MEGEN
CTOF_DEL --- 0.074 R7C5B.B1 to R7C5B.F1 SLICE_26
ROUTE 1 0.099 R7C5B.F1 to R7C5B.C0 Cmdn8MEGEN_4_u_i_0
CTOF_DEL --- 0.074 R7C5B.C0 to R7C5B.F0 SLICE_26
ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 N_19_i (to PHI2_c)
--------
0.592 (48.1% logic, 51.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_26:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C5B.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_26:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C5B.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.634ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.615ns (42.6% logic, 57.4% route), 2 logic levels.
Constraint Details:
0.615ns physical path delay SLICE_14 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.634ns
Physical Path Details:
Data path SLICE_14 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R7C3C.CLK to R7C3C.Q0 SLICE_14 (from PHI2_c)
ROUTE 2 0.353 R7C3C.Q0 to R6C2D.C0 C1Submitted
CTOOFX_DEL --- 0.125 R6C2D.C0 to R6C2D.OFX0 SLICE_20
ROUTE 1 0.000 R6C2D.OFX0 to R6C2D.DI0 CmdEnable_s (to PHI2_c)
--------
0.615 (42.6% logic, 57.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C3C.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.665ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdLEDEN (from PHI2_c -)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 0.646ns (44.1% logic, 55.9% route), 3 logic levels.
Constraint Details:
0.646ns physical path delay SLICE_21 to SLICE_21 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.665ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R7C5A.CLK to R7C5A.Q0 SLICE_21 (from PHI2_c)
ROUTE 2 0.169 R7C5A.Q0 to R7C5C.C1 CmdLEDEN
CTOF_DEL --- 0.074 R7C5C.C1 to R7C5C.F1 SLICE_82
ROUTE 1 0.192 R7C5C.F1 to R7C5A.A0 N_132
CTOF_DEL --- 0.074 R7C5A.A0 to R7C5A.F0 SLICE_21
ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 N_21_i (to PHI2_c)
--------
0.646 (44.1% logic, 55.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.723ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 0.700ns (30.1% logic, 69.9% route), 2 logic levels.
Constraint Details:
0.700ns physical path delay SLICE_20 to SLICE_21 meets
-0.023ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.023ns) by 0.723ns
Physical Path Details:
Data path SLICE_20 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C2D.CLK to R6C2D.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.348 R6C2D.Q0 to R7C5D.B0 CmdEnable
CTOF_DEL --- 0.074 R7C5D.B0 to R7C5D.F0 SLICE_67
ROUTE 5 0.141 R7C5D.F0 to R7C5A.CE XOR8MEG18 (to PHI2_c)
--------
0.700 (30.1% logic, 69.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R6C2D.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.907 39.PADDI to R7C5A.CLK PHI2_c
--------
0.907 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
388 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.273ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels.
Constraint Details:
0.256ns physical path delay SLICE_75 to SLICE_75 meets
-0.017ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.017ns) by 0.273ns
Physical Path Details:
Data path SLICE_75 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c)
ROUTE 1 0.130 R7C4B.Q0 to R7C4B.M1 CASr (to RCLK_c)
--------
0.256 (49.2% logic, 50.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R7C4B.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R7C4B.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in FS[17] (to RCLK_c +)
FF FS[16]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_1 to SLICE_1 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C6A.CLK to R8C6A.Q1 SLICE_1 (from RCLK_c)
ROUTE 3 0.131 R8C6A.Q1 to R8C6A.A1 FS[17] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C6A.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C6A.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in FS_cry_0[14] (to RCLK_c +)
FF FS[15]
FF FS[14]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_2 to SLICE_2 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C5D.CLK to R8C5D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 0.131 R8C5D.Q1 to R8C5D.A1 FS[15] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5D.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5D.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in FS_cry_0[12] (to RCLK_c +)
FF FS[13]
FF FS[12]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_3 to SLICE_3 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C5C.CLK to R8C5C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 0.131 R8C5C.Q1 to R8C5C.A1 FS[13] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5C.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5C.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[5] (from RCLK_c +)
Destination: FF Data in FS_cry_0[4] (to RCLK_c +)
FF FS[5]
FF FS[4]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_7 to SLICE_7 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_7 to SLICE_7:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C4C.CLK to R8C4C.Q1 SLICE_7 (from RCLK_c)
ROUTE 4 0.131 R8C4C.Q1 to R8C4C.A1 FS[5] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4C.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4C.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[3] (from RCLK_c +)
Destination: FF Data in FS_cry_0[2] (to RCLK_c +)
FF FS[3]
FF FS[2]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_8 to SLICE_8 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_8 to SLICE_8:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C4B.CLK to R8C4B.Q1 SLICE_8 (from RCLK_c)
ROUTE 3 0.131 R8C4B.Q1 to R8C4B.A1 FS[3] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4B.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4B.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from RCLK_c +)
Destination: FF Data in FS_cry_0[0] (to RCLK_c +)
FF FS[1]
FF FS[0]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_0 to SLICE_0 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_0 (from RCLK_c)
ROUTE 3 0.131 R8C4A.Q0 to R8C4A.A0 FS[0] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4A.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4A.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[10] (from RCLK_c +)
Destination: FF Data in FS_cry_0[10] (to RCLK_c +)
FF FS[11]
FF FS[10]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_4 to SLICE_4 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C5B.CLK to R8C5B.Q0 SLICE_4 (from RCLK_c)
ROUTE 5 0.131 R8C5B.Q0 to R8C5B.A0 FS[10] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5B.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5B.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[8] (from RCLK_c +)
Destination: FF Data in FS_cry_0[8] (to RCLK_c +)
FF FS[9]
FF FS[8]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_5 to SLICE_5 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C5A.CLK to R8C5A.Q0 SLICE_5 (from RCLK_c)
ROUTE 3 0.131 R8C5A.Q0 to R8C5A.A0 FS[8] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5A.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C5A.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[6] (from RCLK_c +)
Destination: FF Data in FS_cry_0[6] (to RCLK_c +)
FF FS[7]
FF FS[6]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_6 to SLICE_6 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_6 to SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C4D.CLK to R8C4D.Q0 SLICE_6 (from RCLK_c)
ROUTE 3 0.131 R8C4D.Q0 to R8C4D.A0 FS[6] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4D.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.351 86.PADDI to R8C4D.CLK RCLK_c
--------
0.351 (0.0% logic, 100.0% route), 0 logic levels.
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 10
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 8
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 32
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 517 paths, 4 nets, and 421 connections (66.51% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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