469 lines
20 KiB
Plaintext
469 lines
20 KiB
Plaintext
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Lattice Mapping Report File for Design Module 'RAM2GS'
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Design Information
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------------------
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Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
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RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
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RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
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c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_s
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ynplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
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-msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
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Target Vendor: LATTICE
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Target Device: LCMXO2-1200HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
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Mapped on: 10/19/23 23:50:56
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Design Summary
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--------------
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Number of registers: 110 out of 1520 (7%)
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PFU registers: 85 out of 1280 (7%)
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PIO registers: 25 out of 240 (10%)
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Number of SLICEs: 115 out of 640 (18%)
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SLICEs as Logic/ROM: 115 out of 640 (18%)
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SLICEs as RAM: 0 out of 480 (0%)
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SLICEs as Carry: 10 out of 640 (2%)
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Number of LUT4s: 229 out of 1280 (18%)
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Number used as logic LUTs: 209
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Number used as distributed RAM: 0
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Number used as ripple logic: 20
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Number used as shift registers: 0
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Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
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Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
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Number of IDDR cells: 0
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Number of ODDR cells: 1
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Number of TDDR cells: 0
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Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
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Number of PIO using IDDR only: 0 (0 differential)
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Number of PIO using ODDR only: 1 (0 differential)
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Number of PIO using TDDR only: 0 (0 differential)
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Number of PIO using IDDR/ODDR: 0 (0 differential)
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Number of PIO using IDDR/TDDR: 0 (0 differential)
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Number of PIO using ODDR/TDDR: 0 (0 differential)
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Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
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Number of block RAMs: 0 out of 7 (0%)
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Number of GSRs: 0 out of 1 (0%)
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EFB used : Yes
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JTAG used : No
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Readback used : No
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Oscillator used : No
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Startup used : No
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POR : On
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Bandgap : On
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Number of Power Controller: 0 out of 1 (0%)
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
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Number of DCCA: 0 out of 8 (0%)
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Number of DCMA: 0 out of 2 (0%)
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Number of PLLs: 0 out of 1 (0%)
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Page 1
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Design: RAM2GS Date: 10/19/23 23:50:56
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Design Summary (cont)
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---------------------
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Number of DQSDLLs: 0 out of 2 (0%)
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Number of CLKDIVC: 0 out of 4 (0%)
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Number of ECLKSYNCA: 0 out of 4 (0%)
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Number of ECLKBRIDGECS: 0 out of 2 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 4
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Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
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Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
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Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
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Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
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Number of Clock Enables: 5
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Net N_103: 1 loads, 1 LSLICEs
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Net XOR8MEG18: 5 loads, 5 LSLICEs
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Net N_122: 9 loads, 9 LSLICEs
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Net N_244_i: 2 loads, 2 LSLICEs
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Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
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Number of LSRs: 5
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Net RA10s_i: 1 loads, 0 LSLICEs
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Net wb_rst10: 3 loads, 3 LSLICEs
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Net wb_rst: 1 loads, 0 LSLICEs
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Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
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Net RASr2: 2 loads, 2 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net InitReady: 31 loads
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Net FS[12]: 23 loads
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Net FS[13]: 23 loads
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Net FS[11]: 21 loads
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Net N_132: 20 loads
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Net FS[14]: 18 loads
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Net FS[10]: 16 loads
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Net FS[9]: 14 loads
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Net Ready: 14 loads
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Net Ready_fast: 14 loads
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Number of warnings: 1
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Number of errors: 0
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Design Errors/Warnings
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----------------------
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WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
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temporarily disable certain features of the device including Power
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Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
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Functionality is restored after the Flash Memory (UFM/Configuration)
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Interface is disabled using Disable Configuration Interface command 0x26
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followed by Bypass command 0xFF.
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Page 2
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Design: RAM2GS Date: 10/19/23 23:50:56
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IO (PIO) Attributes
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-------------------
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| RD[0] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| Dout[0] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| PHI2 | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| RDQML | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RDQMH | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nRCAS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRRAS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRWE | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RCKE | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RCLKout | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RCLK | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nRCS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[7] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[6] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[5] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[4] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[3] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[2] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[1] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[11] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[10] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[9] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[8] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[7] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[6] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[5] | OUTPUT | LVCMOS33 | |
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Page 3
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Design: RAM2GS Date: 10/19/23 23:50:56
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| RA[4] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[3] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[2] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[1] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[0] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RBA[1] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RBA[0] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| LED | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nFWE | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nCRAS | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nCCAS | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[7] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[6] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[5] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[4] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[3] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[2] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[1] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Din[7] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[6] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[5] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[4] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[3] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[2] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[1] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[0] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| CROW[1] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| CROW[0] | INPUT | LVCMOS33 | |
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Page 4
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Design: RAM2GS Date: 10/19/23 23:50:56
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| MAin[9] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[8] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[7] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[6] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[5] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[4] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[3] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[2] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[1] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[0] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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Removed logic
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-------------
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Block GSR_INST undriven or does not drive anything - clipped.
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Signal nCRAS_c_i was merged into signal nCRAS_c
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Signal RASr2_i was merged into signal RASr2
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Signal XOR8MEG.CN was merged into signal PHI2_c
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Signal ufmefb/VCC undriven or does not drive anything - clipped.
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Signal ufmefb/GND undriven or does not drive anything - clipped.
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Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
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Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
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Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
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Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
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Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
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Signal ufmefb/TCOC undriven or does not drive anything - clipped.
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Signal ufmefb/TCINT undriven or does not drive anything - clipped.
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Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
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Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
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Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
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Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
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Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
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Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
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Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
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Page 5
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Design: RAM2GS Date: 10/19/23 23:50:56
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Removed logic (cont)
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--------------------
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Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
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Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
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Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
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Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
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Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
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Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
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Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
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Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
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Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
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Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
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Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
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Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
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Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
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Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
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Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
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Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
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Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
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Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
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Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
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Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
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Signal N_1 undriven or does not drive anything - clipped.
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Block nCRAS_pad_RNIBPVB was optimized away.
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Block RASr2_RNIAFR1 was optimized away.
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Block XOR8MEG.CN was optimized away.
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Block ufmefb/VCC was optimized away.
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Block ufmefb/GND was optimized away.
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Embedded Functional Block Connection Summary
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--------------------------------------------
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Desired WISHBONE clock frequency: 66.7 MHz
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Clock source: RCLK_c
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Reset source: wb_rst
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Functions mode:
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I2C #1 (Primary) Function: DISABLED
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I2C #2 (Secondary) Function: DISABLED
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SPI Function: DISABLED
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Timer/Counter Function: DISABLED
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Timer/Counter Mode: WB
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UFM Connection: ENABLED
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PLL0 Connection: DISABLED
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Page 6
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Design: RAM2GS Date: 10/19/23 23:50:56
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Embedded Functional Block Connection Summary (cont)
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---------------------------------------------------
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PLL1 Connection: DISABLED
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I2C Function Summary:
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--------------------
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None
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SPI Function Summary:
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--------------------
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None
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Timer/Counter Function Summary:
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------------------------------
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None
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UFM Function Summary:
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--------------------
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UFM Utilization: General Purpose Flash Memory
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Initialized UFM Pages: 321 Pages (321*128 Bits)
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Available General
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Purpose Flash Memory: 511 Pages (511*128 Bits)
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EBR Blocks with Unique
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Initialization Data: 0
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WID EBR Instance
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--- ------------
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ASIC Components
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---------------
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Instance Name: ufmefb/EFBInst_0
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Type: EFB
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Run Time and Memory Usage
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 63 MB
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Page 7
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
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reserved.
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