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RAM2GS/CPLD-old/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
Mon Aug 16 21:32:34 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,3
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>PERIOD NET "PHI2_c" 350.000000 ns (0 errors)</A></LI> 113 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_1' Target='right'>PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_2' Target='right'>PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_3' Target='right'>PERIOD NET "RCLK_c" 16.000000 ns (0 errors)</A></LI> 395 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_4' Target='right'>CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_5' Target='right'>CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_6' Target='right'>CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_7' Target='right'>CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_8' Target='right'>CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_9' Target='right'>CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_10' Target='right'>CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_11' Target='right'>CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_12' Target='right'>CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_13' Target='right'>CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_14' Target='right'>CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_15' Target='right'>CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_16' Target='right'>CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_17' Target='right'>CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_18' Target='right'>CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_19' Target='right'>CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_20' Target='right'>CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_21' Target='right'>CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_22' Target='right'>CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_23' Target='right'>CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_24' Target='right'>CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_25' Target='right'>CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_26' Target='right'>CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_27' Target='right'>CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_28' Target='right'>CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_29' Target='right'>CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_30' Target='right'>CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_31' Target='right'>CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_32' Target='right'>CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_33' Target='right'>CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_34' Target='right'>CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_35' Target='right'>CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_36' Target='right'>CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_37' Target='right'>CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_38' Target='right'>CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_39' Target='right'>CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_0_40' Target='right'>CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
113 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 161.925ns (weighted slack = 323.850ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i0 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 12.810ns (21.7% logic, 78.3% route), 7 logic levels.
Constraint Details:
12.810ns physical path delay SLICE_94 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 161.925ns
Physical Path Details:
Data path SLICE_94 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c)
ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0
CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
12.810 (21.7% logic, 78.3% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.080ns (weighted slack = 324.160ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i6 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 12.655ns (22.0% logic, 78.0% route), 7 logic levels.
Constraint Details:
12.655ns physical path delay SLICE_95 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.080ns
Physical Path Details:
Data path SLICE_95 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c)
ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6
CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
12.655 (22.0% logic, 78.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.409ns (weighted slack = 324.818ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i0 (from PHI2_c +)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 12.326ns (22.6% logic, 77.4% route), 7 logic levels.
Constraint Details:
12.326ns physical path delay SLICE_94 to SLICE_19 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.409ns
Physical Path Details:
Data path SLICE_94 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c)
ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0
CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90
ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
12.326 (22.6% logic, 77.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.416ns (weighted slack = 324.832ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i0 (from PHI2_c +)
Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -)
Delay: 12.319ns (22.6% logic, 77.4% route), 7 logic levels.
Constraint Details:
12.319ns physical path delay SLICE_94 to SLICE_88 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.416ns
Physical Path Details:
Data path SLICE_94 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c)
ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0
CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
12.319 (22.6% logic, 77.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.564ns (weighted slack = 325.128ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i6 (from PHI2_c +)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 12.171ns (22.9% logic, 77.1% route), 7 logic levels.
Constraint Details:
12.171ns physical path delay SLICE_95 to SLICE_19 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.564ns
Physical Path Details:
Data path SLICE_95 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c)
ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6
CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4D.A0 to R4C4D.F0 SLICE_90
ROUTE 2 1.550 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
12.171 (22.9% logic, 77.1% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C5A.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.571ns (weighted slack = 325.142ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i6 (from PHI2_c +)
Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -)
Delay: 12.164ns (22.9% logic, 77.1% route), 7 logic levels.
Constraint Details:
12.164ns physical path delay SLICE_95 to SLICE_88 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.571ns
Physical Path Details:
Data path SLICE_95 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 SLICE_95 (from PHI2_c)
ROUTE 1 1.488 R2C2C.Q0 to R5C2C.A0 Bank_6
CTOF_DEL --- 0.371 R5C2C.A0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 1.543 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
12.164 (22.9% logic, 77.1% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C4A.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.606ns (weighted slack = 325.212ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i7 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 12.129ns (23.0% logic, 77.0% route), 7 logic levels.
Constraint Details:
12.129ns physical path delay SLICE_95 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.606ns
Physical Path Details:
Data path SLICE_95 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q1 SLICE_95 (from PHI2_c)
ROUTE 1 1.155 R2C2C.Q1 to R5C2B.D1 Bank_7
CTOF_DEL --- 0.371 R5C2B.D1 to R5C2B.F1 SLICE_67
ROUTE 1 0.304 R5C2B.F1 to R5C2C.D1 n2154
CTOF_DEL --- 0.371 R5C2C.D1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
12.129 (23.0% logic, 77.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C2C.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.635ns (weighted slack = 325.270ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i1 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 12.100ns (20.0% logic, 80.0% route), 6 logic levels.
Constraint Details:
12.100ns physical path delay SLICE_94 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.635ns
Physical Path Details:
Data path SLICE_94 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q1 SLICE_94 (from PHI2_c)
ROUTE 1 1.905 R2C3B.Q1 to R6C2B.C1 Bank_1
CTOF_DEL --- 0.371 R6C2B.C1 to R6C2B.F1 SLICE_97
ROUTE 1 1.444 R6C2B.F1 to R5C5B.C1 n2170
CTOF_DEL --- 0.371 R5C5B.C1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
12.100 (20.0% logic, 80.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.868ns (weighted slack = 325.736ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i5 (from PHI2_c +)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 11.867ns (23.5% logic, 76.5% route), 7 logic levels.
Constraint Details:
11.867ns physical path delay SLICE_97 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.868ns
Physical Path Details:
Data path SLICE_97 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C2B.CLK to R6C2B.Q1 SLICE_97 (from PHI2_c)
ROUTE 1 0.700 R6C2B.Q1 to R5C2C.D0 Bank_5
CTOF_DEL --- 0.371 R5C2C.D0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 2.034 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
11.867 (23.5% logic, 76.5% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R6C2B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R5C4B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.886ns (weighted slack = 325.772ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i0 (from PHI2_c +)
Destination: FF Data in XOR8MEG_381 (to PHI2_c -)
Delay: 11.849ns (23.5% logic, 76.5% route), 7 logic levels.
Constraint Details:
11.849ns physical path delay SLICE_94 to SLICE_96 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 162.886ns
Physical Path Details:
Data path SLICE_94 to SLICE_96:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C3B.CLK to R2C3B.Q0 SLICE_94 (from PHI2_c)
ROUTE 1 1.643 R2C3B.Q0 to R5C2C.B0 Bank_0
CTOF_DEL --- 0.371 R5C2C.B0 to R5C2C.F0 SLICE_82
ROUTE 1 0.497 R5C2C.F0 to R5C2C.C1 n2166
CTOF_DEL --- 0.371 R5C2C.C1 to R5C2C.F1 SLICE_82
ROUTE 1 1.548 R5C2C.F1 to R5C5B.B1 n26
CTOF_DEL --- 0.371 R5C5B.B1 to R5C5B.F1 SLICE_76
ROUTE 4 1.750 R5C5B.F1 to R6C3A.D0 n1285
CTOF_DEL --- 0.371 R6C3A.D0 to R6C3A.F0 SLICE_89
ROUTE 3 1.048 R6C3A.F0 to R5C3C.A1 n2290
CTOF_DEL --- 0.371 R5C3C.A1 to R5C3C.F1 SLICE_18
ROUTE 3 1.504 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112
CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_90
ROUTE 1 1.073 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
--------
11.849 (23.5% logic, 76.5% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R2C3B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.911 39.PADDI to R3C4B.CLK PHI2_c
--------
3.911 (0.0% logic, 100.0% route), 0 logic levels.
Report: 26.150ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK SLICE_76
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK SLICE_77
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
395 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.566ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i15 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 8.190ns (29.5% logic, 70.5% route), 6 logic levels.
Constraint Details:
8.190ns physical path delay SLICE_7 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.566ns
Physical Path Details:
Data path SLICE_7 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c)
ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15
CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119
CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75
ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
--------
8.190 (29.5% logic, 70.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.590ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i15 (from RCLK_c +)
Destination: FF Data in n8MEGEN_391 (to RCLK_c +)
Delay: 8.166ns (29.6% logic, 70.4% route), 6 logic levels.
Constraint Details:
8.166ns physical path delay SLICE_7 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.590ns
Physical Path Details:
Data path SLICE_7 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c)
ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15
CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119
CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33
ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
--------
8.166 (29.6% logic, 70.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.984ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i13 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 7.772ns (31.1% logic, 68.9% route), 6 logic levels.
Constraint Details:
7.772ns physical path delay SLICE_8 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.984ns
Physical Path Details:
Data path SLICE_8 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c)
ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13
CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119
CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75
ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
--------
7.772 (31.1% logic, 68.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.008ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i13 (from RCLK_c +)
Destination: FF Data in n8MEGEN_391 (to RCLK_c +)
Delay: 7.748ns (31.2% logic, 68.8% route), 6 logic levels.
Constraint Details:
7.748ns physical path delay SLICE_8 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.008ns
Physical Path Details:
Data path SLICE_8 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q1 SLICE_8 (from RCLK_c)
ROUTE 3 1.511 R8C4C.Q1 to R7C5C.A0 FS_13
CTOF_DEL --- 0.371 R7C5C.A0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119
CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33
ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
--------
7.748 (31.2% logic, 68.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.123ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i12 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 7.633ns (31.6% logic, 68.4% route), 6 logic levels.
Constraint Details:
7.633ns physical path delay SLICE_8 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.123ns
Physical Path Details:
Data path SLICE_8 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c)
ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119
CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75
ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
--------
7.633 (31.6% logic, 68.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.147ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i12 (from RCLK_c +)
Destination: FF Data in n8MEGEN_391 (to RCLK_c +)
Delay: 7.609ns (31.7% logic, 68.3% route), 6 logic levels.
Constraint Details:
7.609ns physical path delay SLICE_8 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.147ns
Physical Path Details:
Data path SLICE_8 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4C.CLK to R8C4C.Q0 SLICE_8 (from RCLK_c)
ROUTE 3 1.372 R8C4C.Q0 to R7C5C.C0 FS_12
CTOF_DEL --- 0.371 R7C5C.C0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119
CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33
ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
--------
7.609 (31.7% logic, 68.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.262ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i15 (from RCLK_c +)
Destination: FF Data in UFMCLK_389 (to RCLK_c +)
Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels.
Constraint Details:
7.112ns physical path delay SLICE_7 to SLICE_42 meets
16.000ns delay constraint less
0.000ns skew and
0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
Physical Path Details:
Data path SLICE_7 to SLICE_42:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c)
ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15
CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300
CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86
ROUTE 2 1.538 R6C4A.F0 to R7C5A.LSR n2291 (to RCLK_c)
--------
7.112 (23.5% logic, 76.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_42:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R7C5A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.262ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i15 (from RCLK_c +)
Destination: FF Data in UFMSDI_390 (to RCLK_c +)
Delay: 7.112ns (23.5% logic, 76.5% route), 4 logic levels.
Constraint Details:
7.112ns physical path delay SLICE_7 to SLICE_43 meets
16.000ns delay constraint less
0.000ns skew and
0.626ns LSR_SET requirement (totaling 15.374ns) by 8.262ns
Physical Path Details:
Data path SLICE_7 to SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q1 SLICE_7 (from RCLK_c)
ROUTE 3 1.929 R8C4D.Q1 to R7C5C.B0 FS_15
CTOF_DEL --- 0.371 R7C5C.B0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.915 R7C4A.F1 to R6C4A.C0 n2300
CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_86
ROUTE 2 1.538 R6C4A.F0 to R7C5B.LSR n2291 (to RCLK_c)
--------
7.112 (23.5% logic, 76.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_43:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R7C5B.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.316ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i14 (from RCLK_c +)
Destination: FF Data in LEDEN_392 (to RCLK_c +)
Delay: 7.440ns (32.5% logic, 67.5% route), 6 logic levels.
Constraint Details:
7.440ns physical path delay SLICE_7 to SLICE_89 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.316ns
Physical Path Details:
Data path SLICE_7 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c)
ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14
CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 0.513 R7C4B.F0 to R7C4B.C1 n2119
CTOF_DEL --- 0.371 R7C4B.C1 to R7C4B.F1 SLICE_75
ROUTE 1 1.260 R7C4B.F1 to R6C3A.CE RCLK_c_enable_25 (to RCLK_c)
--------
7.440 (32.5% logic, 67.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C3A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.340ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS_577__i14 (from RCLK_c +)
Destination: FF Data in n8MEGEN_391 (to RCLK_c +)
Delay: 7.416ns (32.6% logic, 67.4% route), 6 logic levels.
Constraint Details:
7.416ns physical path delay SLICE_7 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.340ns
Physical Path Details:
Data path SLICE_7 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4D.CLK to R8C4D.Q0 SLICE_7 (from RCLK_c)
ROUTE 3 1.179 R8C4D.Q0 to R7C5C.D0 FS_14
CTOF_DEL --- 0.371 R7C5C.D0 to R7C5C.F0 SLICE_78
ROUTE 3 1.057 R7C5C.F0 to R7C4A.A1 n10
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_73
ROUTE 4 0.712 R7C4A.F1 to R7C4A.B0 n2300
CTOF_DEL --- 0.371 R7C4A.B0 to R7C4A.F0 SLICE_73
ROUTE 1 0.304 R7C4A.F0 to R7C4B.D0 n11
CTOF_DEL --- 0.371 R7C4B.D0 to R7C4B.F0 SLICE_75
ROUTE 2 1.102 R7C4B.F0 to R6C4C.B1 n2119
CTOF_DEL --- 0.371 R6C4C.B1 to R6C4C.F1 SLICE_33
ROUTE 1 0.647 R6C4C.F1 to R6C4B.CE RCLK_c_enable_7 (to RCLK_c)
--------
7.416 (32.6% logic, 67.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R8C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.353 86.PADDI to R6C4B.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Report: 8.434ns is the minimum period for this preference.
================================================================================
<A name="par_twr_pref_0_4"></A>Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_5"></A>Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_6"></A>Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_7"></A>Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_8"></A>Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_9"></A>Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_10"></A>Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_11"></A>Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_12"></A>Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_13"></A>Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_14"></A>Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_15"></A>Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_16"></A>Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.904ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_373 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 6.180ns (67.9% logic, 32.1% route), 2 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_55 and
6.180ns delay SLICE_55 to RA[10] (totaling 8.596ns) meets
12.500ns offset RCLK to RA[10] by 3.904ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C4B.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 1.984 R2C4B.Q0 to 87.PADDO n980
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10]
--------
6.180 (67.9% logic, 32.1% route), 2 logic levels.
Report: 8.596ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_17"></A>Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.734ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
6.350ns delay SLICE_64 to RA[9] (totaling 8.766ns) meets
12.500ns offset RCLK to RA[9] by 3.734ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C1 nRowColSel
CTOF_DEL --- 0.371 R2C4A.C1 to R2C4A.F1 SLICE_88
ROUTE 1 0.817 R2C4A.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9]
--------
6.350 (71.9% logic, 28.1% route), 3 logic levels.
Report: 8.766ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_18"></A>Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.604ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 6.480ns (70.5% logic, 29.5% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
6.480ns delay SLICE_64 to RA[8] (totaling 8.896ns) meets
12.500ns offset RCLK to RA[8] by 3.604ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B0 nRowColSel
CTOF_DEL --- 0.371 R2C2C.B0 to R2C2C.F0 SLICE_95
ROUTE 1 0.817 R2C2C.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8]
--------
6.480 (70.5% logic, 29.5% route), 3 logic levels.
Report: 8.896ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_19"></A>Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.245ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 7.839ns (58.3% logic, 41.7% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.839ns delay SLICE_64 to RA[7] (totaling 10.255ns) meets
12.500ns offset RCLK to RA[7] by 2.245ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.234 R2C2A.Q0 to R6C2B.D0 nRowColSel
CTOF_DEL --- 0.371 R6C2B.D0 to R6C2B.F0 SLICE_97
ROUTE 1 2.038 R6C2B.F0 to 100.PADDO RA_c_7
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7]
--------
7.839 (58.3% logic, 41.7% route), 3 logic levels.
Report: 10.255ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_20"></A>Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.499ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 7.585ns (60.2% logic, 39.8% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.585ns delay SLICE_64 to RA[6] (totaling 10.001ns) meets
12.500ns offset RCLK to RA[6] by 2.499ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C0 nRowColSel
CTOF_DEL --- 0.371 R3C2A.C0 to R3C2A.F0 SLICE_98
ROUTE 1 2.052 R3C2A.F0 to 91.PADDO RA_c_6
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6]
--------
7.585 (60.2% logic, 39.8% route), 3 logic levels.
Report: 10.001ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_21"></A>Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.891ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 7.193ns (63.5% logic, 36.5% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.193ns delay SLICE_64 to RA[5] (totaling 9.609ns) meets
12.500ns offset RCLK to RA[5] by 2.891ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.966 R2C2A.Q0 to R3C2A.C1 nRowColSel
CTOF_DEL --- 0.371 R3C2A.C1 to R3C2A.F1 SLICE_98
ROUTE 1 1.660 R3C2A.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5]
--------
7.193 (63.5% logic, 36.5% route), 3 logic levels.
Report: 9.609ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_22"></A>Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.996ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 6.088ns (75.0% logic, 25.0% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
6.088ns delay SLICE_64 to RA[4] (totaling 8.504ns) meets
12.500ns offset RCLK to RA[4] by 3.996ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.704 R2C2A.Q0 to R2C2A.D1 nRowColSel
CTOF_DEL --- 0.371 R2C2A.D1 to R2C2A.F1 SLICE_64
ROUTE 1 0.817 R2C2A.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4]
--------
6.088 (75.0% logic, 25.0% route), 3 logic levels.
Report: 8.504ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_23"></A>Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.567ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 7.517ns (60.8% logic, 39.2% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.517ns delay SLICE_64 to RA[3] (totaling 9.933ns) meets
12.500ns offset RCLK to RA[3] by 2.567ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C1 nRowColSel
CTOF_DEL --- 0.371 R2C3B.C1 to R2C3B.F1 SLICE_94
ROUTE 1 1.984 R2C3B.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3]
--------
7.517 (60.8% logic, 39.2% route), 3 logic levels.
Report: 9.933ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_24"></A>Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.438ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 7.646ns (59.7% logic, 40.3% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.646ns delay SLICE_64 to RA[2] (totaling 10.062ns) meets
12.500ns offset RCLK to RA[2] by 2.438ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.096 R2C2A.Q0 to R2C2C.B1 nRowColSel
CTOF_DEL --- 0.371 R2C2C.B1 to R2C2C.F1 SLICE_95
ROUTE 1 1.983 R2C2C.F1 to 94.PADDO RA_c_2
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2]
--------
7.646 (59.7% logic, 40.3% route), 3 logic levels.
Report: 10.062ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_25"></A>Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.734ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 6.350ns (71.9% logic, 28.1% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
6.350ns delay SLICE_64 to RA[1] (totaling 8.766ns) meets
12.500ns offset RCLK to RA[1] by 3.734ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.966 R2C2A.Q0 to R2C3B.C0 nRowColSel
CTOF_DEL --- 0.371 R2C3B.C0 to R2C3B.F0 SLICE_94
ROUTE 1 0.817 R2C3B.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1]
--------
6.350 (71.9% logic, 28.1% route), 3 logic levels.
Report: 8.766ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_26"></A>Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.826ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 7.258ns (62.9% logic, 37.1% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.258ns delay SLICE_64 to RA[0] (totaling 9.674ns) meets
12.500ns offset RCLK to RA[0] by 2.826ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 1.165 R2C2A.Q0 to R3C2B.B1 nRowColSel
CTOF_DEL --- 0.371 R3C2B.B1 to R3C2B.F1 SLICE_92
ROUTE 1 1.526 R3C2B.F1 to 98.PADDO RA_c_0
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0]
--------
7.258 (62.9% logic, 37.1% route), 3 logic levels.
Report: 9.674ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_27"></A>Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_369 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_60 and
5.013ns delay SLICE_60 to nRCS (totaling 7.429ns) meets
12.500ns offset RCLK to nRCS by 5.071ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C5B.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 0.817 R2C5B.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.429ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_28"></A>Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.420ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_368 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 6.664ns (63.0% logic, 37.0% route), 2 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_34 and
6.664ns delay SLICE_34 to RCKE (totaling 9.080ns) meets
12.500ns offset RCLK to RCKE by 3.420ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R5C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 2.468 R5C2A.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE
--------
6.664 (63.0% logic, 37.0% route), 2 logic levels.
Report: 9.080ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_29"></A>Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_372 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_63 and
5.013ns delay SLICE_63 to nRWE (totaling 7.429ns) meets
12.500ns offset RCLK to nRWE by 5.071ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R3C5B.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 0.817 R3C5B.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.429ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_30"></A>Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.885ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 6.199ns (67.7% logic, 32.3% route), 2 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_61 and
6.199ns delay SLICE_61 to nRRAS (totaling 8.615ns) meets
12.500ns offset RCLK to nRRAS by 3.885ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R4C5A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 2.003 R4C5A.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS
--------
6.199 (67.7% logic, 32.3% route), 2 logic levels.
Report: 8.615ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_31"></A>Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.905ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_371 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 6.179ns (67.9% logic, 32.1% route), 2 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_58 and
6.179ns delay SLICE_58 to nRCAS (totaling 8.595ns) meets
12.500ns offset RCLK to nRCAS by 3.905ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C4C.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 1.983 R2C4C.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS
--------
6.179 (67.9% logic, 32.1% route), 2 logic levels.
Report: 8.595ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_32"></A>Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.025ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 7.059ns (64.7% logic, 35.3% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
7.059ns delay SLICE_64 to RDQMH (totaling 9.475ns) meets
12.500ns offset RCLK to RDQMH by 3.025ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.966 R2C2A.Q0 to R2C4A.C0 nRowColSel
CTOF_DEL --- 0.371 R2C4A.C0 to R2C4A.F0 SLICE_88
ROUTE 1 1.526 R2C4A.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH
--------
7.059 (64.7% logic, 35.3% route), 3 logic levels.
Report: 9.475ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_33"></A>Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.023ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 8.061ns (56.7% logic, 43.3% route), 3 logic levels.
Clock Path Delay: 2.416ns (44.0% logic, 56.0% route), 1 logic levels.
Constraint Details:
2.416ns delay RCLK to SLICE_64 and
8.061ns delay SLICE_64 to RDQML (totaling 10.477ns) meets
12.500ns offset RCLK to RDQML by 2.023ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
ROUTE 39 1.353 86.PADDI to R2C2A.CLK RCLK_c
--------
2.416 (44.0% logic, 56.0% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.954 R2C2A.Q0 to R3C2B.C0 nRowColSel
CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_92
ROUTE 1 2.540 R3C2B.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML
--------
8.061 (56.7% logic, 43.3% route), 3 logic levels.
Report: 10.477ns is the minimum offset for this preference.
================================================================================
<A name="par_twr_pref_0_34"></A>Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_35"></A>Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_36"></A>Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_37"></A>Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_38"></A>Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_39"></A>Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_40"></A>Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.150 ns| 7
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 8.434 ns| 6
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.596 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.896 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.255 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.001 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.609 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.504 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.933 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.062 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.766 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.674 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.080 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 7.429 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.615 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 8.595 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.475 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.477 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
Mon Aug 16 21:32:34 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>PERIOD NET "PHI2_c" 350.000000 ns (0 errors)</A></LI> 113 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>PERIOD NET "RCLK_c" 16.000000 ns (0 errors)</A></LI> 395 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_4' Target='right'>CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_5' Target='right'>CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_6' Target='right'>CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_7' Target='right'>CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_8' Target='right'>CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_9' Target='right'>CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_10' Target='right'>CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_11' Target='right'>CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_12' Target='right'>CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_13' Target='right'>CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_14' Target='right'>CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_15' Target='right'>CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_16' Target='right'>CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_17' Target='right'>CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_18' Target='right'>CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_19' Target='right'>CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_20' Target='right'>CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_21' Target='right'>CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_22' Target='right'>CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_23' Target='right'>CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_24' Target='right'>CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_25' Target='right'>CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_26' Target='right'>CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_27' Target='right'>CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_28' Target='right'>CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_29' Target='right'>CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_30' Target='right'>CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_31' Target='right'>CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_32' Target='right'>CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_33' Target='right'>CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_34' Target='right'>CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_35' Target='right'>CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_36' Target='right'>CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_37' Target='right'>CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_38' Target='right'>CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_39' Target='right'>CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_40' Target='right'>CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
113 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.444ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_380 (from PHI2_c -)
Destination: FF Data in ADSubmitted_380 (to PHI2_c -)
Delay: 0.421ns (62.2% logic, 37.8% route), 2 logic levels.
Constraint Details:
0.421ns physical path delay SLICE_9 to SLICE_9 meets
-0.023ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.023ns) by 0.444ns
Physical Path Details:
Data path SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D0 ADSubmitted
CTOF_DEL --- 0.092 R5C3A.D0 to R5C3A.F0 SLICE_9
ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 n1361 (to PHI2_c)
--------
0.421 (62.2% logic, 37.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.186ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN_383 (to PHI2_c -)
Delay: 1.157ns (30.6% logic, 69.4% route), 3 logic levels.
Constraint Details:
1.157ns physical path delay SLICE_18 to SLICE_23 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.186ns
Physical Path Details:
Data path SLICE_18 to SLICE_23:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable
CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18
ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90
ROUTE 2 0.167 R4C4D.F0 to R4C4C.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
1.157 (30.6% logic, 69.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R4C4C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.193ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted_379 (from PHI2_c -)
Destination: FF Data in CmdEnable_378 (to PHI2_c -)
Delay: 1.164ns (38.3% logic, 61.7% route), 4 logic levels.
Constraint Details:
1.164ns physical path delay SLICE_14 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.193ns
Physical Path Details:
Data path SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C3B.CLK to R6C3B.Q0 SLICE_14 (from PHI2_c)
ROUTE 1 0.253 R6C3B.Q0 to R6C3B.B1 C1Submitted
CTOF_DEL --- 0.092 R6C3B.B1 to R6C3B.F1 SLICE_14
ROUTE 1 0.075 R6C3B.F1 to R6C3C.D1 n2098
CTOF_DEL --- 0.092 R6C3C.D1 to R6C3C.F1 SLICE_77
ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286
CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77
ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
--------
1.164 (38.3% logic, 61.7% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.280ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted_380 (from PHI2_c -)
Destination: FF Data in CmdEnable_378 (to PHI2_c -)
Delay: 1.251ns (35.7% logic, 64.3% route), 4 logic levels.
Constraint Details:
1.251ns physical path delay SLICE_9 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.280ns
Physical Path Details:
Data path SLICE_9 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3A.CLK to R5C3A.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.159 R5C3A.Q0 to R5C3A.D1 ADSubmitted
CTOF_DEL --- 0.092 R5C3A.D1 to R5C3A.F1 SLICE_9
ROUTE 1 0.256 R5C3A.F1 to R6C3C.A1 n2080
CTOF_DEL --- 0.092 R6C3C.A1 to R6C3C.F1 SLICE_77
ROUTE 1 0.123 R6C3C.F1 to R6C3C.C0 n2286
CTOF_DEL --- 0.092 R6C3C.C0 to R6C3C.F0 SLICE_77
ROUTE 1 0.267 R6C3C.F0 to R5C3C.CE PHI2_N_114_enable_8 (to PHI2_c)
--------
1.251 (35.7% logic, 64.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.286ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in XOR8MEG_381 (to PHI2_c -)
Delay: 1.257ns (28.2% logic, 71.8% route), 3 logic levels.
Constraint Details:
1.257ns physical path delay SLICE_18 to SLICE_96 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.286ns
Physical Path Details:
Data path SLICE_18 to SLICE_96:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable
CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18
ROUTE 3 0.383 R5C3C.F1 to R4C4D.A1 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C4D.A1 to R4C4D.F1 SLICE_90
ROUTE 1 0.267 R4C4D.F1 to R3C4B.CE PHI2_N_114_enable_2 (to PHI2_c)
--------
1.257 (28.2% logic, 71.8% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.400ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in CmdUFMSDI_387 (to PHI2_c -)
Delay: 1.371ns (25.8% logic, 74.2% route), 3 logic levels.
Constraint Details:
1.371ns physical path delay SLICE_18 to SLICE_88 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.400ns
Physical Path Details:
Data path SLICE_18 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable
CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18
ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 0.381 R4C4A.F0 to R2C4A.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
1.371 (25.8% logic, 74.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R2C4A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.414ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
Delay: 1.385ns (25.6% logic, 74.4% route), 3 logic levels.
Constraint Details:
1.385ns physical path delay SLICE_18 to SLICE_19 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.414ns
Physical Path Details:
Data path SLICE_18 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable
CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18
ROUTE 3 0.383 R5C3C.F1 to R4C4D.A0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C4D.A0 to R4C4D.F0 SLICE_90
ROUTE 2 0.395 R4C4D.F0 to R5C5A.CE PHI2_N_114_enable_6 (to PHI2_c)
--------
1.385 (25.6% logic, 74.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C5A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.537ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable_378 (from PHI2_c -)
Destination: FF Data in CmdUFMCS_385 (to PHI2_c -)
FF CmdUFMCLK_386
Delay: 1.508ns (23.5% logic, 76.5% route), 3 logic levels.
Constraint Details:
1.508ns physical path delay SLICE_18 to SLICE_83 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.537ns
Physical Path Details:
Data path SLICE_18 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R5C3C.CLK to R5C3C.Q0 SLICE_18 (from PHI2_c)
ROUTE 1 0.253 R5C3C.Q0 to R5C3C.B1 CmdEnable
CTOF_DEL --- 0.092 R5C3C.B1 to R5C3C.F1 SLICE_18
ROUTE 3 0.383 R5C3C.F1 to R4C4A.A0 XOR8MEG_N_112
CTOF_DEL --- 0.092 R4C4A.A0 to R4C4A.F0 SLICE_72
ROUTE 2 0.518 R4C4A.F0 to R5C4B.CE PHI2_N_114_enable_7 (to PHI2_c)
--------
1.508 (23.5% logic, 76.5% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C3C.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R5C4B.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 175.681ns (weighted slack = 351.362ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG_381 (from PHI2_c -)
Destination: FF Data in RA11_358 (to PHI2_c +)
Delay: 0.670ns (39.1% logic, 60.9% route), 2 logic levels.
Constraint Details:
0.670ns physical path delay SLICE_96 to SLICE_31 meets
-0.011ns DIN_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.011ns) by 175.681ns
Physical Path Details:
Data path SLICE_96 to SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R3C4B.CLK to R3C4B.Q0 SLICE_96 (from PHI2_c)
ROUTE 1 0.408 R3C4B.Q0 to R2C5A.D0 XOR8MEG
CTOF_DEL --- 0.092 R2C5A.D0 to R2C5A.F0 SLICE_31
ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_180 (to PHI2_c)
--------
0.670 (39.1% logic, 60.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R3C4B.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R2C5A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 176.485ns (weighted slack = 352.970ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_i3 (from PHI2_c +)
Destination: FF Data in C1Submitted_379 (to PHI2_c -)
Delay: 1.456ns (23.4% logic, 76.6% route), 3 logic levels.
Constraint Details:
1.456ns physical path delay SLICE_98 to SLICE_14 meets
-0.029ns CE_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.029ns) by 176.485ns
Physical Path Details:
Data path SLICE_98 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C2A.CLK to R3C2A.Q1 SLICE_98 (from PHI2_c)
ROUTE 1 0.495 R3C2A.Q1 to R5C5B.A1 Bank_3
CTOF_DEL --- 0.092 R5C5B.A1 to R5C5B.F1 SLICE_76
ROUTE 4 0.459 R5C5B.F1 to R6C3A.D1 n1285
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 SLICE_89
ROUTE 1 0.161 R6C3A.F1 to R6C3B.CE PHI2_N_114_enable_1 (to PHI2_c)
--------
1.456 (23.4% logic, 76.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_98:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R3C2A.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.196 39.PADDI to R6C3B.CLK PHI2_c
--------
1.196 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
395 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i11 (from RCLK_c +)
Destination: FF Data in IS_FSM__i12 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_72 to SLICE_72 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_72 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q0 SLICE_72 (from RCLK_c)
ROUTE 1 0.161 R4C4A.Q0 to R4C4A.M1 n702 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i12 (from RCLK_c +)
Destination: FF Data in IS_FSM__i13 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_72 to SLICE_90 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_72 to SLICE_90:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C4A.CLK to R4C4A.Q1 SLICE_72 (from RCLK_c)
ROUTE 1 0.161 R4C4A.Q1 to R4C4D.M0 n701 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i7 (from RCLK_c +)
Destination: FF Data in IS_FSM__i8 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_73 to SLICE_73 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_73 to SLICE_73:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C4A.CLK to R7C4A.Q0 SLICE_73 (from RCLK_c)
ROUTE 1 0.161 R7C4A.Q0 to R7C4A.M1 n706 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i3 (from RCLK_c +)
Destination: FF Data in IS_FSM__i4 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_74 to SLICE_74 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_74 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C3B.CLK to R5C3B.Q0 SLICE_74 (from RCLK_c)
ROUTE 1 0.161 R5C3B.Q0 to R5C3B.M1 n710 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i6 (from RCLK_c +)
Destination: FF Data in IS_FSM__i7 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_75 to SLICE_73 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_75 to SLICE_73:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q1 SLICE_75 (from RCLK_c)
ROUTE 1 0.161 R7C4B.Q1 to R7C4A.M0 n707 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_73:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i5 (from RCLK_c +)
Destination: FF Data in IS_FSM__i6 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_75 to SLICE_75 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_75 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C4B.CLK to R7C4B.Q0 SLICE_75 (from RCLK_c)
ROUTE 1 0.161 R7C4B.Q0 to R7C4B.M1 n708 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C4B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i10 (from RCLK_c +)
Destination: FF Data in IS_FSM__i11 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_84 to SLICE_72 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_84 to SLICE_72:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C4B.CLK to R4C4B.Q1 SLICE_84 (from RCLK_c)
ROUTE 1 0.161 R4C4B.Q1 to R4C4A.M0 n703 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4A.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i2 (from RCLK_c +)
Destination: FF Data in IS_FSM__i3 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_87 to SLICE_74 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_87 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C3D.CLK to R5C3D.Q1 SLICE_87 (from RCLK_c)
ROUTE 1 0.161 R5C3D.Q1 to R5C3B.M0 n711 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_87:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C3D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R5C3B.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS_FSM__i13 (from RCLK_c +)
Destination: FF Data in IS_FSM__i14 (to RCLK_c +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_90 to SLICE_90 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
Data path SLICE_90 to SLICE_90:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C4D.CLK to R4C4D.Q0 SLICE_90 (from RCLK_c)
ROUTE 1 0.161 R4C4D.Q0 to R4C4D.M1 n700 (to RCLK_c)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R4C4D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.345ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2_353 (from RCLK_c +)
Destination: FF Data in RASr3_354 (to RCLK_c +)
Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.324ns physical path delay SLICE_93 to SLICE_93 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.345ns
Physical Path Details:
Data path SLICE_93 to SLICE_93:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C5D.CLK to R7C5D.Q0 SLICE_93 (from RCLK_c)
ROUTE 16 0.167 R7C5D.Q0 to R7C5D.M1 RASr2 (to RCLK_c)
--------
0.324 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_93:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_93:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413 86.PADDI to R7C5D.CLK RCLK_c
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_4"></A>Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_5"></A>Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_6"></A>Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_7"></A>Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_8"></A>Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_9"></A>Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_10"></A>Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_11"></A>Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_12"></A>Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_13"></A>Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_14"></A>Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_15"></A>Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_16"></A>Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.220ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RA10_373 (from RCLK_c +)
Destination: Port Pad RA[10]
Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_55 and
1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
0.000ns hold offset RCLK to RA[10] by 2.220ns
Physical Path Details:
Clock path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C4B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4B.CLK to R2C4B.Q0 SLICE_55 (from RCLK_c)
ROUTE 1 0.468 R2C4B.Q0 to 87.PADDO n980
DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10]
--------
1.733 (73.0% logic, 27.0% route), 2 logic levels.
Report: 2.220ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_17"></A>Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.284ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[9]
Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.797ns delay SLICE_64 to RA[9] (totaling 2.284ns) meets
0.000ns hold offset RCLK to RA[9] by 2.284ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C1 nRowColSel
CTOF_DEL --- 0.092 R2C4A.C1 to R2C4A.F1 SLICE_88
ROUTE 1 0.197 R2C4A.F1 to 85.PADDO RA_c_9
DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9]
--------
1.797 (75.5% logic, 24.5% route), 3 logic levels.
Report: 2.284ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_18"></A>Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.316ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[8]
Data Path Delay: 1.829ns (74.2% logic, 25.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.829ns delay SLICE_64 to RA[8] (totaling 2.316ns) meets
0.000ns hold offset RCLK to RA[8] by 2.316ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B0 nRowColSel
CTOF_DEL --- 0.092 R2C2C.B0 to R2C2C.F0 SLICE_95
ROUTE 1 0.197 R2C2C.F0 to 96.PADDO RA_c_8
DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8]
--------
1.829 (74.2% logic, 25.8% route), 3 logic levels.
Report: 2.316ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_19"></A>Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.652ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[7]
Data Path Delay: 2.165ns (62.7% logic, 37.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.165ns delay SLICE_64 to RA[7] (totaling 2.652ns) meets
0.000ns hold offset RCLK to RA[7] by 2.652ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.319 R2C2A.Q0 to R6C2B.D0 nRowColSel
CTOF_DEL --- 0.092 R6C2B.D0 to R6C2B.F0 SLICE_97
ROUTE 1 0.489 R6C2B.F0 to 100.PADDO RA_c_7
DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7]
--------
2.165 (62.7% logic, 37.3% route), 3 logic levels.
Report: 2.652ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_20"></A>Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.579ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[6]
Data Path Delay: 2.092ns (64.9% logic, 35.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.092ns delay SLICE_64 to RA[6] (totaling 2.579ns) meets
0.000ns hold offset RCLK to RA[6] by 2.579ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C0 nRowColSel
CTOF_DEL --- 0.092 R3C2A.C0 to R3C2A.F0 SLICE_98
ROUTE 1 0.492 R3C2A.F0 to 91.PADDO RA_c_6
DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6]
--------
2.092 (64.9% logic, 35.1% route), 3 logic levels.
Report: 2.579ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_21"></A>Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.481ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[5]
Data Path Delay: 1.994ns (68.1% logic, 31.9% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.994ns delay SLICE_64 to RA[5] (totaling 2.481ns) meets
0.000ns hold offset RCLK to RA[5] by 2.481ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.243 R2C2A.Q0 to R3C2A.C1 nRowColSel
CTOF_DEL --- 0.092 R3C2A.C1 to R3C2A.F1 SLICE_98
ROUTE 1 0.394 R3C2A.F1 to 95.PADDO RA_c_5
DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5]
--------
1.994 (68.1% logic, 31.9% route), 3 logic levels.
Report: 2.481ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_22"></A>Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.219ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[4]
Data Path Delay: 1.732ns (78.3% logic, 21.7% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.732ns delay SLICE_64 to RA[4] (totaling 2.219ns) meets
0.000ns hold offset RCLK to RA[4] by 2.219ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.178 R2C2A.Q0 to R2C2A.D1 nRowColSel
CTOF_DEL --- 0.092 R2C2A.D1 to R2C2A.F1 SLICE_64
ROUTE 1 0.197 R2C2A.F1 to 99.PADDO RA_c_4
DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4]
--------
1.732 (78.3% logic, 21.7% route), 3 logic levels.
Report: 2.219ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_23"></A>Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.555ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[3]
Data Path Delay: 2.068ns (65.6% logic, 34.4% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.068ns delay SLICE_64 to RA[3] (totaling 2.555ns) meets
0.000ns hold offset RCLK to RA[3] by 2.555ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C1 nRowColSel
CTOF_DEL --- 0.092 R2C3B.C1 to R2C3B.F1 SLICE_94
ROUTE 1 0.468 R2C3B.F1 to 97.PADDO RA_c_3
DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3]
--------
2.068 (65.6% logic, 34.4% route), 3 logic levels.
Report: 2.555ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_24"></A>Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.599ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[2]
Data Path Delay: 2.112ns (64.3% logic, 35.7% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.112ns delay SLICE_64 to RA[2] (totaling 2.599ns) meets
0.000ns hold offset RCLK to RA[2] by 2.599ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.275 R2C2A.Q0 to R2C2C.B1 nRowColSel
CTOF_DEL --- 0.092 R2C2C.B1 to R2C2C.F1 SLICE_95
ROUTE 1 0.480 R2C2C.F1 to 94.PADDO RA_c_2
DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2]
--------
2.112 (64.3% logic, 35.7% route), 3 logic levels.
Report: 2.599ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_25"></A>Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.284ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[1]
Data Path Delay: 1.797ns (75.5% logic, 24.5% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.797ns delay SLICE_64 to RA[1] (totaling 2.284ns) meets
0.000ns hold offset RCLK to RA[1] by 2.284ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.243 R2C2A.Q0 to R2C3B.C0 nRowColSel
CTOF_DEL --- 0.092 R2C3B.C0 to R2C3B.F0 SLICE_94
ROUTE 1 0.197 R2C3B.F0 to 89.PADDO RA_c_1
DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1]
--------
1.797 (75.5% logic, 24.5% route), 3 logic levels.
Report: 2.284ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_26"></A>Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RA[0]
Data Path Delay: 2.005ns (67.7% logic, 32.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.005ns delay SLICE_64 to RA[0] (totaling 2.492ns) meets
0.000ns hold offset RCLK to RA[0] by 2.492ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.292 R2C2A.Q0 to R3C2B.B1 nRowColSel
CTOF_DEL --- 0.092 R3C2B.B1 to R3C2B.F1 SLICE_92
ROUTE 1 0.356 R3C2B.F1 to 98.PADDO RA_c_0
DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0]
--------
2.005 (67.7% logic, 32.3% route), 3 logic levels.
Report: 2.492ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_27"></A>Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCS_369 (from RCLK_c +)
Destination: Port Pad nRCS
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_60 and
1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRCS by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C5B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 SLICE_60 (from RCLK_c)
ROUTE 1 0.197 R2C5B.Q0 to 77.PADDO nRCS_c
DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_28"></A>Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.363ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RCKE_368 (from RCLK_c +)
Destination: Port Pad RCKE
Data Path Delay: 1.876ns (67.4% logic, 32.6% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_34 and
1.876ns delay SLICE_34 to RCKE (totaling 2.363ns) meets
0.000ns hold offset RCLK to RCKE by 2.363ns
Physical Path Details:
Clock path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R5C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C2A.CLK to R5C2A.Q0 SLICE_34 (from RCLK_c)
ROUTE 4 0.611 R5C2A.Q0 to 82.PADDO RCKE_c
DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE
--------
1.876 (67.4% logic, 32.6% route), 2 logic levels.
Report: 2.363ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_29"></A>Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRWE_372 (from RCLK_c +)
Destination: Port Pad nRWE
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_63 and
1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRWE by 1.949ns
Physical Path Details:
Clock path RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R3C5B.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5B.CLK to R3C5B.Q0 SLICE_63 (from RCLK_c)
ROUTE 1 0.197 R3C5B.Q0 to 72.PADDO nRWE_c
DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_30"></A>Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.236ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRRAS_370 (from RCLK_c +)
Destination: Port Pad nRRAS
Data Path Delay: 1.749ns (72.3% logic, 27.7% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_61 and
1.749ns delay SLICE_61 to nRRAS (totaling 2.236ns) meets
0.000ns hold offset RCLK to nRRAS by 2.236ns
Physical Path Details:
Clock path RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R4C5A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C5A.CLK to R4C5A.Q0 SLICE_61 (from RCLK_c)
ROUTE 2 0.484 R4C5A.Q0 to 73.PADDO nRRAS_c
DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS
--------
1.749 (72.3% logic, 27.7% route), 2 logic levels.
Report: 2.236ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_31"></A>Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.232ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRCAS_371 (from RCLK_c +)
Destination: Port Pad nRCAS
Data Path Delay: 1.745ns (72.5% logic, 27.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_58 and
1.745ns delay SLICE_58 to nRCAS (totaling 2.232ns) meets
0.000ns hold offset RCLK to nRCAS by 2.232ns
Physical Path Details:
Clock path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C4C.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4C.CLK to R2C4C.Q0 SLICE_58 (from RCLK_c)
ROUTE 1 0.480 R2C4C.Q0 to 78.PADDO nRCAS_c
DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS
--------
1.745 (72.5% logic, 27.5% route), 2 logic levels.
Report: 2.232ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_32"></A>Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.443ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQMH
Data Path Delay: 1.956ns (69.4% logic, 30.6% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.956ns delay SLICE_64 to RDQMH (totaling 2.443ns) meets
0.000ns hold offset RCLK to RDQMH by 2.443ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.243 R2C2A.Q0 to R2C4A.C0 nRowColSel
CTOF_DEL --- 0.092 R2C4A.C0 to R2C4A.F0 SLICE_88
ROUTE 1 0.356 R2C4A.F0 to 76.PADDO RDQMH_c
DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH
--------
1.956 (69.4% logic, 30.6% route), 3 logic levels.
Report: 2.443ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_33"></A>Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.713ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nRowColSel_375 (from RCLK_c +)
Destination: Port Pad RDQML
Data Path Delay: 2.226ns (61.0% logic, 39.0% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.226ns delay SLICE_64 to RDQML (totaling 2.713ns) meets
0.000ns hold offset RCLK to RDQML by 2.713ns
Physical Path Details:
Clock path RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
ROUTE 39 0.223 86.PADDI to R2C2A.CLK RCLK_c
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
Data path SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C2A.CLK to R2C2A.Q0 SLICE_64 (from RCLK_c)
ROUTE 13 0.238 R2C2A.Q0 to R3C2B.C0 nRowColSel
CTOF_DEL --- 0.092 R3C2B.C0 to R3C2B.F0 SLICE_92
ROUTE 1 0.631 R3C2B.F0 to 61.PADDO RDQML_c
DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML
--------
2.226 (61.0% logic, 39.0% route), 3 logic levels.
Report: 2.713ns is the maximum offset for this preference.
================================================================================
<A name="par_twr_pref_1_34"></A>Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_35"></A>Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_36"></A>Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_37"></A>Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_38"></A>Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_39"></A>Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_40"></A>Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.316 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.652 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.579 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.481 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.219 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.555 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.599 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.284 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.492 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.363 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.236 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.232 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.443 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.713 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 526 paths, 6 nets, and 440 connections (71.20% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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