mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-12-11 13:49:28 +00:00
89 lines
3.9 KiB
Plaintext
89 lines
3.9 KiB
Plaintext
PERIOD NET "PHI2_c" 350.000000 ns ;
|
|
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
|
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
|
PERIOD NET "RCLK_c" 15.000000 ns ;
|
|
BLOCK RESETPATHS ;
|
|
BLOCK ASYNCPATHS ;
|
|
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
|
|
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
|
|
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
|
|
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
|
|
OUTPUT PORT "LED" LOAD 25.000000 pF ;
|
|
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
|
|
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
|
|
VOLTAGE 3.300 V;
|
|
VCCIO_DERATE BANK 0 PERCENT -5;
|
|
VCCIO_DERATE PERCENT -5;
|
|
VCCIO_DERATE BANK 1 PERCENT -5;
|
|
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
|