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203 lines
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203 lines
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<HEAD><TITLE>I/O Timing Report</TITLE>
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body,pre{
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font-family:'Courier New', monospace;
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color: #000000;
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font-size:88%;
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background-color: #ffffff;
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}
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h1 {
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font-weight: bold;
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margin-top: 24px;
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margin-bottom: 10px;
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border-bottom: 3px solid #000; font-size: 1em;
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}
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h2 {
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font-weight: bold;
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margin-top: 18px;
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margin-bottom: 5px;
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font-size: 0.90em;
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}
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h3 {
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font-weight: bold;
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margin-top: 12px;
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margin-bottom: 5px;
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font-size: 0.80em;
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}
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p {
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font-size:78%;
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}
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P.Table {
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margin-top: 4px;
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margin-bottom: 4px;
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margin-right: 4px;
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margin-left: 4px;
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}
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table
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{
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border-width: 1px 1px 1px 1px;
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border-style: solid solid solid solid;
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border-color: black black black black;
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border-collapse: collapse;
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}
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th {
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font-weight:bold;
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padding: 4px;
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border-width: 1px 1px 1px 1px;
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border-style: solid solid solid solid;
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border-color: black black black black;
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vertical-align:top;
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text-align:left;
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font-size:78%;
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}
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td {
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padding: 4px;
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border-width: 1px 1px 1px 1px;
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border-style: solid solid solid solid;
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border-color: black black black black;
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vertical-align:top;
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font-size:78%;
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}
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a {
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color:#013C9A;
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text-decoration:none;
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}
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a:visited {
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color:#013C9A;
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}
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a:hover, a:active {
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text-decoration:underline;
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color:#5BAFD4;
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}
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.pass
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{
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background-color: #00ff00;
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}
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.fail
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{
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background-color: #ff0000;
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}
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.comment
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{
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font-size: 90%;
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font-style: italic;
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}
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<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
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Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO640C
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Package: TQFP100
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Performance: 4
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Package Status: Final Version 1.17.
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Performance Hardware Data Status: Version 1.124.
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Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO640C
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Package: TQFP100
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Performance: 5
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Package Status: Final Version 1.17.
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Performance Hardware Data Status: Version 1.124.
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Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO640C
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Package: TQFP100
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Performance: M
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Package Status: Final Version 1.17.
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Performance Hardware Data Status: Version 1.124.
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// Design: RAM2GS
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// Package: TQFP100
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// ncd File: ram2gs_lcmxo640c_impl1.ncd
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// Version: Diamond (64-bit) 3.12.0.240.2
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// Written on Mon Aug 16 21:33:38 2021
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// M: Minimum Performance Grade
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// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml
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I/O Timing Report (All units are in ns)
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Worst Case Results across Performance Grades (M, 5, 4, 3):
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// Input Setup and Hold Times
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Port Clock Edge Setup Performance_Grade Hold Performance_Grade
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----------------------------------------------------------------------
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CROW[0] nCRAS F 0.474 3 1.625 3
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CROW[1] nCRAS F 0.104 3 1.925 3
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Din[0] PHI2 F 6.682 3 1.613 3
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Din[0] nCCAS F -0.028 M 2.082 3
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Din[1] PHI2 F 6.886 3 2.631 3
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Din[1] nCCAS F -0.025 M 2.074 3
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Din[2] PHI2 F 5.426 3 1.921 3
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Din[2] nCCAS F 1.175 3 1.003 3
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Din[3] PHI2 F 5.699 3 1.852 3
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Din[3] nCCAS F 0.331 3 1.707 3
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Din[4] PHI2 F 6.556 3 1.438 3
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Din[4] nCCAS F 0.706 3 1.406 3
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Din[5] PHI2 F 6.281 3 1.959 3
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Din[5] nCCAS F 0.246 3 1.807 3
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Din[6] PHI2 F 5.585 3 1.441 3
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Din[6] nCCAS F 0.799 3 1.341 3
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Din[7] PHI2 F 7.980 3 1.725 3
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Din[7] nCCAS F 0.333 3 1.707 3
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MAin[0] PHI2 F 4.994 3 1.265 3
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MAin[0] nCRAS F 0.662 3 1.471 3
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MAin[1] PHI2 F 6.056 3 1.867 3
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MAin[1] nCRAS F 1.180 3 0.990 3
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MAin[2] PHI2 F 10.634 3 -1.183 M
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MAin[2] nCRAS F -0.218 M 2.631 3
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MAin[3] PHI2 F 10.902 3 -1.260 M
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MAin[3] nCRAS F 0.208 3 1.826 3
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MAin[4] PHI2 F 10.204 3 -1.072 M
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MAin[4] nCRAS F -0.218 M 2.628 3
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MAin[5] PHI2 F 7.043 3 -0.270 M
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MAin[5] nCRAS F 0.123 3 1.925 3
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MAin[6] PHI2 F 9.465 3 -0.885 M
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MAin[6] nCRAS F 0.584 3 1.522 3
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MAin[7] PHI2 F 9.683 3 -0.938 M
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MAin[7] nCRAS F -0.218 M 2.628 3
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MAin[8] nCRAS F 0.316 3 1.758 3
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MAin[9] nCRAS F -0.058 M 2.185 3
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PHI2 RCLK R 1.456 3 0.038 3
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UFMSDO RCLK R 2.953 3 -0.147 M
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nCCAS RCLK R 2.435 3 -0.244 M
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nCCAS nCRAS F 0.156 3 1.902 3
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nCRAS RCLK R 5.307 3 -0.787 M
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nFWE PHI2 F 5.614 3 1.072 3
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nFWE nCRAS F -0.101 M 2.317 3
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// Clock to Output Delay
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Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
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------------------------------------------------------------------------
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LED RCLK R 11.635 3 3.019 M
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RA[0] RCLK R 11.287 3 2.893 M
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RA[0] nCRAS F 15.323 3 3.902 M
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RA[10] RCLK R 7.501 3 1.949 M
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RA[11] PHI2 R 9.747 3 2.487 M
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RA[1] RCLK R 11.083 3 2.855 M
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RA[1] nCRAS F 12.034 3 3.047 M
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RA[2] RCLK R 10.857 3 2.787 M
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RA[2] nCRAS F 13.411 3 3.403 M
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RA[3] RCLK R 10.775 3 2.772 M
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RA[3] nCRAS F 12.977 3 3.296 M
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RA[4] RCLK R 10.758 3 2.776 M
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RA[4] nCRAS F 14.192 3 3.619 M
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RA[5] RCLK R 10.334 3 2.652 M
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RA[5] nCRAS F 13.484 3 3.424 M
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RA[6] RCLK R 10.334 3 2.652 M
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RA[6] nCRAS F 12.972 3 3.291 M
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RA[7] RCLK R 9.917 3 2.572 M
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RA[7] nCRAS F 12.327 3 3.147 M
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RA[8] RCLK R 10.465 3 2.689 M
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RA[8] nCRAS F 12.559 3 3.170 M
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RA[9] RCLK R 10.412 3 2.668 M
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RA[9] nCRAS F 14.019 3 3.564 M
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RBA[0] nCRAS F 11.063 3 2.809 M
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RBA[1] nCRAS F 11.902 3 3.028 M
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RCKE RCLK R 7.501 3 1.949 M
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RDQMH RCLK R 9.831 3 2.523 M
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RDQML RCLK R 9.117 3 2.351 M
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RD[0] nCCAS F 12.575 3 3.249 M
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RD[1] nCCAS F 13.016 3 3.365 M
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RD[2] nCCAS F 11.602 3 2.993 M
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RD[3] nCCAS F 10.893 3 2.834 M
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RD[4] nCCAS F 12.063 3 3.116 M
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RD[5] nCCAS F 12.555 3 3.242 M
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RD[6] nCCAS F 12.537 3 3.240 M
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RD[7] nCCAS F 12.524 3 3.239 M
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UFMCLK RCLK R 8.079 3 2.126 M
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UFMSDI RCLK R 8.079 3 2.126 M
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nRCAS RCLK R 7.501 3 1.949 M
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nRCS RCLK R 7.501 3 1.949 M
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nRRAS RCLK R 9.175 3 2.363 M
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nRWE RCLK R 9.141 3 2.356 M
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nUFMCS RCLK R 8.804 3 2.290 M
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WARNING: you must also run trce with hold speed: 3
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WARNING: you must also run trce with setup speed: M
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</BODY>
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