26388 lines
925 KiB
VHDL
26388 lines
925 KiB
VHDL
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-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
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-- ldbanno -n VHDL -o RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd
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-- Netlist created on Tue Aug 15 05:03:26 2023
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-- Netlist written on Tue Aug 15 05:03:31 2023
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-- Design is for device LCMXO2-1200HC
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-- Design is for package TQFP100
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-- Design is for performance grade 4
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-- entity vmuxregsre
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity vmuxregsre is
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
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end vmuxregsre;
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architecture Structure of vmuxregsre is
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begin
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INST01: FL1P3DX
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generic map (GSR => "DISABLED")
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port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
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end Structure;
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-- entity vcc
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity vcc is
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port (PWR1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
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end vcc;
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architecture Structure of vcc is
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begin
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INST1: VHI
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port map (Z=>PWR1);
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end Structure;
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-- entity gnd
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity gnd is
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port (PWR0: out Std_logic);
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ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
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end gnd;
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architecture Structure of gnd is
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begin
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INST1: VLO
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port map (Z=>PWR0);
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end Structure;
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-- entity ccu2B0
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity ccu2B0 is
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE;
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end ccu2B0;
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architecture Structure of ccu2B0 is
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begin
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inst1: CCU2D
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generic map (INIT0 => X"faaa", INIT1 => X"faaa", INJECT1_0 => "NO",
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INJECT1_1 => "NO")
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port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
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C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
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end Structure;
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-- entity SLICE_0
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_0 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_0";
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI1_CLK : VitalDelayType := 0 ns;
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tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
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DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
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F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
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Q1: out Std_logic; FCO: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
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end SLICE_0;
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architecture Structure of SLICE_0 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A1_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal DI1_ipd : std_logic := 'X';
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signal DI1_dly : std_logic := 'X';
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signal DI0_ipd : std_logic := 'X';
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signal DI0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal FCI_ipd : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal FCO_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal GNDI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component ccu2B0
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
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end component;
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begin
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FS_610_i14: vmuxregsre
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port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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FS_610_i13: vmuxregsre
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port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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FS_610_add_4_15: ccu2B0
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port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
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C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
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CO1=>FCO_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
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VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
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VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
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FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE FCO_zd : std_logic := 'X';
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VARIABLE FCO_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_DI1_CLK : x01 := '0';
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VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_DI0_CLK : x01 := '0';
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VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => DI1_dly,
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TestSignalName => "DI1",
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TestDelay => tisd_DI1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI1_CLK_noedge_posedge,
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SetupLow => tsetup_DI1_CLK_noedge_posedge,
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HoldHigh => thold_DI1_CLK_noedge_posedge,
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HoldLow => thold_DI1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI1_CLK_TimingDatash,
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Violation => tviol_DI1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => DI0_dly,
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TestSignalName => "DI0",
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TestDelay => tisd_DI0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI0_CLK_noedge_posedge,
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SetupLow => tsetup_DI0_CLK_noedge_posedge,
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HoldHigh => thold_DI0_CLK_noedge_posedge,
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HoldLow => thold_DI0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI0_CLK_TimingDatash,
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Violation => tviol_DI0_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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FCO_zd := FCO_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => FCI_ipd'last_event,
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PathDelay => tpd_FCI_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F1,
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PathCondition => TRUE),
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2 => (InputChangeTime => FCI_ipd'last_event,
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PathDelay => tpd_FCI_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
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Paths => (0 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_FCO,
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PathCondition => TRUE),
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1 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_FCO,
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PathCondition => TRUE),
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2 => (InputChangeTime => FCI_ipd'last_event,
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PathDelay => tpd_FCI_FCO,
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PathCondition => TRUE)),
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GlitchData => FCO_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity SLICE_1
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_1 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_1";
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI1_CLK : VitalDelayType := 0 ns;
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tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
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DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
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F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
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Q1: out Std_logic; FCO: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
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end SLICE_1;
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architecture Structure of SLICE_1 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A1_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i12: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i11: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_13: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_2
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_2 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_2";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
|
|
|
|
end SLICE_2;
|
|
|
|
architecture Structure of SLICE_2 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i8: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i7: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_9: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_3
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_3 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_3";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
|
|
|
|
end SLICE_3;
|
|
|
|
architecture Structure of SLICE_3 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i6: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i5: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_7: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_4
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_4 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_4";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
|
|
|
|
end SLICE_4;
|
|
|
|
architecture Structure of SLICE_4 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_3: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity ccu20001
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity ccu20001 is
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
|
|
|
|
end ccu20001;
|
|
|
|
architecture Structure of ccu20001 is
|
|
begin
|
|
inst1: CCU2D
|
|
generic map (INIT0 => X"F000", INIT1 => X"0555", INJECT1_0 => "NO",
|
|
INJECT1_1 => "NO")
|
|
port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
|
|
C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
|
|
end Structure;
|
|
|
|
-- entity SLICE_5
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_5 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_5";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
|
|
|
|
end SLICE_5;
|
|
|
|
architecture Structure of SLICE_5 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20001
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i0: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CASr3_384: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_1: ccu20001
|
|
port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, DI1_dly, M0_dly, CLK_dly, Q0_out, F1_out,
|
|
Q1_out, FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_6
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_6 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_6";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
|
|
|
|
end SLICE_6;
|
|
|
|
architecture Structure of SLICE_6 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i10: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i9: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_11: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity ccu20002
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity ccu20002 is
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE;
|
|
|
|
end ccu20002;
|
|
|
|
architecture Structure of ccu20002 is
|
|
begin
|
|
inst1: CCU2D
|
|
generic map (INIT0 => X"faaa", INIT1 => X"0000", INJECT1_0 => "NO",
|
|
INJECT1_1 => "NO")
|
|
port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
|
|
C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
|
|
end Structure;
|
|
|
|
-- entity SLICE_7
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_7 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_7";
|
|
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
|
|
|
|
end SLICE_7;
|
|
|
|
architecture Structure of SLICE_7 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i17: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_add_4_19: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open,
|
|
CO1=>open);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_8
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_8 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_8";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
|
|
|
|
end SLICE_8;
|
|
|
|
architecture Structure of SLICE_8 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i4: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_5: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_9
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_9 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_9";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
|
|
|
|
end SLICE_9;
|
|
|
|
architecture Structure of SLICE_9 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B0
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_610_i16: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_610_i15: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_610_add_4_17: ccu2B0
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut4
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut4 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
|
|
|
|
end lut4;
|
|
|
|
architecture Structure of lut4 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0002")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40003
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40003 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
|
|
|
|
end lut40003;
|
|
|
|
architecture Structure of lut40003 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"2000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0004
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0004 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0004 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0004;
|
|
|
|
architecture Structure of vmuxregsre0004 is
|
|
begin
|
|
INST01: FL1P3IY
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity inverter
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity inverter is
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
|
|
|
|
end inverter;
|
|
|
|
architecture Structure of inverter is
|
|
begin
|
|
INST1: INV
|
|
port map (A=>I, Z=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_10
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_10 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_10";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE;
|
|
|
|
end SLICE_10;
|
|
|
|
architecture Structure of SLICE_10 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40003
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i3_3_lut_4_lut: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_4_lut_adj_4: lut40003
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
ADSubmitted_407: vmuxregsre0004
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40005
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40005 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
|
|
|
|
end lut40005;
|
|
|
|
architecture Structure of lut40005 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FF7F")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40006
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40006 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
|
|
|
|
end lut40006;
|
|
|
|
architecture Structure of lut40006 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"E0F0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0007
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0007 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0007;
|
|
|
|
architecture Structure of vmuxregsre0007 is
|
|
begin
|
|
INST01: FL1P3JY
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity SLICE_15
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_15 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_15";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_15 : ENTITY IS TRUE;
|
|
|
|
end SLICE_15;
|
|
|
|
architecture Structure of SLICE_15 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40006
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
i13_2_lut_rep_16_4_lut: lut40005
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1110_2_lut_3_lut_4_lut: lut40006
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
C1Submitted_406: vmuxregsre0007
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40008
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40008 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
|
|
|
|
end lut40008;
|
|
|
|
architecture Structure of lut40008 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"5555")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_16
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_16 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_16";
|
|
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE;
|
|
|
|
end SLICE_16;
|
|
|
|
architecture Structure of SLICE_16 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40008
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2045: lut40008
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CASr2_383: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CASr_382: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out,
|
|
Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40009
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40009 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
|
|
|
|
end lut40009;
|
|
|
|
architecture Structure of lut40009 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"C0CA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40010
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40010 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
|
|
|
|
end lut40010;
|
|
|
|
architecture Structure of lut40010 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_19
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_19 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_19";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
|
|
|
|
end SLICE_19;
|
|
|
|
architecture Structure of SLICE_19 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40009
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40010
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i26_4_lut: lut40009
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i2_3_lut_4_lut: lut40010
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdEnable_405: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40011
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40011 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
|
|
|
|
end lut40011;
|
|
|
|
architecture Structure of lut40011 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFFF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_20
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_20 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_20";
|
|
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
|
|
|
|
end SLICE_20;
|
|
|
|
architecture Structure of SLICE_20 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
n2447_001_BUF1_BUF1: lut40011
|
|
port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdSubmitted_411: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0 <= F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40012
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40012 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
|
|
|
|
end lut40012;
|
|
|
|
architecture Structure of lut40012 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FEFE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40013
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40013 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
|
|
|
|
end lut40013;
|
|
|
|
architecture Structure of lut40013 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CC5C")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_24
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_24 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_24";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE;
|
|
|
|
end SLICE_24;
|
|
|
|
architecture Structure of SLICE_24 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40013
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_3_lut_adj_15: lut40012
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Cmdn8MEGEN_I_93_4_lut: lut40013
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
Cmdn8MEGEN_410: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40014
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40014 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
|
|
|
|
end lut40014;
|
|
|
|
architecture Structure of lut40014 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4040")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_25
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_25 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_25";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE;
|
|
|
|
end SLICE_25;
|
|
|
|
architecture Structure of SLICE_25 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40008
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2_3_lut_3_lut: lut40014
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i2_1_lut_rep_24: lut40008
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
CBR_390: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
FWEr_389: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_26
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_26 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_26";
|
|
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
|
|
|
|
end SLICE_26;
|
|
|
|
architecture Structure of SLICE_26 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
n2447_000_BUF1_BUF1: lut40011
|
|
port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
InitReady_394: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0 <= F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_27
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_27 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_27";
|
|
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE;
|
|
|
|
end SLICE_27;
|
|
|
|
architecture Structure of SLICE_27 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
m1_lut: lut40011
|
|
port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
LEDEN_419: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0 <= F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40015
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40015 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
|
|
|
|
end lut40015;
|
|
|
|
architecture Structure of lut40015 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FBFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_30
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_30 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_30";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
|
|
|
|
end SLICE_30;
|
|
|
|
architecture Structure of SLICE_30 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40008
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40015
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2010_3_lut_3_lut: lut40015
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i2044: lut40008
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RASr2_380: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
RASr_379: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40016
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40016 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
|
|
|
|
end lut40016;
|
|
|
|
architecture Structure of lut40016 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8080")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40017
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40017 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
|
|
|
|
end lut40017;
|
|
|
|
architecture Structure of lut40017 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_32
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_32 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_32";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
|
|
|
|
end SLICE_32;
|
|
|
|
architecture Structure of SLICE_32 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40016
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40017
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2_3_lut_rep_32: lut40016
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i2_2_lut_3_lut_4_lut: lut40017
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RA10_400: vmuxregsre0007
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40018
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40018 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
|
|
|
|
end lut40018;
|
|
|
|
architecture Structure of lut40018 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1010")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40019
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40019 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
|
|
|
|
end lut40019;
|
|
|
|
architecture Structure of lut40019 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"C6C6")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_33
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_33 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_33";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
|
|
|
|
end SLICE_33;
|
|
|
|
architecture Structure of SLICE_33 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40019
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_3_lut: lut40018
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RA11_I_54_3_lut: lut40019
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
RA11_385: vmuxregsre0004
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40020
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40020 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
|
|
|
|
end lut40020;
|
|
|
|
architecture Structure of lut40020 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"20FF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40021
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40021 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
|
|
|
|
end lut40021;
|
|
|
|
architecture Structure of lut40021 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CACA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_35
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_35 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_35";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE;
|
|
|
|
end SLICE_35;
|
|
|
|
architecture Structure of SLICE_35 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40020
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_4_lut_adj_25: lut40020
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i29_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RCKEEN_401: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40022
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40022 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
|
|
|
|
end lut40022;
|
|
|
|
architecture Structure of lut40022 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CFC8")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_36
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_36 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_36";
|
|
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE;
|
|
|
|
end SLICE_36;
|
|
|
|
architecture Structure of SLICE_36 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40022
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1404_4_lut: lut40022
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
PHI2r2_377: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RCKE_395: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly,
|
|
CLK_dly, F0_out, Q0_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_37
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_37 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_37";
|
|
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE;
|
|
|
|
end SLICE_37;
|
|
|
|
architecture Structure of SLICE_37 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
n2447_002_BUF1_BUF1: lut40011
|
|
port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Ready_404: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0 <= F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40023
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40023 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
|
|
|
|
end lut40023;
|
|
|
|
architecture Structure of lut40023 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3A0A")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_44
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_44 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_44";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
|
|
|
|
end SLICE_44;
|
|
|
|
architecture Structure of SLICE_44 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40023
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1970_4_lut: lut40023
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1603_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
UFMCLK_416: vmuxregsre0004
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40024
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40024 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
|
|
|
|
end lut40024;
|
|
|
|
architecture Structure of lut40024 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CAC0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_45
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_45 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_45";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE;
|
|
|
|
end SLICE_45;
|
|
|
|
architecture Structure of SLICE_45 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40024
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i4_4_lut_adj_17: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1589_4_lut: lut40024
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
UFMSDI_417: vmuxregsre0004
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40025
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40025 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
|
|
|
|
end lut40025;
|
|
|
|
architecture Structure of lut40025 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FEFA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40026
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40026 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
|
|
|
|
end lut40026;
|
|
|
|
architecture Structure of lut40026 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0008")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_50
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_50 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_50";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
|
|
|
|
end SLICE_50;
|
|
|
|
architecture Structure of SLICE_50 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40025
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40026
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1962_4_lut: lut40025
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i2_3_lut_4_lut_adj_11: lut40026
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
XOR8MEG_408: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40027
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40027 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
|
|
|
|
end lut40027;
|
|
|
|
architecture Structure of lut40027 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40028
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40028 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
|
|
|
|
end lut40028;
|
|
|
|
architecture Structure of lut40028 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"BF04")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_57
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_57 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_57";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
|
|
|
|
end SLICE_57;
|
|
|
|
architecture Structure of SLICE_57 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40027
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40028
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2_3_lut_rep_18_4_lut: lut40027
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
n8MEGEN_I_14_3_lut_4_lut: lut40028
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
n8MEGEN_418: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40029
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40029 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
|
|
|
|
end lut40029;
|
|
|
|
architecture Structure of lut40029 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3AFA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40030
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40030 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
|
|
|
|
end lut40030;
|
|
|
|
architecture Structure of lut40030 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FE0E")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0031
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0031 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0031 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0031;
|
|
|
|
architecture Structure of vmuxregsre0031 is
|
|
begin
|
|
INST01: FL1P3BX
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity SLICE_59
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_59 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_59";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
|
|
|
|
end SLICE_59;
|
|
|
|
architecture Structure of SLICE_59 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40029
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40030
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0031
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_I_43_4_lut: lut40029
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCAS_I_0_452_3_lut_4_lut: lut40030
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRCAS_398: vmuxregsre0031
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40032
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40032 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
|
|
|
|
end lut40032;
|
|
|
|
architecture Structure of lut40032 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1F10")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_61
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_61 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_61";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
|
|
|
|
end SLICE_61;
|
|
|
|
architecture Structure of SLICE_61 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0031
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40032
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_I_31_3_lut_4_lut: lut40032
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCS_I_0_448_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRCS_396: vmuxregsre0031
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40033
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40033 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
|
|
|
|
end lut40033;
|
|
|
|
architecture Structure of lut40033 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"BFFF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_62
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_62 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_62";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
|
|
|
|
end SLICE_62;
|
|
|
|
architecture Structure of SLICE_62 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40029
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0031
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40033
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i3_4_lut_adj_2: lut40033
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCS_N_137_I_0_4_lut: lut40029
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRRAS_397: vmuxregsre0031
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40034
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40034 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
|
|
|
|
end lut40034;
|
|
|
|
architecture Structure of lut40034 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"EEEE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40035
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40035 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
|
|
|
|
end lut40035;
|
|
|
|
architecture Structure of lut40035 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CFC5")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_64
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_64 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_64";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
|
|
|
|
end SLICE_64;
|
|
|
|
architecture Structure of SLICE_64 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0031
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40035
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1477_2_lut: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRWE_I_0_455_4_lut: lut40035
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRWE_399: vmuxregsre0031
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40036
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40036 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
|
|
|
|
end lut40036;
|
|
|
|
architecture Structure of lut40036 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3032")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_65
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_65 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_65";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE;
|
|
|
|
end SLICE_65;
|
|
|
|
architecture Structure of SLICE_65 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40036
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i786_2_lut: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1432_4_lut: lut40036
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRowColSel_402: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40037
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40037 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
|
|
|
|
end lut40037;
|
|
|
|
architecture Structure of lut40037 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"BBBB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_66
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_66 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_66";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
|
|
|
|
end SLICE_66;
|
|
|
|
architecture Structure of SLICE_66 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_adj_23: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1439_2_lut: lut40034
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
S_FSM_i4: vmuxregsre0004
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40038
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40038 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
|
|
|
|
end lut40038;
|
|
|
|
architecture Structure of lut40038 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"2222")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_67
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_67 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_67";
|
|
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
|
|
|
|
end SLICE_67;
|
|
|
|
architecture Structure of SLICE_67 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_adj_10: lut40038
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
S_FSM_i3: vmuxregsre0004
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out,
|
|
Q0_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40039
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40039 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
|
|
|
|
end lut40039;
|
|
|
|
architecture Structure of lut40039 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8888")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_68
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_68 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_68";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
|
|
|
|
end SLICE_68;
|
|
|
|
architecture Structure of SLICE_68 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i4_2_lut: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1989_2_lut: lut40039
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
S_FSM_i2: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_69
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_69 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_69";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
|
|
|
|
end SLICE_69;
|
|
|
|
architecture Structure of SLICE_69 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40008
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1491_2_lut_rep_30: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RASr2_I_0_1_lut_rep_25: lut40008
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
PHI2r3_378: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
S_FSM_i1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly,
|
|
F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40040
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40040 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
|
|
|
|
end lut40040;
|
|
|
|
architecture Structure of lut40040 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFFE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40041
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40041 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
|
|
|
|
end lut40041;
|
|
|
|
architecture Structure of lut40041 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3FBB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_70
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_70 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_70";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
|
|
|
|
end SLICE_70;
|
|
|
|
architecture Structure of SLICE_70 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0031
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40040
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40041
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_4_lut: lut40040
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1448_4_lut: lut40041
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nUFMCS_415: vmuxregsre0031
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40042
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40042 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
|
|
|
|
end lut40042;
|
|
|
|
architecture Structure of lut40042 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1F1F")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40043
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40043 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
|
|
|
|
end lut40043;
|
|
|
|
architecture Structure of lut40043 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"5540")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity selmux2
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity selmux2 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
|
|
|
|
end selmux2;
|
|
|
|
architecture Structure of selmux2 is
|
|
begin
|
|
INST1: MUX21
|
|
port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
|
|
end Structure;
|
|
|
|
-- entity i30_SLICE_71
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity i30_SLICE_71 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "i30_SLICE_71";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF i30_SLICE_71 : ENTITY IS TRUE;
|
|
|
|
end i30_SLICE_71;
|
|
|
|
architecture Structure of i30_SLICE_71 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal OFX0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal i30_SLICE_71_i30_SLICE_71_K1_H1: Std_logic;
|
|
signal i30_SLICE_71_i30_GATE_H0: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40042
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40043
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component selmux2
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i30_SLICE_71_K1: lut40042
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI,
|
|
Z=>i30_SLICE_71_i30_SLICE_71_K1_H1);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i30_GATE: lut40043
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd,
|
|
Z=>i30_SLICE_71_i30_GATE_H0);
|
|
i30_SLICE_71_K0K1MUX: selmux2
|
|
port map (D0=>i30_SLICE_71_i30_GATE_H0,
|
|
D1=>i30_SLICE_71_i30_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M0_ipd, OFX0_out)
|
|
VARIABLE OFX0_zd : std_logic := 'X';
|
|
VARIABLE OFX0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
OFX0_zd := OFX0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_OFX0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_OFX0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_OFX0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_OFX0,
|
|
PathCondition => TRUE),
|
|
4 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_OFX0,
|
|
PathCondition => TRUE),
|
|
5 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_OFX0,
|
|
PathCondition => TRUE),
|
|
6 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_OFX0,
|
|
PathCondition => TRUE),
|
|
7 => (InputChangeTime => M0_ipd'last_event,
|
|
PathDelay => tpd_M0_OFX0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => OFX0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40044
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40044 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
|
|
|
|
end lut40044;
|
|
|
|
architecture Structure of lut40044 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FF40")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_72
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_72 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_72";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
|
|
|
|
end SLICE_72;
|
|
|
|
architecture Structure of SLICE_72 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40044
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_4_lut_4_lut_adj_12: lut40044
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i2_2_lut: lut40039
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_73
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_73 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_73";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
|
|
|
|
end SLICE_73;
|
|
|
|
architecture Structure of SLICE_73 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40003
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40010
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2_3_lut_4_lut_adj_14: lut40003
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i4_4_lut: lut40010
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40045
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40045 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
|
|
|
|
end lut40045;
|
|
|
|
architecture Structure of lut40045 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0020")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_74
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_74 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_74";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
|
|
|
|
end SLICE_74;
|
|
|
|
architecture Structure of SLICE_74 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40033
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40045
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i12_4_lut: lut40033
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_2_lut_3_lut_4_lut: lut40045
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_i1: vmuxregsre0004
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_i0: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out,
|
|
Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_75
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_75 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_75";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
|
|
|
|
end SLICE_75;
|
|
|
|
architecture Structure of SLICE_75 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40027
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i3_4_lut_adj_18: lut40027
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_2_lut: lut40038
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
IS_FSM_i9: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_FSM_i8: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_76
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_76 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_76";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
|
|
|
|
end SLICE_76;
|
|
|
|
architecture Structure of SLICE_76 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40026
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_rep_19_3_lut: lut40012
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1_2_lut_rep_15_4_lut: lut40026
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_i9: vmuxregsre0007
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_i8: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40046
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40046 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
|
|
|
|
end lut40046;
|
|
|
|
architecture Structure of lut40046 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0800")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_77
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_77 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_77";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
|
|
|
|
end SLICE_77;
|
|
|
|
architecture Structure of SLICE_77 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40046
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i3_4_lut_adj_22: lut40046
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i3_4_lut: lut40046
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40047
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40047 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
|
|
|
|
end lut40047;
|
|
|
|
architecture Structure of lut40047 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"F0DD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40048
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40048 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
|
|
|
|
end lut40048;
|
|
|
|
architecture Structure of lut40048 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"DDDD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_78
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_78 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_78";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
|
|
|
|
end SLICE_78;
|
|
|
|
architecture Structure of SLICE_78 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40047
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40048
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_N_146_bdd_4_lut: lut40047
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1423_2_lut: lut40048
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
IS_FSM_i13: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_FSM_i12: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40049
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40049 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
|
|
|
|
end lut40049;
|
|
|
|
architecture Structure of lut40049 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0200")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_79
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_79 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_79";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
|
|
|
|
end SLICE_79;
|
|
|
|
architecture Structure of SLICE_79 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40016
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i11_3_lut_rep_20: lut40016
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
MAin_c_0_bdd_4_lut: lut40049
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
IS_FSM_i11: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_FSM_i10: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40050
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40050 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
|
|
|
|
end lut40050;
|
|
|
|
architecture Structure of lut40050 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0001")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_80
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_80 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_80";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
|
|
|
|
end SLICE_80;
|
|
|
|
architecture Structure of SLICE_80 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40050
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i3_2_lut_rep_26: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i2005_3_lut_rep_17_4_lut: lut40050
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40051
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40051 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
|
|
|
|
end lut40051;
|
|
|
|
architecture Structure of lut40051 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FCDD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_81
|
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_81 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_81";
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_CE_CLK : VitalDelayType := 0 ns;
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tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
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C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
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M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
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CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
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F1: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
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end SLICE_81;
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architecture Structure of SLICE_81 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal CE_ipd : std_logic := 'X';
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signal CE_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40034
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40051
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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i1_2_lut_rep_29: lut40034
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port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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i1427_4_lut: lut40051
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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IS_FSM_i15: vmuxregsre
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port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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IS_FSM_i14: vmuxregsre
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port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(D0_ipd, D0, tipd_D0);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(M1_ipd, M1, tipd_M1);
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VitalWireDelay(M0_ipd, M0, tipd_M0);
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VitalWireDelay(CE_ipd, CE, tipd_CE);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
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VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
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VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
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M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_M1_CLK : x01 := '0';
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VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_M0_CLK : x01 := '0';
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VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CE_CLK : x01 := '0';
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VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => M1_dly,
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TestSignalName => "M1",
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TestDelay => tisd_M1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M1_CLK_noedge_posedge,
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SetupLow => tsetup_M1_CLK_noedge_posedge,
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HoldHigh => thold_M1_CLK_noedge_posedge,
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HoldLow => thold_M1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M1_CLK_TimingDatash,
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Violation => tviol_M1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => M0_dly,
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TestSignalName => "M0",
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TestDelay => tisd_M0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M0_CLK_noedge_posedge,
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SetupLow => tsetup_M0_CLK_noedge_posedge,
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HoldHigh => thold_M0_CLK_noedge_posedge,
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HoldLow => thold_M0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M0_CLK_TimingDatash,
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Violation => tviol_M0_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => CE_dly,
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TestSignalName => "CE",
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TestDelay => tisd_CE_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_CE_CLK_noedge_posedge,
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SetupLow => tsetup_CE_CLK_noedge_posedge,
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HoldHigh => thold_CE_CLK_noedge_posedge,
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HoldLow => thold_CE_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => CE_CLK_TimingDatash,
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Violation => tviol_CE_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => D0_ipd'last_event,
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PathDelay => tpd_D0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => C0_ipd'last_event,
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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2 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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3 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => B1_ipd'last_event,
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PathDelay => tpd_B1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity lut40052
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity lut40052 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
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end lut40052;
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architecture Structure of lut40052 is
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begin
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INST10: ROM16X1A
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generic map (initval => X"8000")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity SLICE_82
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_82 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_82";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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tperiod_LSR : VitalDelayType := 0 ns;
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tpw_LSR_posedge : VitalDelayType := 0 ns;
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tpw_LSR_negedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns;
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
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tisd_LSR_CLK : VitalDelayType := 0 ns;
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tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
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thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
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M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
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CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
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F1: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
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end SLICE_82;
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architecture Structure of SLICE_82 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal D1_ipd : std_logic := 'X';
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal LSR_ipd : std_logic := 'X';
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signal LSR_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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signal CLK_NOTIN: Std_logic;
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signal LSR_NOTIN: Std_logic;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component vmuxregsre0004
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i6_4_lut: lut40052
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_2_lut_adj_3: lut40039
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RowA_i5: vmuxregsre0007
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_i4: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40053
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40053 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
|
|
|
|
end lut40053;
|
|
|
|
architecture Structure of lut40053 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0004")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40054
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40054 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
|
|
|
|
end lut40054;
|
|
|
|
architecture Structure of lut40054 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFDF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_83
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_83 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_83";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
|
|
|
|
end SLICE_83;
|
|
|
|
architecture Structure of SLICE_83 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40053
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40054
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2_4_lut_adj_21: lut40053
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i2_3_lut_4_lut_adj_6: lut40054
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40055
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40055 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
|
|
|
|
end lut40055;
|
|
|
|
architecture Structure of lut40055 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"2020")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_84
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
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entity SLICE_84 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_84";
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_CE_CLK : VitalDelayType := 0 ns;
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tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
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D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
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A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
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CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
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Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
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end SLICE_84;
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architecture Structure of SLICE_84 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal CE_ipd : std_logic := 'X';
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signal CE_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40024
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40055
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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i2_3_lut_rep_28: lut40055
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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i1573_4_lut: lut40024
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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IS_FSM_i3: vmuxregsre
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port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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IS_FSM_i2: vmuxregsre
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port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(D0_ipd, D0, tipd_D0);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(M1_ipd, M1, tipd_M1);
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VitalWireDelay(M0_ipd, M0, tipd_M0);
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VitalWireDelay(CE_ipd, CE, tipd_CE);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
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VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
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VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
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A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_M1_CLK : x01 := '0';
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VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_M0_CLK : x01 := '0';
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VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CE_CLK : x01 := '0';
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VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => M1_dly,
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TestSignalName => "M1",
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TestDelay => tisd_M1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M1_CLK_noedge_posedge,
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SetupLow => tsetup_M1_CLK_noedge_posedge,
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HoldHigh => thold_M1_CLK_noedge_posedge,
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HoldLow => thold_M1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M1_CLK_TimingDatash,
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Violation => tviol_M1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => M0_dly,
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TestSignalName => "M0",
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TestDelay => tisd_M0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M0_CLK_noedge_posedge,
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SetupLow => tsetup_M0_CLK_noedge_posedge,
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HoldHigh => thold_M0_CLK_noedge_posedge,
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HoldLow => thold_M0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M0_CLK_TimingDatash,
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Violation => tviol_M0_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => CE_dly,
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TestSignalName => "CE",
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TestDelay => tisd_CE_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_CE_CLK_noedge_posedge,
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SetupLow => tsetup_CE_CLK_noedge_posedge,
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HoldHigh => thold_CE_CLK_noedge_posedge,
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HoldLow => thold_CE_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => CE_CLK_TimingDatash,
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Violation => tviol_CE_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => D0_ipd'last_event,
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PathDelay => tpd_D0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => C0_ipd'last_event,
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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2 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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3 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => C1_ipd'last_event,
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PathDelay => tpd_C1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => B1_ipd'last_event,
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PathDelay => tpd_B1_F1,
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PathCondition => TRUE),
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2 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity lut40056
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity lut40056 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
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end lut40056;
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architecture Structure of lut40056 is
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begin
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INST10: ROM16X1A
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generic map (initval => X"FFEF")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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|
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-- entity SLICE_85
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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|
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entity SLICE_85 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_85";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
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B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
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F1: out Std_logic);
|
|
|
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ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
|
|
|
|
end SLICE_85;
|
|
|
|
architecture Structure of SLICE_85 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
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signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
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|
signal B1_ipd : std_logic := 'X';
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|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
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|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40040
|
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40056
|
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1969_2_lut_3_lut_4_lut: lut40056
|
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i3_4_lut_adj_7: lut40040
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_86
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_86 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_86";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
|
|
|
|
end SLICE_86;
|
|
|
|
architecture Structure of SLICE_86 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i5_3_lut: lut40012
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1_4_lut_adj_8: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RASr3_381: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
PHI2r_376: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_87
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_87 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_87";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
|
|
|
|
end SLICE_87;
|
|
|
|
architecture Structure of SLICE_87 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40040
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40048
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i4_4_lut_adj_16: lut40040
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_2_lut_2_lut: lut40048
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RBA_i2: vmuxregsre0004
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RBA_i1: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40057
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40057 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
|
|
|
|
end lut40057;
|
|
|
|
architecture Structure of lut40057 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"C0C5")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_88
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_88 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_88";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
|
|
|
|
end SLICE_88;
|
|
|
|
architecture Structure of SLICE_88 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40053
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40057
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i34_4_lut: lut40057
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_4_lut_adj_13: lut40053
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
WRD_i7: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_i6: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40058
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40058 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
|
|
|
|
end lut40058;
|
|
|
|
architecture Structure of lut40058 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8088")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40059
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40059 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
|
|
|
|
end lut40059;
|
|
|
|
architecture Structure of lut40059 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"C444")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_89
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_89 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_89";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
|
|
|
|
end SLICE_89;
|
|
|
|
architecture Structure of SLICE_89 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40058
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40059
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2_4_lut: lut40058
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_4_lut: lut40059
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
WRD_i5: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_i4: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_90
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_90 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_90";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
|
|
|
|
end SLICE_90;
|
|
|
|
architecture Structure of SLICE_90 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40055
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_3_lut_4_lut_adj_1: lut40049
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_2_lut_rep_21_3_lut: lut40055
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
WRD_i1: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_i0: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40060
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40060 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
|
|
|
|
end lut40060;
|
|
|
|
architecture Structure of lut40060 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"DFDF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40061
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40061 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
|
|
|
|
end lut40061;
|
|
|
|
architecture Structure of lut40061 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"DFFF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_91
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_91 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_91";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
|
|
|
|
end SLICE_91;
|
|
|
|
architecture Structure of SLICE_91 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40060
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40061
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_rep_13_3_lut: lut40060
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1_2_lut_3_lut_4_lut_adj_5: lut40061
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_i3: vmuxregsre0004
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_i2: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40062
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40062 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
|
|
|
|
end lut40062;
|
|
|
|
architecture Structure of lut40062 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0080")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_92
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_92 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_92";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
|
|
|
|
end SLICE_92;
|
|
|
|
architecture Structure of SLICE_92 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40062
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2008_2_lut_4_lut: lut40062
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
i1_2_lut_rep_22_4_lut: lut40005
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
WRD_i3: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_i2: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40063
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40063 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
|
|
|
|
end lut40063;
|
|
|
|
architecture Structure of lut40063 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"7777")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_93
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_93 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_93";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
|
|
|
|
end SLICE_93;
|
|
|
|
architecture Structure of SLICE_93 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40063
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i2001_2_lut: lut40063
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
MAin_9_I_0_427_i10_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
Bank_i1: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Bank_i0: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly,
|
|
M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40064
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40064 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
|
|
|
|
end lut40064;
|
|
|
|
architecture Structure of lut40064 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFFD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_94
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_94 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_94";
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
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port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
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C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
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F0: out Std_logic; F1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
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end SLICE_94;
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architecture Structure of SLICE_94 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40048
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40064
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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i771_2_lut_rep_23_2_lut: lut40048
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port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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i2_3_lut_4_lut_4_lut: lut40064
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(D0_ipd, D0, tipd_D0);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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END BLOCK;
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VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
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F0_out, F1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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END IF;
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F0_zd := F0_out;
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F1_zd := F1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => D0_ipd'last_event,
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PathDelay => tpd_D0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => C0_ipd'last_event,
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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2 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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3 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => B1_ipd'last_event,
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PathDelay => tpd_B1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity lut40065
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity lut40065 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
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end lut40065;
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architecture Structure of lut40065 is
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begin
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INST10: ROM16X1A
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generic map (initval => X"1404")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity SLICE_95
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_95 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_95";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
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B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
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F1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE;
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end SLICE_95;
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architecture Structure of SLICE_95 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal D1_ipd : std_logic := 'X';
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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component lut40040
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40065
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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i2_4_lut_adj_20: lut40065
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
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i6_4_lut_adj_9: lut40040
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(D1_ipd, D1, tipd_D1);
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(D0_ipd, D0, tipd_D0);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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END BLOCK;
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VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
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B0_ipd, A0_ipd, F0_out, F1_out)
|
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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|
|
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BEGIN
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IF (TimingChecksOn) THEN
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END IF;
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F0_zd := F0_out;
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F1_zd := F1_out;
|
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => D0_ipd'last_event,
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PathDelay => tpd_D0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => C0_ipd'last_event,
|
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PathDelay => tpd_C0_F0,
|
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PathCondition => TRUE),
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2 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
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1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
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3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
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GlitchData => F1_GlitchData,
|
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
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|
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end Structure;
|
|
|
|
-- entity SLICE_96
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_96 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
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TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_96";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE;
|
|
|
|
end SLICE_96;
|
|
|
|
architecture Structure of SLICE_96 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40027
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_rep_27: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i2_3_lut_4_lut_adj_24: lut40027
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40066
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40066 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
|
|
|
|
end lut40066;
|
|
|
|
architecture Structure of lut40066 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"C5C5")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_97
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_97 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_97";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE;
|
|
|
|
end SLICE_97;
|
|
|
|
architecture Structure of SLICE_97 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40066
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i13_3_lut: lut40066
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1956_2_lut: lut40034
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
IS_FSM_i7: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_FSM_i6: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly,
|
|
M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_98
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_98 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_98";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE;
|
|
|
|
end SLICE_98;
|
|
|
|
architecture Structure of SLICE_98 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1416_2_lut: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
MAin_9_I_0_427_i9_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
IS_FSM_i1: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_FSM_i0: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly,
|
|
M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_99
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_99 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_99";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE;
|
|
|
|
end SLICE_99;
|
|
|
|
architecture Structure of SLICE_99 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i8_4_lut: lut40052
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
MAin_9_I_0_427_i8_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdUFMSDI_414: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_100
|
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_100 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_100";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns;
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
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tisd_CE_CLK : VitalDelayType := 0 ns;
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tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
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thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
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A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
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CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
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Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE;
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end SLICE_100;
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architecture Structure of SLICE_100 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal D1_ipd : std_logic := 'X';
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal CE_ipd : std_logic := 'X';
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signal CE_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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signal CLK_NOTIN: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component inverter
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port (I: in Std_logic; Z: out Std_logic);
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end component;
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component lut40021
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40052
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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i1979_4_lut: lut40052
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
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MAin_9_I_0_427_i7_3_lut: lut40021
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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CmdUFMCS_412: vmuxregsre
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port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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CLK_INVERTERIN: inverter
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port map (I=>CLK_dly, Z=>CLK_NOTIN);
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CmdUFMCLK_413: vmuxregsre
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port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
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LSR=>GNDI, Q=>Q0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(D1_ipd, D1, tipd_D1);
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(M1_ipd, M1, tipd_M1);
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VitalWireDelay(M0_ipd, M0, tipd_M0);
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VitalWireDelay(CE_ipd, CE, tipd_CE);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
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VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
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VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
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A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_M1_CLK : x01 := '0';
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VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_M0_CLK : x01 := '0';
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VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CE_CLK : x01 := '0';
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VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => M1_dly,
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TestSignalName => "M1",
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TestDelay => tisd_M1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M1_CLK_noedge_negedge,
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SetupLow => tsetup_M1_CLK_noedge_negedge,
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HoldHigh => thold_M1_CLK_noedge_negedge,
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HoldLow => thold_M1_CLK_noedge_negedge,
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CheckEnabled => TRUE,
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RefTransition => '\',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M1_CLK_TimingDatash,
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Violation => tviol_M1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => M0_dly,
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TestSignalName => "M0",
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TestDelay => tisd_M0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M0_CLK_noedge_negedge,
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SetupLow => tsetup_M0_CLK_noedge_negedge,
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HoldHigh => thold_M0_CLK_noedge_negedge,
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HoldLow => thold_M0_CLK_noedge_negedge,
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CheckEnabled => TRUE,
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RefTransition => '\',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M0_CLK_TimingDatash,
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Violation => tviol_M0_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => CE_dly,
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TestSignalName => "CE",
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TestDelay => tisd_CE_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_CE_CLK_noedge_negedge,
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SetupLow => tsetup_CE_CLK_noedge_negedge,
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HoldHigh => thold_CE_CLK_noedge_negedge,
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HoldLow => thold_CE_CLK_noedge_negedge,
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CheckEnabled => TRUE,
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RefTransition => '\',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => CE_CLK_TimingDatash,
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Violation => tviol_CE_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => C0_ipd'last_event,
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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2 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => D1_ipd'last_event,
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PathDelay => tpd_D1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => C1_ipd'last_event,
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PathDelay => tpd_C1_F1,
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PathCondition => TRUE),
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2 => (InputChangeTime => B1_ipd'last_event,
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PathDelay => tpd_B1_F1,
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PathCondition => TRUE),
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3 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity SLICE_101
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_101 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_101";
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
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C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
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M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
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F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
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Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE;
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end SLICE_101;
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architecture Structure of SLICE_101 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40021
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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MAin_9_I_0_427_i1_3_lut: lut40021
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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MAin_9_I_0_427_i6_3_lut: lut40021
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
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Bank_i7: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Bank_i6: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_102
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_102 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_102";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE;
|
|
|
|
end SLICE_102;
|
|
|
|
architecture Structure of SLICE_102 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_9_I_0_427_i2_3_lut: lut40021
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
MAin_9_I_0_427_i5_3_lut: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
Bank_i5: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Bank_i4: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_103
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_103 is
|
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_103";
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
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C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
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M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
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F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
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Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE;
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end SLICE_103;
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architecture Structure of SLICE_103 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40021
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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MAin_9_I_0_427_i3_3_lut: lut40021
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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MAin_9_I_0_427_i4_3_lut: lut40021
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
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Bank_i3: vmuxregsre
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port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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Bank_i2: vmuxregsre
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port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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|
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(M1_ipd, M1, tipd_M1);
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VitalWireDelay(M0_ipd, M0, tipd_M0);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
|
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
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VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
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M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_M1_CLK : x01 := '0';
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VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_M0_CLK : x01 := '0';
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VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => M1_dly,
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TestSignalName => "M1",
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TestDelay => tisd_M1_CLK,
|
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M1_CLK_noedge_posedge,
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SetupLow => tsetup_M1_CLK_noedge_posedge,
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|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
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HoldLow => thold_M1_CLK_noedge_posedge,
|
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M1_CLK_TimingDatash,
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|
Violation => tviol_M1_CLK,
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MsgSeverity => warning);
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|
VitalSetupHoldCheck (
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TestSignal => M0_dly,
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|
TestSignalName => "M0",
|
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TestDelay => tisd_M0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M0_CLK_noedge_posedge,
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SetupLow => tsetup_M0_CLK_noedge_posedge,
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HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
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|
RefTransition => '/',
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|
MsgOn => MsgOn, XOn => XOn,
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|
HeaderMsg => InstancePath,
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|
TimingData => M0_CLK_TimingDatash,
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|
Violation => tviol_M0_CLK,
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|
MsgSeverity => warning);
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|
VitalPeriodPulseCheck (
|
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TestSignal => CLK_ipd,
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|
TestSignalName => "CLK",
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|
Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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|
Violation => tviol_CLK_CLK,
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|
MsgOn => MsgOn, XOn => XOn,
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|
HeaderMsg => InstancePath,
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|
CheckEnabled => TRUE,
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|
MsgSeverity => warning);
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|
|
|
END IF;
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|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
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|
Q1_zd := Q1_out;
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|
|
VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => C0_ipd'last_event,
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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|
1 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
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|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
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|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
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|
GlitchData => Q0_GlitchData,
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|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
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|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
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GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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|
|
|
END PROCESS;
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|
|
|
end Structure;
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|
|
|
-- entity lut40067
|
|
library IEEE, vital2000, MACHXO2;
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|
use IEEE.STD_LOGIC_1164.all;
|
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use vital2000.vital_timing.all;
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|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40067 is
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|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
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|
|
|
end lut40067;
|
|
|
|
architecture Structure of lut40067 is
|
|
begin
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|
INST10: ROM16X1A
|
|
generic map (initval => X"FDFD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_104
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_104 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_104";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE;
|
|
|
|
end SLICE_104;
|
|
|
|
architecture Structure of SLICE_104 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0004
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40067
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1417_2_lut: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1_2_lut_rep_14_3_lut: lut40067
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
RowA_i7: vmuxregsre0004
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_i6: vmuxregsre0004
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly,
|
|
M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_105
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_105 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_105";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE;
|
|
|
|
end SLICE_105;
|
|
|
|
architecture Structure of SLICE_105 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_adj_19: lut40039
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i5_4_lut: lut40052
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_106
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_106 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_106";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE;
|
|
|
|
end SLICE_106;
|
|
|
|
architecture Structure of SLICE_106 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
i1_2_lut_rep_33: lut40039
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
i1930_2_lut: lut40034
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
IS_FSM_i5: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_FSM_i4: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly,
|
|
CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf is
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf;
|
|
|
|
architecture Structure of xo2iobuf is
|
|
begin
|
|
INST1: IBPD
|
|
port map (I=>PADI, O=>Z);
|
|
INST2: OBZPD
|
|
port map (I=>I, T=>T, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity RD_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_7_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD7 : VitalDelayType := 0 ns;
|
|
tpw_RD7_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD7_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD7: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
|
|
|
|
end RD_7_B;
|
|
|
|
architecture Structure of RD_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD7_ipd : std_logic := 'X';
|
|
signal RD7_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_7_713: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out,
|
|
PADI=>RD7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD7_zd : std_logic := 'X';
|
|
VARIABLE RD7_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD7_RD7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD7_ipd,
|
|
TestSignalName => "RD7",
|
|
Period => tperiod_RD7,
|
|
PulseWidthHigh => tpw_RD7_posedge,
|
|
PulseWidthLow => tpw_RD7_negedge,
|
|
PeriodData => periodcheckinfo_RD7,
|
|
Violation => tviol_RD7_RD7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD7_zd := RD7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD7_ipd'last_event,
|
|
PathDelay => tpd_RD7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD7,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_6_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD6 : VitalDelayType := 0 ns;
|
|
tpw_RD6_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD6_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD6: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
|
|
|
|
end RD_6_B;
|
|
|
|
architecture Structure of RD_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD6_ipd : std_logic := 'X';
|
|
signal RD6_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_6_714: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out,
|
|
PADI=>RD6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD6_zd : std_logic := 'X';
|
|
VARIABLE RD6_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD6_RD6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD6_ipd,
|
|
TestSignalName => "RD6",
|
|
Period => tperiod_RD6,
|
|
PulseWidthHigh => tpw_RD6_posedge,
|
|
PulseWidthLow => tpw_RD6_negedge,
|
|
PeriodData => periodcheckinfo_RD6,
|
|
Violation => tviol_RD6_RD6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD6_zd := RD6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD6_ipd'last_event,
|
|
PathDelay => tpd_RD6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD6,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_5_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD5 : VitalDelayType := 0 ns;
|
|
tpw_RD5_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD5_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD5: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
|
|
|
|
end RD_5_B;
|
|
|
|
architecture Structure of RD_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD5_ipd : std_logic := 'X';
|
|
signal RD5_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_5_715: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out,
|
|
PADI=>RD5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD5_zd : std_logic := 'X';
|
|
VARIABLE RD5_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD5_RD5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD5_ipd,
|
|
TestSignalName => "RD5",
|
|
Period => tperiod_RD5,
|
|
PulseWidthHigh => tpw_RD5_posedge,
|
|
PulseWidthLow => tpw_RD5_negedge,
|
|
PeriodData => periodcheckinfo_RD5,
|
|
Violation => tviol_RD5_RD5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD5_zd := RD5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD5_ipd'last_event,
|
|
PathDelay => tpd_RD5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD5,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_4_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD4 : VitalDelayType := 0 ns;
|
|
tpw_RD4_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD4_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD4: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
|
|
|
|
end RD_4_B;
|
|
|
|
architecture Structure of RD_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD4_ipd : std_logic := 'X';
|
|
signal RD4_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_4_716: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out,
|
|
PADI=>RD4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD4_zd : std_logic := 'X';
|
|
VARIABLE RD4_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD4_RD4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD4_ipd,
|
|
TestSignalName => "RD4",
|
|
Period => tperiod_RD4,
|
|
PulseWidthHigh => tpw_RD4_posedge,
|
|
PulseWidthLow => tpw_RD4_negedge,
|
|
PeriodData => periodcheckinfo_RD4,
|
|
Violation => tviol_RD4_RD4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD4_zd := RD4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD4_ipd'last_event,
|
|
PathDelay => tpd_RD4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD4,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_3_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD3 : VitalDelayType := 0 ns;
|
|
tpw_RD3_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD3_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD3: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
|
|
|
|
end RD_3_B;
|
|
|
|
architecture Structure of RD_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD3_ipd : std_logic := 'X';
|
|
signal RD3_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_3_717: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out,
|
|
PADI=>RD3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD3_zd : std_logic := 'X';
|
|
VARIABLE RD3_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD3_RD3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD3_ipd,
|
|
TestSignalName => "RD3",
|
|
Period => tperiod_RD3,
|
|
PulseWidthHigh => tpw_RD3_posedge,
|
|
PulseWidthLow => tpw_RD3_negedge,
|
|
PeriodData => periodcheckinfo_RD3,
|
|
Violation => tviol_RD3_RD3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD3_zd := RD3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD3_ipd'last_event,
|
|
PathDelay => tpd_RD3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD3,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_2_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD2 : VitalDelayType := 0 ns;
|
|
tpw_RD2_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD2_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD2: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
|
|
|
|
end RD_2_B;
|
|
|
|
architecture Structure of RD_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD2_ipd : std_logic := 'X';
|
|
signal RD2_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_2_718: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out,
|
|
PADI=>RD2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD2_zd : std_logic := 'X';
|
|
VARIABLE RD2_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD2_RD2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD2_ipd,
|
|
TestSignalName => "RD2",
|
|
Period => tperiod_RD2,
|
|
PulseWidthHigh => tpw_RD2_posedge,
|
|
PulseWidthLow => tpw_RD2_negedge,
|
|
PeriodData => periodcheckinfo_RD2,
|
|
Violation => tviol_RD2_RD2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD2_zd := RD2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD2_ipd'last_event,
|
|
PathDelay => tpd_RD2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD2,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_1_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD1 : VitalDelayType := 0 ns;
|
|
tpw_RD1_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD1_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD1: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
|
|
|
|
end RD_1_B;
|
|
|
|
architecture Structure of RD_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD1_ipd : std_logic := 'X';
|
|
signal RD1_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_1_719: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out,
|
|
PADI=>RD1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD1_zd : std_logic := 'X';
|
|
VARIABLE RD1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD1_RD1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD1_ipd,
|
|
TestSignalName => "RD1",
|
|
Period => tperiod_RD1,
|
|
PulseWidthHigh => tpw_RD1_posedge,
|
|
PulseWidthLow => tpw_RD1_negedge,
|
|
PeriodData => periodcheckinfo_RD1,
|
|
Violation => tviol_RD1_RD1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD1_zd := RD1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD1_ipd'last_event,
|
|
PathDelay => tpd_RD1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_0_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD0 : VitalDelayType := 0 ns;
|
|
tpw_RD0_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD0_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD0: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
|
|
|
|
end RD_0_B;
|
|
|
|
architecture Structure of RD_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD0_ipd : std_logic := 'X';
|
|
signal RD0_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_0_720: xo2iobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out,
|
|
PADI=>RD0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD0_zd : std_logic := 'X';
|
|
VARIABLE RD0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD0_RD0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD0_ipd,
|
|
TestSignalName => "RD0",
|
|
Period => tperiod_RD0,
|
|
PulseWidthHigh => tpw_RD0_posedge,
|
|
PulseWidthLow => tpw_RD0_negedge,
|
|
PeriodData => periodcheckinfo_RD0,
|
|
Violation => tviol_RD0_RD0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD0_zd := RD0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD0_ipd'last_event,
|
|
PathDelay => tpd_RD0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0068
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0068 is
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0068 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0068;
|
|
|
|
architecture Structure of xo2iobuf0068 is
|
|
begin
|
|
INST5: OBZPD
|
|
port map (I=>I, T=>T, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity Dout_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_7_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout7: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
|
|
|
|
end Dout_7_B;
|
|
|
|
architecture Structure of Dout_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout7_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_7: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
|
|
VARIABLE Dout7_zd : std_logic := 'X';
|
|
VARIABLE Dout7_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout7_zd := Dout7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_6_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout6: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
|
|
|
|
end Dout_6_B;
|
|
|
|
architecture Structure of Dout_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout6_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_6: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
|
|
VARIABLE Dout6_zd : std_logic := 'X';
|
|
VARIABLE Dout6_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout6_zd := Dout6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_5_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout5: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
|
|
|
|
end Dout_5_B;
|
|
|
|
architecture Structure of Dout_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout5_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_5: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
|
|
VARIABLE Dout5_zd : std_logic := 'X';
|
|
VARIABLE Dout5_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout5_zd := Dout5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_4_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout4: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
|
|
|
|
end Dout_4_B;
|
|
|
|
architecture Structure of Dout_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout4_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_4: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
|
|
VARIABLE Dout4_zd : std_logic := 'X';
|
|
VARIABLE Dout4_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout4_zd := Dout4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_3_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout3: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
|
|
|
|
end Dout_3_B;
|
|
|
|
architecture Structure of Dout_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout3_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_3: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
|
|
VARIABLE Dout3_zd : std_logic := 'X';
|
|
VARIABLE Dout3_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout3_zd := Dout3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_2_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout2: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
|
|
|
|
end Dout_2_B;
|
|
|
|
architecture Structure of Dout_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout2_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_2: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
|
|
VARIABLE Dout2_zd : std_logic := 'X';
|
|
VARIABLE Dout2_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout2_zd := Dout2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
|
|
|
|
end Dout_1_B;
|
|
|
|
architecture Structure of Dout_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_1: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
|
|
VARIABLE Dout1_zd : std_logic := 'X';
|
|
VARIABLE Dout1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout1_zd := Dout1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
|
|
|
|
end Dout_0_B;
|
|
|
|
architecture Structure of Dout_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_0: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
|
|
VARIABLE Dout0_zd : std_logic := 'X';
|
|
VARIABLE Dout0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout0_zd := Dout0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity LEDB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity LEDB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "LEDB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; LEDS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
|
|
|
|
end LEDB;
|
|
|
|
architecture Structure of LEDB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal LEDS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
LED_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
|
|
VARIABLE LEDS_zd : std_logic := 'X';
|
|
VARIABLE LEDS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
LEDS_zd := LEDS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_LEDS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => LEDS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RBA_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RBA1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
|
|
|
|
end RBA_1_B;
|
|
|
|
architecture Structure of RBA_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RBA1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_pad_1: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
|
|
VARIABLE RBA1_zd : std_logic := 'X';
|
|
VARIABLE RBA1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RBA1_zd := RBA1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RBA1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RBA1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RBA_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RBA0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
|
|
|
|
end RBA_0_B;
|
|
|
|
architecture Structure of RBA_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RBA0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_pad_0: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
|
|
VARIABLE RBA0_zd : std_logic := 'X';
|
|
VARIABLE RBA0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RBA0_zd := RBA0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RBA0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RBA0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_11_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_11_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_11_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA11 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA11: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
|
|
|
|
end RA_11_B;
|
|
|
|
architecture Structure of RA_11_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA11_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_11: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
|
|
VARIABLE RA11_zd : std_logic := 'X';
|
|
VARIABLE RA11_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA11_zd := RA11_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA11,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA11_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_10_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_10_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_10_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA10 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA10: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
|
|
|
|
end RA_10_B;
|
|
|
|
architecture Structure of RA_10_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA10_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_10: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
|
|
VARIABLE RA10_zd : std_logic := 'X';
|
|
VARIABLE RA10_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA10_zd := RA10_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA10,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA10_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_9_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_9_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_9_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA9: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
|
|
|
|
end RA_9_B;
|
|
|
|
architecture Structure of RA_9_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA9_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_9: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
|
|
VARIABLE RA9_zd : std_logic := 'X';
|
|
VARIABLE RA9_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA9_zd := RA9_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA9,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA9_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_8_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_8_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_8_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA8: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
|
|
|
|
end RA_8_B;
|
|
|
|
architecture Structure of RA_8_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA8_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_8: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
|
|
VARIABLE RA8_zd : std_logic := 'X';
|
|
VARIABLE RA8_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA8_zd := RA8_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA8,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA8_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_7_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA7: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
|
|
|
|
end RA_7_B;
|
|
|
|
architecture Structure of RA_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA7_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_7: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
|
|
VARIABLE RA7_zd : std_logic := 'X';
|
|
VARIABLE RA7_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA7_zd := RA7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_6_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA6: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
|
|
|
|
end RA_6_B;
|
|
|
|
architecture Structure of RA_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA6_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_6: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
|
|
VARIABLE RA6_zd : std_logic := 'X';
|
|
VARIABLE RA6_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA6_zd := RA6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_5_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA5: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
|
|
|
|
end RA_5_B;
|
|
|
|
architecture Structure of RA_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA5_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_5: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
|
|
VARIABLE RA5_zd : std_logic := 'X';
|
|
VARIABLE RA5_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA5_zd := RA5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_4_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA4: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
|
|
|
|
end RA_4_B;
|
|
|
|
architecture Structure of RA_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA4_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_4: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
|
|
VARIABLE RA4_zd : std_logic := 'X';
|
|
VARIABLE RA4_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA4_zd := RA4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_3_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA3: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
|
|
|
|
end RA_3_B;
|
|
|
|
architecture Structure of RA_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA3_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_3: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
|
|
VARIABLE RA3_zd : std_logic := 'X';
|
|
VARIABLE RA3_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA3_zd := RA3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_2_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA2: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
|
|
|
|
end RA_2_B;
|
|
|
|
architecture Structure of RA_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA2_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_2: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
|
|
VARIABLE RA2_zd : std_logic := 'X';
|
|
VARIABLE RA2_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA2_zd := RA2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
|
|
|
|
end RA_1_B;
|
|
|
|
architecture Structure of RA_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_1: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
|
|
VARIABLE RA1_zd : std_logic := 'X';
|
|
VARIABLE RA1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA1_zd := RA1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
|
|
|
|
end RA_0_B;
|
|
|
|
architecture Structure of RA_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_0: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
|
|
VARIABLE RA0_zd : std_logic := 'X';
|
|
VARIABLE RA0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA0_zd := RA0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCSB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRCSB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCSB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; nRCSS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
|
|
|
|
end nRCSB;
|
|
|
|
architecture Structure of nRCSB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRCSS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
|
|
VARIABLE nRCSS_zd : std_logic := 'X';
|
|
VARIABLE nRCSS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRCSS_zd := nRCSS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRCSS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRCSS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RCKEB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RCKEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RCKEB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RCKES: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
|
|
|
|
end RCKEB;
|
|
|
|
architecture Structure of RCKEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RCKES_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RCKE_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
|
|
VARIABLE RCKES_zd : std_logic := 'X';
|
|
VARIABLE RCKES_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RCKES_zd := RCKES_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RCKES,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RCKES_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRWEB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRWEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRWEB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRWES : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; nRWES: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
|
|
|
|
end nRWEB;
|
|
|
|
architecture Structure of nRWEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRWES_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
|
|
VARIABLE nRWES_zd : std_logic := 'X';
|
|
VARIABLE nRWES_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRWES_zd := nRWES_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRWES,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRWES_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRRASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRRASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRRASB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; nRRASS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
|
|
|
|
end nRRASB;
|
|
|
|
architecture Structure of nRRASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRRASS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
|
|
VARIABLE nRRASS_zd : std_logic := 'X';
|
|
VARIABLE nRRASS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRRASS_zd := nRRASS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRRASS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRRASS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRCASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCASB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; nRCASS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
|
|
|
|
end nRCASB;
|
|
|
|
architecture Structure of nRCASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRCASS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
|
|
VARIABLE nRCASS_zd : std_logic := 'X';
|
|
VARIABLE nRCASS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRCASS_zd := nRCASS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRCASS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRCASS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RDQMHB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RDQMHB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RDQMHB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RDQMHS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
|
|
|
|
end RDQMHB;
|
|
|
|
architecture Structure of RDQMHB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RDQMHS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQMH_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
|
|
VARIABLE RDQMHS_zd : std_logic := 'X';
|
|
VARIABLE RDQMHS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RDQMHS_zd := RDQMHS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RDQMHS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RDQMHS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RDQMLB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RDQMLB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RDQMLB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RDQMLS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
|
|
|
|
end RDQMLB;
|
|
|
|
architecture Structure of RDQMLB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RDQMLS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQML_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
|
|
VARIABLE RDQMLS_zd : std_logic := 'X';
|
|
VARIABLE RDQMLS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RDQMLS_zd := RDQMLS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RDQMLS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RDQMLS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nUFMCSB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nUFMCSB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nUFMCSB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
|
|
|
|
end nUFMCSB;
|
|
|
|
architecture Structure of nUFMCSB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nUFMCSS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nUFMCS_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
|
|
VARIABLE nUFMCSS_zd : std_logic := 'X';
|
|
VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nUFMCSS_zd := nUFMCSS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nUFMCSS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nUFMCSS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity UFMCLKB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity UFMCLKB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "UFMCLKB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
|
|
|
|
end UFMCLKB;
|
|
|
|
architecture Structure of UFMCLKB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal UFMCLKS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMCLK_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
|
|
VARIABLE UFMCLKS_zd : std_logic := 'X';
|
|
VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
UFMCLKS_zd := UFMCLKS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_UFMCLKS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => UFMCLKS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity UFMSDIB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity UFMSDIB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "UFMSDIB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
|
|
|
|
end UFMSDIB;
|
|
|
|
architecture Structure of UFMSDIB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal UFMSDIS_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component xo2iobuf0068
|
|
port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_pad: xo2iobuf0068
|
|
port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
|
|
VARIABLE UFMSDIS_zd : std_logic := 'X';
|
|
VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
UFMSDIS_zd := UFMSDIS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_UFMSDIS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => UFMSDIS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0069
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0069 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0069 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0069;
|
|
|
|
architecture Structure of xo2iobuf0069 is
|
|
begin
|
|
INST1: IBPD
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity PHI2B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity PHI2B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "PHI2B";
|
|
|
|
tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_PHI2S : VitalDelayType := 0 ns;
|
|
tpw_PHI2S_posedge : VitalDelayType := 0 ns;
|
|
tpw_PHI2S_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; PHI2S: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
|
|
|
|
end PHI2B;
|
|
|
|
architecture Structure of PHI2B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PHI2S_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2_pad: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_PHI2S_PHI2S : x01 := '0';
|
|
VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => PHI2S_ipd,
|
|
TestSignalName => "PHI2S",
|
|
Period => tperiod_PHI2S,
|
|
PulseWidthHigh => tpw_PHI2S_posedge,
|
|
PulseWidthLow => tpw_PHI2S_negedge,
|
|
PeriodData => periodcheckinfo_PHI2S,
|
|
Violation => tviol_PHI2S_PHI2S,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event,
|
|
PathDelay => tpd_PHI2S_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_9_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_9_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_9_B";
|
|
|
|
tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin9 : VitalDelayType := 0 ns;
|
|
tpw_MAin9_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin9_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin9: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
|
|
|
|
end MAin_9_B;
|
|
|
|
architecture Structure of MAin_9_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin9_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_9: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin9_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin9_MAin9 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin9_ipd,
|
|
TestSignalName => "MAin9",
|
|
Period => tperiod_MAin9,
|
|
PulseWidthHigh => tpw_MAin9_posedge,
|
|
PulseWidthLow => tpw_MAin9_negedge,
|
|
PeriodData => periodcheckinfo_MAin9,
|
|
Violation => tviol_MAin9_MAin9,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin9_ipd'last_event,
|
|
PathDelay => tpd_MAin9_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_8_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_8_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_8_B";
|
|
|
|
tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin8 : VitalDelayType := 0 ns;
|
|
tpw_MAin8_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin8_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin8: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
|
|
|
|
end MAin_8_B;
|
|
|
|
architecture Structure of MAin_8_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin8_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_8: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin8_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin8_MAin8 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin8_ipd,
|
|
TestSignalName => "MAin8",
|
|
Period => tperiod_MAin8,
|
|
PulseWidthHigh => tpw_MAin8_posedge,
|
|
PulseWidthLow => tpw_MAin8_negedge,
|
|
PeriodData => periodcheckinfo_MAin8,
|
|
Violation => tviol_MAin8_MAin8,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin8_ipd'last_event,
|
|
PathDelay => tpd_MAin8_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_7_B";
|
|
|
|
tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin7 : VitalDelayType := 0 ns;
|
|
tpw_MAin7_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin7_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin7: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
|
|
|
|
end MAin_7_B;
|
|
|
|
architecture Structure of MAin_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin7_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_7: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin7_MAin7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin7_ipd,
|
|
TestSignalName => "MAin7",
|
|
Period => tperiod_MAin7,
|
|
PulseWidthHigh => tpw_MAin7_posedge,
|
|
PulseWidthLow => tpw_MAin7_negedge,
|
|
PeriodData => periodcheckinfo_MAin7,
|
|
Violation => tviol_MAin7_MAin7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin7_ipd'last_event,
|
|
PathDelay => tpd_MAin7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_6_B";
|
|
|
|
tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin6 : VitalDelayType := 0 ns;
|
|
tpw_MAin6_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin6_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin6: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
|
|
|
|
end MAin_6_B;
|
|
|
|
architecture Structure of MAin_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin6_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_6: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin6_MAin6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin6_ipd,
|
|
TestSignalName => "MAin6",
|
|
Period => tperiod_MAin6,
|
|
PulseWidthHigh => tpw_MAin6_posedge,
|
|
PulseWidthLow => tpw_MAin6_negedge,
|
|
PeriodData => periodcheckinfo_MAin6,
|
|
Violation => tviol_MAin6_MAin6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin6_ipd'last_event,
|
|
PathDelay => tpd_MAin6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_5_B";
|
|
|
|
tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin5 : VitalDelayType := 0 ns;
|
|
tpw_MAin5_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin5_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin5: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
|
|
|
|
end MAin_5_B;
|
|
|
|
architecture Structure of MAin_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin5_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_5: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin5_MAin5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin5_ipd,
|
|
TestSignalName => "MAin5",
|
|
Period => tperiod_MAin5,
|
|
PulseWidthHigh => tpw_MAin5_posedge,
|
|
PulseWidthLow => tpw_MAin5_negedge,
|
|
PeriodData => periodcheckinfo_MAin5,
|
|
Violation => tviol_MAin5_MAin5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin5_ipd'last_event,
|
|
PathDelay => tpd_MAin5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_4_B";
|
|
|
|
tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin4 : VitalDelayType := 0 ns;
|
|
tpw_MAin4_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin4_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin4: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
|
|
|
|
end MAin_4_B;
|
|
|
|
architecture Structure of MAin_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin4_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_4: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin4_MAin4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin4_ipd,
|
|
TestSignalName => "MAin4",
|
|
Period => tperiod_MAin4,
|
|
PulseWidthHigh => tpw_MAin4_posedge,
|
|
PulseWidthLow => tpw_MAin4_negedge,
|
|
PeriodData => periodcheckinfo_MAin4,
|
|
Violation => tviol_MAin4_MAin4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin4_ipd'last_event,
|
|
PathDelay => tpd_MAin4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_3_B";
|
|
|
|
tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin3 : VitalDelayType := 0 ns;
|
|
tpw_MAin3_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin3_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin3: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
|
|
|
|
end MAin_3_B;
|
|
|
|
architecture Structure of MAin_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin3_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_3: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin3_MAin3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin3_ipd,
|
|
TestSignalName => "MAin3",
|
|
Period => tperiod_MAin3,
|
|
PulseWidthHigh => tpw_MAin3_posedge,
|
|
PulseWidthLow => tpw_MAin3_negedge,
|
|
PeriodData => periodcheckinfo_MAin3,
|
|
Violation => tviol_MAin3_MAin3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin3_ipd'last_event,
|
|
PathDelay => tpd_MAin3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_2_B";
|
|
|
|
tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin2 : VitalDelayType := 0 ns;
|
|
tpw_MAin2_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin2_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin2: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
|
|
|
|
end MAin_2_B;
|
|
|
|
architecture Structure of MAin_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin2_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_2: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin2_MAin2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin2_ipd,
|
|
TestSignalName => "MAin2",
|
|
Period => tperiod_MAin2,
|
|
PulseWidthHigh => tpw_MAin2_posedge,
|
|
PulseWidthLow => tpw_MAin2_negedge,
|
|
PeriodData => periodcheckinfo_MAin2,
|
|
Violation => tviol_MAin2_MAin2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin2_ipd'last_event,
|
|
PathDelay => tpd_MAin2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_1_B";
|
|
|
|
tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin1 : VitalDelayType := 0 ns;
|
|
tpw_MAin1_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
|
|
|
|
end MAin_1_B;
|
|
|
|
architecture Structure of MAin_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin1_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_1: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin1_MAin1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin1_ipd,
|
|
TestSignalName => "MAin1",
|
|
Period => tperiod_MAin1,
|
|
PulseWidthHigh => tpw_MAin1_posedge,
|
|
PulseWidthLow => tpw_MAin1_negedge,
|
|
PeriodData => periodcheckinfo_MAin1,
|
|
Violation => tviol_MAin1_MAin1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin1_ipd'last_event,
|
|
PathDelay => tpd_MAin1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_0_B";
|
|
|
|
tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin0 : VitalDelayType := 0 ns;
|
|
tpw_MAin0_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
|
|
|
|
end MAin_0_B;
|
|
|
|
architecture Structure of MAin_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin0_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_0: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>MAin0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin0_MAin0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin0_ipd,
|
|
TestSignalName => "MAin0",
|
|
Period => tperiod_MAin0,
|
|
PulseWidthHigh => tpw_MAin0_posedge,
|
|
PulseWidthLow => tpw_MAin0_negedge,
|
|
PeriodData => periodcheckinfo_MAin0,
|
|
Violation => tviol_MAin0_MAin0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin0_ipd'last_event,
|
|
PathDelay => tpd_MAin0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity CROW_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity CROW_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "CROW_1_B";
|
|
|
|
tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CROW1 : VitalDelayType := 0 ns;
|
|
tpw_CROW1_posedge : VitalDelayType := 0 ns;
|
|
tpw_CROW1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; CROW1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
|
|
|
|
end CROW_1_B;
|
|
|
|
architecture Structure of CROW_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal CROW1_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
CROW_pad_1: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>CROW1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_CROW1_CROW1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CROW1_ipd,
|
|
TestSignalName => "CROW1",
|
|
Period => tperiod_CROW1,
|
|
PulseWidthHigh => tpw_CROW1_posedge,
|
|
PulseWidthLow => tpw_CROW1_negedge,
|
|
PeriodData => periodcheckinfo_CROW1,
|
|
Violation => tviol_CROW1_CROW1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => CROW1_ipd'last_event,
|
|
PathDelay => tpd_CROW1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity CROW_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity CROW_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "CROW_0_B";
|
|
|
|
tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CROW0 : VitalDelayType := 0 ns;
|
|
tpw_CROW0_posedge : VitalDelayType := 0 ns;
|
|
tpw_CROW0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; CROW0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
|
|
|
|
end CROW_0_B;
|
|
|
|
architecture Structure of CROW_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal CROW0_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
CROW_pad_0: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>CROW0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_CROW0_CROW0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CROW0_ipd,
|
|
TestSignalName => "CROW0",
|
|
Period => tperiod_CROW0,
|
|
PulseWidthHigh => tpw_CROW0_posedge,
|
|
PulseWidthLow => tpw_CROW0_negedge,
|
|
PeriodData => periodcheckinfo_CROW0,
|
|
Violation => tviol_CROW0_CROW0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => CROW0_ipd'last_event,
|
|
PathDelay => tpd_CROW0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_7_B";
|
|
|
|
tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din7 : VitalDelayType := 0 ns;
|
|
tpw_Din7_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din7_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din7: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
|
|
|
|
end Din_7_B;
|
|
|
|
architecture Structure of Din_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din7_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_7: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din7_Din7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din7_ipd,
|
|
TestSignalName => "Din7",
|
|
Period => tperiod_Din7,
|
|
PulseWidthHigh => tpw_Din7_posedge,
|
|
PulseWidthLow => tpw_Din7_negedge,
|
|
PeriodData => periodcheckinfo_Din7,
|
|
Violation => tviol_Din7_Din7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din7_ipd'last_event,
|
|
PathDelay => tpd_Din7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_6_B";
|
|
|
|
tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din6 : VitalDelayType := 0 ns;
|
|
tpw_Din6_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din6_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din6: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
|
|
|
|
end Din_6_B;
|
|
|
|
architecture Structure of Din_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din6_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_6: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din6_Din6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din6_ipd,
|
|
TestSignalName => "Din6",
|
|
Period => tperiod_Din6,
|
|
PulseWidthHigh => tpw_Din6_posedge,
|
|
PulseWidthLow => tpw_Din6_negedge,
|
|
PeriodData => periodcheckinfo_Din6,
|
|
Violation => tviol_Din6_Din6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din6_ipd'last_event,
|
|
PathDelay => tpd_Din6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_5_B";
|
|
|
|
tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din5 : VitalDelayType := 0 ns;
|
|
tpw_Din5_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din5_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din5: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
|
|
|
|
end Din_5_B;
|
|
|
|
architecture Structure of Din_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din5_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_5: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din5_Din5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din5_ipd,
|
|
TestSignalName => "Din5",
|
|
Period => tperiod_Din5,
|
|
PulseWidthHigh => tpw_Din5_posedge,
|
|
PulseWidthLow => tpw_Din5_negedge,
|
|
PeriodData => periodcheckinfo_Din5,
|
|
Violation => tviol_Din5_Din5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din5_ipd'last_event,
|
|
PathDelay => tpd_Din5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_4_B";
|
|
|
|
tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din4 : VitalDelayType := 0 ns;
|
|
tpw_Din4_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din4_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din4: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
|
|
|
|
end Din_4_B;
|
|
|
|
architecture Structure of Din_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din4_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_4: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din4_Din4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din4_ipd,
|
|
TestSignalName => "Din4",
|
|
Period => tperiod_Din4,
|
|
PulseWidthHigh => tpw_Din4_posedge,
|
|
PulseWidthLow => tpw_Din4_negedge,
|
|
PeriodData => periodcheckinfo_Din4,
|
|
Violation => tviol_Din4_Din4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din4_ipd'last_event,
|
|
PathDelay => tpd_Din4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_3_B";
|
|
|
|
tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din3 : VitalDelayType := 0 ns;
|
|
tpw_Din3_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din3_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din3: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
|
|
|
|
end Din_3_B;
|
|
|
|
architecture Structure of Din_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din3_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_3: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din3_Din3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din3_ipd,
|
|
TestSignalName => "Din3",
|
|
Period => tperiod_Din3,
|
|
PulseWidthHigh => tpw_Din3_posedge,
|
|
PulseWidthLow => tpw_Din3_negedge,
|
|
PeriodData => periodcheckinfo_Din3,
|
|
Violation => tviol_Din3_Din3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din3_ipd'last_event,
|
|
PathDelay => tpd_Din3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_2_B";
|
|
|
|
tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din2 : VitalDelayType := 0 ns;
|
|
tpw_Din2_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din2_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din2: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
|
|
|
|
end Din_2_B;
|
|
|
|
architecture Structure of Din_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din2_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_2: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din2_Din2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din2_ipd,
|
|
TestSignalName => "Din2",
|
|
Period => tperiod_Din2,
|
|
PulseWidthHigh => tpw_Din2_posedge,
|
|
PulseWidthLow => tpw_Din2_negedge,
|
|
PeriodData => periodcheckinfo_Din2,
|
|
Violation => tviol_Din2_Din2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din2_ipd'last_event,
|
|
PathDelay => tpd_Din2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_1_B";
|
|
|
|
tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din1 : VitalDelayType := 0 ns;
|
|
tpw_Din1_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
|
|
|
|
end Din_1_B;
|
|
|
|
architecture Structure of Din_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din1_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_1: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din1_Din1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din1_ipd,
|
|
TestSignalName => "Din1",
|
|
Period => tperiod_Din1,
|
|
PulseWidthHigh => tpw_Din1_posedge,
|
|
PulseWidthLow => tpw_Din1_negedge,
|
|
PeriodData => periodcheckinfo_Din1,
|
|
Violation => tviol_Din1_Din1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din1_ipd'last_event,
|
|
PathDelay => tpd_Din1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_0_B";
|
|
|
|
tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din0 : VitalDelayType := 0 ns;
|
|
tpw_Din0_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
|
|
|
|
end Din_0_B;
|
|
|
|
architecture Structure of Din_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din0_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_0: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>Din0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din0_Din0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din0_ipd,
|
|
TestSignalName => "Din0",
|
|
Period => tperiod_Din0,
|
|
PulseWidthHigh => tpw_Din0_posedge,
|
|
PulseWidthLow => tpw_Din0_negedge,
|
|
PeriodData => periodcheckinfo_Din0,
|
|
Violation => tviol_Din0_Din0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din0_ipd'last_event,
|
|
PathDelay => tpd_Din0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nCCASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nCCASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nCCASB";
|
|
|
|
tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nCCASS : VitalDelayType := 0 ns;
|
|
tpw_nCCASS_posedge : VitalDelayType := 0 ns;
|
|
tpw_nCCASS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nCCASS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
|
|
|
|
end nCCASB;
|
|
|
|
architecture Structure of nCCASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nCCASS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nCCAS_pad: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nCCASS_nCCASS : x01 := '0';
|
|
VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nCCASS_ipd,
|
|
TestSignalName => "nCCASS",
|
|
Period => tperiod_nCCASS,
|
|
PulseWidthHigh => tpw_nCCASS_posedge,
|
|
PulseWidthLow => tpw_nCCASS_negedge,
|
|
PeriodData => periodcheckinfo_nCCASS,
|
|
Violation => tviol_nCCASS_nCCASS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event,
|
|
PathDelay => tpd_nCCASS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nCRASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nCRASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nCRASB";
|
|
|
|
tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nCRASS : VitalDelayType := 0 ns;
|
|
tpw_nCRASS_posedge : VitalDelayType := 0 ns;
|
|
tpw_nCRASS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nCRASS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
|
|
|
|
end nCRASB;
|
|
|
|
architecture Structure of nCRASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nCRASS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nCRAS_pad: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nCRASS_nCRASS : x01 := '0';
|
|
VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nCRASS_ipd,
|
|
TestSignalName => "nCRASS",
|
|
Period => tperiod_nCRASS,
|
|
PulseWidthHigh => tpw_nCRASS_posedge,
|
|
PulseWidthLow => tpw_nCRASS_negedge,
|
|
PeriodData => periodcheckinfo_nCRASS,
|
|
Violation => tviol_nCRASS_nCRASS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event,
|
|
PathDelay => tpd_nCRASS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nFWEB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nFWEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nFWEB";
|
|
|
|
tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nFWES : VitalDelayType := 0 ns;
|
|
tpw_nFWES_posedge : VitalDelayType := 0 ns;
|
|
tpw_nFWES_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nFWES: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
|
|
|
|
end nFWEB;
|
|
|
|
architecture Structure of nFWEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nFWES_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nFWE_pad: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>nFWES_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nFWES_nFWES : x01 := '0';
|
|
VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nFWES_ipd,
|
|
TestSignalName => "nFWES",
|
|
Period => tperiod_nFWES,
|
|
PulseWidthHigh => tpw_nFWES_posedge,
|
|
PulseWidthLow => tpw_nFWES_negedge,
|
|
PeriodData => periodcheckinfo_nFWES,
|
|
Violation => tviol_nFWES_nFWES,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nFWES_ipd'last_event,
|
|
PathDelay => tpd_nFWES_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RCLKB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RCLKB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RCLKB";
|
|
|
|
tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RCLKS : VitalDelayType := 0 ns;
|
|
tpw_RCLKS_posedge : VitalDelayType := 0 ns;
|
|
tpw_RCLKS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; RCLKS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
|
|
|
|
end RCLKB;
|
|
|
|
architecture Structure of RCLKB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal RCLKS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
RCLK_pad: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RCLKS_RCLKS : x01 := '0';
|
|
VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RCLKS_ipd,
|
|
TestSignalName => "RCLKS",
|
|
Period => tperiod_RCLKS,
|
|
PulseWidthHigh => tpw_RCLKS_posedge,
|
|
PulseWidthLow => tpw_RCLKS_negedge,
|
|
PeriodData => periodcheckinfo_RCLKS,
|
|
Violation => tviol_RCLKS_RCLKS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event,
|
|
PathDelay => tpd_RCLKS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity UFMSDOB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity UFMSDOB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "UFMSDOB";
|
|
|
|
tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_UFMSDOS : VitalDelayType := 0 ns;
|
|
tpw_UFMSDOS_posedge : VitalDelayType := 0 ns;
|
|
tpw_UFMSDOS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
|
|
|
|
end UFMSDOB;
|
|
|
|
architecture Structure of UFMSDOB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal UFMSDOS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0069
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDO_pad: xo2iobuf0069
|
|
port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0';
|
|
VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => UFMSDOS_ipd,
|
|
TestSignalName => "UFMSDOS",
|
|
Period => tperiod_UFMSDOS,
|
|
PulseWidthHigh => tpw_UFMSDOS_posedge,
|
|
PulseWidthLow => tpw_UFMSDOS_negedge,
|
|
PeriodData => periodcheckinfo_UFMSDOS,
|
|
Violation => tviol_UFMSDOS_UFMSDOS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
|
|
PathDelay => tpd_UFMSDOS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RAM2GS
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RAM2GS is
|
|
port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0);
|
|
CROW: in Std_logic_vector (1 downto 0);
|
|
Din: in Std_logic_vector (7 downto 0);
|
|
Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic;
|
|
nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic;
|
|
RBA: out Std_logic_vector (1 downto 0);
|
|
RA: out Std_logic_vector (11 downto 0);
|
|
RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic;
|
|
RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic;
|
|
nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic;
|
|
RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic;
|
|
UFMSDI: out Std_logic; UFMSDO: in Std_logic);
|
|
|
|
|
|
|
|
end RAM2GS;
|
|
|
|
architecture Structure of RAM2GS is
|
|
signal FS_14: Std_logic;
|
|
signal FS_13: Std_logic;
|
|
signal n81: Std_logic;
|
|
signal n82: Std_logic;
|
|
signal RCLK_c: Std_logic;
|
|
signal n1998: Std_logic;
|
|
signal n1999: Std_logic;
|
|
signal FS_12: Std_logic;
|
|
signal FS_11: Std_logic;
|
|
signal n83: Std_logic;
|
|
signal n84: Std_logic;
|
|
signal n1997: Std_logic;
|
|
signal FS_8: Std_logic;
|
|
signal FS_7: Std_logic;
|
|
signal n87: Std_logic;
|
|
signal n88: Std_logic;
|
|
signal n1995: Std_logic;
|
|
signal n1996: Std_logic;
|
|
signal FS_6: Std_logic;
|
|
signal FS_5: Std_logic;
|
|
signal n89: Std_logic;
|
|
signal n90: Std_logic;
|
|
signal n1994: Std_logic;
|
|
signal FS_2: Std_logic;
|
|
signal FS_1: Std_logic;
|
|
signal n93: Std_logic;
|
|
signal n94: Std_logic;
|
|
signal n1992: Std_logic;
|
|
signal n1993: Std_logic;
|
|
signal FS_0: Std_logic;
|
|
signal n95: Std_logic;
|
|
signal CASr2: Std_logic;
|
|
signal CASr3: Std_logic;
|
|
signal FS_10: Std_logic;
|
|
signal FS_9: Std_logic;
|
|
signal n85: Std_logic;
|
|
signal n86: Std_logic;
|
|
signal FS_17: Std_logic;
|
|
signal n78: Std_logic;
|
|
signal n2000: Std_logic;
|
|
signal FS_4: Std_logic;
|
|
signal FS_3: Std_logic;
|
|
signal n91: Std_logic;
|
|
signal n92: Std_logic;
|
|
signal FS_16: Std_logic;
|
|
signal FS_15: Std_logic;
|
|
signal n79: Std_logic;
|
|
signal n80: Std_logic;
|
|
signal Din_c_4: Std_logic;
|
|
signal Din_c_6: Std_logic;
|
|
signal Din_c_1: Std_logic;
|
|
signal Din_c_7: Std_logic;
|
|
signal n2382: Std_logic;
|
|
signal n8: Std_logic;
|
|
signal n2225: Std_logic;
|
|
signal n2180: Std_logic;
|
|
signal ADSubmitted_N_246: Std_logic;
|
|
signal PHI2_N_120_enable_2: Std_logic;
|
|
signal C1Submitted_N_237: Std_logic;
|
|
signal PHI2_c: Std_logic;
|
|
signal ADSubmitted: Std_logic;
|
|
signal n26: Std_logic;
|
|
signal MAin_c_5: Std_logic;
|
|
signal n22: Std_logic;
|
|
signal MAin_c_2: Std_logic;
|
|
signal MAin_c_1: Std_logic;
|
|
signal C1Submitted: Std_logic;
|
|
signal n2365: Std_logic;
|
|
signal nFWE_c: Std_logic;
|
|
signal n1398: Std_logic;
|
|
signal nCCAS_c: Std_logic;
|
|
signal nCCAS_N_3: Std_logic;
|
|
signal CASr: Std_logic;
|
|
signal n2254: Std_logic;
|
|
signal Din_c_5: Std_logic;
|
|
signal n2191: Std_logic;
|
|
signal n2183: Std_logic;
|
|
signal n15_adj_1: Std_logic;
|
|
signal n2208: Std_logic;
|
|
signal n2363: Std_logic;
|
|
signal CmdEnable_N_248: Std_logic;
|
|
signal PHI2_N_120_enable_1: Std_logic;
|
|
signal CmdEnable: Std_logic;
|
|
signal n2447_001_BUF1: Std_logic;
|
|
signal PHI2_N_120_enable_7: Std_logic;
|
|
signal CmdSubmitted: Std_logic;
|
|
signal n1314: Std_logic;
|
|
signal n8MEGEN: Std_logic;
|
|
signal Din_c_0: Std_logic;
|
|
signal Cmdn8MEGEN_N_264: Std_logic;
|
|
signal PHI2_N_120_enable_6: Std_logic;
|
|
signal Cmdn8MEGEN: Std_logic;
|
|
signal Din_c_3: Std_logic;
|
|
signal n2373: Std_logic;
|
|
signal nCRAS_c: Std_logic;
|
|
signal FWEr: Std_logic;
|
|
signal CBR: Std_logic;
|
|
signal n2447_000_BUF1: Std_logic;
|
|
signal RCLK_c_enable_28: Std_logic;
|
|
signal InitReady: Std_logic;
|
|
signal n2447: Std_logic;
|
|
signal RCLK_c_enable_16: Std_logic;
|
|
signal LEDEN: Std_logic;
|
|
signal nCRAS_c_inv: Std_logic;
|
|
signal RASr: Std_logic;
|
|
signal LED_c: Std_logic;
|
|
signal RASr2: Std_logic;
|
|
signal nRowColSel_N_35: Std_logic;
|
|
signal nRCAS_N_165: Std_logic;
|
|
signal Ready: Std_logic;
|
|
signal n2381: Std_logic;
|
|
signal nRCS_N_139: Std_logic;
|
|
signal n2036: Std_logic;
|
|
signal nRWE_N_177: Std_logic;
|
|
signal RA_0S: Std_logic;
|
|
signal XOR8MEG: Std_logic;
|
|
signal RA11_N_184: Std_logic;
|
|
signal RA_c: Std_logic;
|
|
signal n6_adj_2: Std_logic;
|
|
signal PHI2r2: Std_logic;
|
|
signal PHI2r3: Std_logic;
|
|
signal n15_adj_4: Std_logic;
|
|
signal RCKEEN_N_121: Std_logic;
|
|
signal RCLK_c_enable_6: Std_logic;
|
|
signal RCKEEN: Std_logic;
|
|
signal RCLK_c_enable_10: Std_logic;
|
|
signal RASr3: Std_logic;
|
|
signal RCKE_N_132: Std_logic;
|
|
signal PHI2r: Std_logic;
|
|
signal RCKE_c: Std_logic;
|
|
signal n2447_002_BUF1: Std_logic;
|
|
signal Ready_N_292: Std_logic;
|
|
signal n2267: Std_logic;
|
|
signal n13_adj_6: Std_logic;
|
|
signal CmdUFMCLK: Std_logic;
|
|
signal n1893: Std_logic;
|
|
signal UFMCLK_N_224: Std_logic;
|
|
signal n2366: Std_logic;
|
|
signal UFMCLK_c: Std_logic;
|
|
signal n10: Std_logic;
|
|
signal n7: Std_logic;
|
|
signal n4: Std_logic;
|
|
signal CmdUFMSDI: Std_logic;
|
|
signal n2174: Std_logic;
|
|
signal UFMSDI_N_231: Std_logic;
|
|
signal UFMSDI_c: Std_logic;
|
|
signal n2260: Std_logic;
|
|
signal Din_c_2: Std_logic;
|
|
signal XOR8MEG_N_110: Std_logic;
|
|
signal PHI2_N_120_enable_3: Std_logic;
|
|
signal n2375: Std_logic;
|
|
signal UFMSDO_c: Std_logic;
|
|
signal n2367: Std_logic;
|
|
signal n8MEGEN_N_91: Std_logic;
|
|
signal RCLK_c_enable_15: Std_logic;
|
|
signal nRCS_N_142: Std_logic;
|
|
signal nRCAS_N_166: Std_logic;
|
|
signal n2371: Std_logic;
|
|
signal nRCAS_N_161: Std_logic;
|
|
signal nRCAS_c: Std_logic;
|
|
signal nRCS_N_141: Std_logic;
|
|
signal nRCS_N_137: Std_logic;
|
|
signal nRCS_N_136: Std_logic;
|
|
signal nRCS_c: Std_logic;
|
|
signal n2379: Std_logic;
|
|
signal nRRAS_N_156: Std_logic;
|
|
signal nRRAS_c: Std_logic;
|
|
signal nRWE_N_178: Std_logic;
|
|
signal n1765: Std_logic;
|
|
signal nRWE_N_171: Std_logic;
|
|
signal RCLK_c_enable_5: Std_logic;
|
|
signal nRWE_c: Std_logic;
|
|
signal nRowColSel_N_34: Std_logic;
|
|
signal nRowColSel_N_33: Std_logic;
|
|
signal n2376: Std_logic;
|
|
signal n1060: Std_logic;
|
|
signal n2372: Std_logic;
|
|
signal n917: Std_logic;
|
|
signal nRowColSel: Std_logic;
|
|
signal nRowColSel_N_32: Std_logic;
|
|
signal n827: Std_logic;
|
|
signal n2227: Std_logic;
|
|
signal n1406: Std_logic;
|
|
signal Bank_3: Std_logic;
|
|
signal Bank_6: Std_logic;
|
|
signal n2287: Std_logic;
|
|
signal n13: Std_logic;
|
|
signal n2374: Std_logic;
|
|
signal n2368: Std_logic;
|
|
signal CmdUFMCS: Std_logic;
|
|
signal n64: Std_logic;
|
|
signal nUFMCS_N_199: Std_logic;
|
|
signal nUFMCS_c: Std_logic;
|
|
signal n6_adj_3: Std_logic;
|
|
signal Ready_N_296: Std_logic;
|
|
signal n2204: Std_logic;
|
|
signal n2369: Std_logic;
|
|
signal MAin_c_0: Std_logic;
|
|
signal PHI2_N_120_enable_8: Std_logic;
|
|
signal Bank_5: Std_logic;
|
|
signal n2277: Std_logic;
|
|
signal Bank_2: Std_logic;
|
|
signal n2220: Std_logic;
|
|
signal RowA_0: Std_logic;
|
|
signal RowA_1: Std_logic;
|
|
signal n2370: Std_logic;
|
|
signal n2228: Std_logic;
|
|
signal n732: Std_logic;
|
|
signal n733: Std_logic;
|
|
signal RCLK_c_enable_27: Std_logic;
|
|
signal n2055: Std_logic;
|
|
signal MAin_c_9: Std_logic;
|
|
signal MAin_c_8: Std_logic;
|
|
signal RowA_8: Std_logic;
|
|
signal RowA_9: Std_logic;
|
|
signal n2210: Std_logic;
|
|
signal nRWE_N_182: Std_logic;
|
|
signal nRCS_N_146: Std_logic;
|
|
signal n728: Std_logic;
|
|
signal n729: Std_logic;
|
|
signal n727: Std_logic;
|
|
signal n730: Std_logic;
|
|
signal n2378: Std_logic;
|
|
signal n726: Std_logic;
|
|
signal n12: Std_logic;
|
|
signal MAin_c_4: Std_logic;
|
|
signal RowA_4: Std_logic;
|
|
signal RowA_5: Std_logic;
|
|
signal n1277: Std_logic;
|
|
signal n4_adj_7: Std_logic;
|
|
signal n2377: Std_logic;
|
|
signal n738: Std_logic;
|
|
signal n737: Std_logic;
|
|
signal n14: Std_logic;
|
|
signal n15: Std_logic;
|
|
signal n6: Std_logic;
|
|
signal CROW_c_1: Std_logic;
|
|
signal CROW_c_0: Std_logic;
|
|
signal RBA_c_0: Std_logic;
|
|
signal RBA_c_1: Std_logic;
|
|
signal n7_adj_5: Std_logic;
|
|
signal n2362: Std_logic;
|
|
signal WRD_6: Std_logic;
|
|
signal WRD_7: Std_logic;
|
|
signal WRD_4: Std_logic;
|
|
signal WRD_5: Std_logic;
|
|
signal WRD_0: Std_logic;
|
|
signal WRD_1: Std_logic;
|
|
signal MAin_c_3: Std_logic;
|
|
signal RowA_2: Std_logic;
|
|
signal RowA_3: Std_logic;
|
|
signal WRD_2: Std_logic;
|
|
signal WRD_3: Std_logic;
|
|
signal RA_1_9: Std_logic;
|
|
signal Bank_0: Std_logic;
|
|
signal RDQML_c: Std_logic;
|
|
signal Bank_1: Std_logic;
|
|
signal n734: Std_logic;
|
|
signal n735: Std_logic;
|
|
signal RA_1_8: Std_logic;
|
|
signal RDQMH_c: Std_logic;
|
|
signal Bank_4: Std_logic;
|
|
signal MAin_c_7: Std_logic;
|
|
signal RowA_7: Std_logic;
|
|
signal RA_1_7: Std_logic;
|
|
signal Bank_7: Std_logic;
|
|
signal MAin_c_6: Std_logic;
|
|
signal RowA_6: Std_logic;
|
|
signal RA_1_6: Std_logic;
|
|
signal RA_1_5: Std_logic;
|
|
signal RA_1_0: Std_logic;
|
|
signal RA_1_4: Std_logic;
|
|
signal RA_1_1: Std_logic;
|
|
signal RA_1_3: Std_logic;
|
|
signal RA_1_2: Std_logic;
|
|
signal n984: Std_logic;
|
|
signal n736: Std_logic;
|
|
signal Dout_c: Std_logic;
|
|
signal Dout_0S: Std_logic;
|
|
signal Dout_1S: Std_logic;
|
|
signal Dout_2S: Std_logic;
|
|
signal Dout_3S: Std_logic;
|
|
signal Dout_4S: Std_logic;
|
|
signal Dout_5S: Std_logic;
|
|
signal Dout_6S: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component SLICE_0
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_1
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_2
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_3
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_4
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_5
|
|
port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_6
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_7
|
|
port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_8
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_9
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_10
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_15
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_16
|
|
port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_19
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_20
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_24
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_25
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_26
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_27
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_30
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_32
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_33
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_35
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_36
|
|
port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_37
|
|
port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_44
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_45
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_50
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_57
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_59
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_61
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_62
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_64
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_65
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_66
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_67
|
|
port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_68
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_69
|
|
port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_70
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component i30_SLICE_71
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
|
|
end component;
|
|
component SLICE_72
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_73
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_74
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_75
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_76
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_77
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_78
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_79
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_80
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_81
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_82
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_83
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_84
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_85
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_86
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_87
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_88
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_89
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_90
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_91
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_92
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_93
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_94
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_95
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_96
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_97
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_98
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_99
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_100
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_101
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_102
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_103
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_104
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_105
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_106
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component RD_7_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD7: inout Std_logic);
|
|
end component;
|
|
component RD_6_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD6: inout Std_logic);
|
|
end component;
|
|
component RD_5_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD5: inout Std_logic);
|
|
end component;
|
|
component RD_4_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD4: inout Std_logic);
|
|
end component;
|
|
component RD_3_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD3: inout Std_logic);
|
|
end component;
|
|
component RD_2_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD2: inout Std_logic);
|
|
end component;
|
|
component RD_1_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD1: inout Std_logic);
|
|
end component;
|
|
component RD_0_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD0: inout Std_logic);
|
|
end component;
|
|
component Dout_7_B
|
|
port (PADDO: in Std_logic; Dout7: out Std_logic);
|
|
end component;
|
|
component Dout_6_B
|
|
port (PADDO: in Std_logic; Dout6: out Std_logic);
|
|
end component;
|
|
component Dout_5_B
|
|
port (PADDO: in Std_logic; Dout5: out Std_logic);
|
|
end component;
|
|
component Dout_4_B
|
|
port (PADDO: in Std_logic; Dout4: out Std_logic);
|
|
end component;
|
|
component Dout_3_B
|
|
port (PADDO: in Std_logic; Dout3: out Std_logic);
|
|
end component;
|
|
component Dout_2_B
|
|
port (PADDO: in Std_logic; Dout2: out Std_logic);
|
|
end component;
|
|
component Dout_1_B
|
|
port (PADDO: in Std_logic; Dout1: out Std_logic);
|
|
end component;
|
|
component Dout_0_B
|
|
port (PADDO: in Std_logic; Dout0: out Std_logic);
|
|
end component;
|
|
component LEDB
|
|
port (PADDO: in Std_logic; LEDS: out Std_logic);
|
|
end component;
|
|
component RBA_1_B
|
|
port (PADDO: in Std_logic; RBA1: out Std_logic);
|
|
end component;
|
|
component RBA_0_B
|
|
port (PADDO: in Std_logic; RBA0: out Std_logic);
|
|
end component;
|
|
component RA_11_B
|
|
port (PADDO: in Std_logic; RA11: out Std_logic);
|
|
end component;
|
|
component RA_10_B
|
|
port (PADDO: in Std_logic; RA10: out Std_logic);
|
|
end component;
|
|
component RA_9_B
|
|
port (PADDO: in Std_logic; RA9: out Std_logic);
|
|
end component;
|
|
component RA_8_B
|
|
port (PADDO: in Std_logic; RA8: out Std_logic);
|
|
end component;
|
|
component RA_7_B
|
|
port (PADDO: in Std_logic; RA7: out Std_logic);
|
|
end component;
|
|
component RA_6_B
|
|
port (PADDO: in Std_logic; RA6: out Std_logic);
|
|
end component;
|
|
component RA_5_B
|
|
port (PADDO: in Std_logic; RA5: out Std_logic);
|
|
end component;
|
|
component RA_4_B
|
|
port (PADDO: in Std_logic; RA4: out Std_logic);
|
|
end component;
|
|
component RA_3_B
|
|
port (PADDO: in Std_logic; RA3: out Std_logic);
|
|
end component;
|
|
component RA_2_B
|
|
port (PADDO: in Std_logic; RA2: out Std_logic);
|
|
end component;
|
|
component RA_1_B
|
|
port (PADDO: in Std_logic; RA1: out Std_logic);
|
|
end component;
|
|
component RA_0_B
|
|
port (PADDO: in Std_logic; RA0: out Std_logic);
|
|
end component;
|
|
component nRCSB
|
|
port (PADDO: in Std_logic; nRCSS: out Std_logic);
|
|
end component;
|
|
component RCKEB
|
|
port (PADDO: in Std_logic; RCKES: out Std_logic);
|
|
end component;
|
|
component nRWEB
|
|
port (PADDO: in Std_logic; nRWES: out Std_logic);
|
|
end component;
|
|
component nRRASB
|
|
port (PADDO: in Std_logic; nRRASS: out Std_logic);
|
|
end component;
|
|
component nRCASB
|
|
port (PADDO: in Std_logic; nRCASS: out Std_logic);
|
|
end component;
|
|
component RDQMHB
|
|
port (PADDO: in Std_logic; RDQMHS: out Std_logic);
|
|
end component;
|
|
component RDQMLB
|
|
port (PADDO: in Std_logic; RDQMLS: out Std_logic);
|
|
end component;
|
|
component nUFMCSB
|
|
port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
|
|
end component;
|
|
component UFMCLKB
|
|
port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
|
|
end component;
|
|
component UFMSDIB
|
|
port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
|
|
end component;
|
|
component PHI2B
|
|
port (PADDI: out Std_logic; PHI2S: in Std_logic);
|
|
end component;
|
|
component MAin_9_B
|
|
port (PADDI: out Std_logic; MAin9: in Std_logic);
|
|
end component;
|
|
component MAin_8_B
|
|
port (PADDI: out Std_logic; MAin8: in Std_logic);
|
|
end component;
|
|
component MAin_7_B
|
|
port (PADDI: out Std_logic; MAin7: in Std_logic);
|
|
end component;
|
|
component MAin_6_B
|
|
port (PADDI: out Std_logic; MAin6: in Std_logic);
|
|
end component;
|
|
component MAin_5_B
|
|
port (PADDI: out Std_logic; MAin5: in Std_logic);
|
|
end component;
|
|
component MAin_4_B
|
|
port (PADDI: out Std_logic; MAin4: in Std_logic);
|
|
end component;
|
|
component MAin_3_B
|
|
port (PADDI: out Std_logic; MAin3: in Std_logic);
|
|
end component;
|
|
component MAin_2_B
|
|
port (PADDI: out Std_logic; MAin2: in Std_logic);
|
|
end component;
|
|
component MAin_1_B
|
|
port (PADDI: out Std_logic; MAin1: in Std_logic);
|
|
end component;
|
|
component MAin_0_B
|
|
port (PADDI: out Std_logic; MAin0: in Std_logic);
|
|
end component;
|
|
component CROW_1_B
|
|
port (PADDI: out Std_logic; CROW1: in Std_logic);
|
|
end component;
|
|
component CROW_0_B
|
|
port (PADDI: out Std_logic; CROW0: in Std_logic);
|
|
end component;
|
|
component Din_7_B
|
|
port (PADDI: out Std_logic; Din7: in Std_logic);
|
|
end component;
|
|
component Din_6_B
|
|
port (PADDI: out Std_logic; Din6: in Std_logic);
|
|
end component;
|
|
component Din_5_B
|
|
port (PADDI: out Std_logic; Din5: in Std_logic);
|
|
end component;
|
|
component Din_4_B
|
|
port (PADDI: out Std_logic; Din4: in Std_logic);
|
|
end component;
|
|
component Din_3_B
|
|
port (PADDI: out Std_logic; Din3: in Std_logic);
|
|
end component;
|
|
component Din_2_B
|
|
port (PADDI: out Std_logic; Din2: in Std_logic);
|
|
end component;
|
|
component Din_1_B
|
|
port (PADDI: out Std_logic; Din1: in Std_logic);
|
|
end component;
|
|
component Din_0_B
|
|
port (PADDI: out Std_logic; Din0: in Std_logic);
|
|
end component;
|
|
component nCCASB
|
|
port (PADDI: out Std_logic; nCCASS: in Std_logic);
|
|
end component;
|
|
component nCRASB
|
|
port (PADDI: out Std_logic; nCRASS: in Std_logic);
|
|
end component;
|
|
component nFWEB
|
|
port (PADDI: out Std_logic; nFWES: in Std_logic);
|
|
end component;
|
|
component RCLKB
|
|
port (PADDI: out Std_logic; RCLKS: in Std_logic);
|
|
end component;
|
|
component UFMSDOB
|
|
port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
|
|
end component;
|
|
begin
|
|
SLICE_0I: SLICE_0
|
|
port map (A1=>FS_14, A0=>FS_13, DI1=>n81, DI0=>n82, CLK=>RCLK_c,
|
|
FCI=>n1998, F0=>n82, Q0=>FS_13, F1=>n81, Q1=>FS_14, FCO=>n1999);
|
|
SLICE_1I: SLICE_1
|
|
port map (A1=>FS_12, A0=>FS_11, DI1=>n83, DI0=>n84, CLK=>RCLK_c,
|
|
FCI=>n1997, F0=>n84, Q0=>FS_11, F1=>n83, Q1=>FS_12, FCO=>n1998);
|
|
SLICE_2I: SLICE_2
|
|
port map (A1=>FS_8, A0=>FS_7, DI1=>n87, DI0=>n88, CLK=>RCLK_c,
|
|
FCI=>n1995, F0=>n88, Q0=>FS_7, F1=>n87, Q1=>FS_8, FCO=>n1996);
|
|
SLICE_3I: SLICE_3
|
|
port map (A1=>FS_6, A0=>FS_5, DI1=>n89, DI0=>n90, CLK=>RCLK_c,
|
|
FCI=>n1994, F0=>n90, Q0=>FS_5, F1=>n89, Q1=>FS_6, FCO=>n1995);
|
|
SLICE_4I: SLICE_4
|
|
port map (A1=>FS_2, A0=>FS_1, DI1=>n93, DI0=>n94, CLK=>RCLK_c,
|
|
FCI=>n1992, F0=>n94, Q0=>FS_1, F1=>n93, Q1=>FS_2, FCO=>n1993);
|
|
SLICE_5I: SLICE_5
|
|
port map (A1=>FS_0, DI1=>n95, M0=>CASr2, CLK=>RCLK_c, Q0=>CASr3, F1=>n95,
|
|
Q1=>FS_0, FCO=>n1992);
|
|
SLICE_6I: SLICE_6
|
|
port map (A1=>FS_10, A0=>FS_9, DI1=>n85, DI0=>n86, CLK=>RCLK_c,
|
|
FCI=>n1996, F0=>n86, Q0=>FS_9, F1=>n85, Q1=>FS_10, FCO=>n1997);
|
|
SLICE_7I: SLICE_7
|
|
port map (A0=>FS_17, DI0=>n78, CLK=>RCLK_c, FCI=>n2000, F0=>n78,
|
|
Q0=>FS_17);
|
|
SLICE_8I: SLICE_8
|
|
port map (A1=>FS_4, A0=>FS_3, DI1=>n91, DI0=>n92, CLK=>RCLK_c,
|
|
FCI=>n1993, F0=>n92, Q0=>FS_3, F1=>n91, Q1=>FS_4, FCO=>n1994);
|
|
SLICE_9I: SLICE_9
|
|
port map (A1=>FS_16, A0=>FS_15, DI1=>n79, DI0=>n80, CLK=>RCLK_c,
|
|
FCI=>n1999, F0=>n80, Q0=>FS_15, F1=>n79, Q1=>FS_16, FCO=>n2000);
|
|
SLICE_10I: SLICE_10
|
|
port map (D1=>Din_c_4, C1=>Din_c_6, B1=>Din_c_1, A1=>Din_c_7, D0=>n2382,
|
|
C0=>n8, B0=>n2225, A0=>n2180, DI0=>ADSubmitted_N_246,
|
|
CE=>PHI2_N_120_enable_2, LSR=>C1Submitted_N_237, CLK=>PHI2_c,
|
|
F0=>ADSubmitted_N_246, Q0=>ADSubmitted, F1=>n8);
|
|
SLICE_15I: SLICE_15
|
|
port map (D1=>n26, C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1,
|
|
C0=>C1Submitted, B0=>n2365, A0=>nFWE_c, DI0=>n1398,
|
|
LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1398,
|
|
Q0=>C1Submitted, F1=>n2365);
|
|
SLICE_16I: SLICE_16
|
|
port map (A0=>nCCAS_c, DI0=>nCCAS_N_3, M1=>CASr, CLK=>RCLK_c,
|
|
F0=>nCCAS_N_3, Q0=>CASr, Q1=>CASr2);
|
|
SLICE_19I: SLICE_19
|
|
port map (D1=>n2254, C1=>Din_c_5, B1=>n2191, A1=>n2183, D0=>n15_adj_1,
|
|
C0=>n2208, B0=>MAin_c_1, A0=>n2363, DI0=>CmdEnable_N_248,
|
|
CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>CmdEnable_N_248,
|
|
Q0=>CmdEnable, F1=>n15_adj_1);
|
|
SLICE_20I: SLICE_20
|
|
port map (DI0=>n2447_001_BUF1, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c,
|
|
F0=>n2447_001_BUF1, Q0=>CmdSubmitted);
|
|
SLICE_24I: SLICE_24
|
|
port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4,
|
|
B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264,
|
|
CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264,
|
|
Q0=>Cmdn8MEGEN, F1=>n1314);
|
|
SLICE_25I: SLICE_25
|
|
port map (C1=>Din_c_3, B1=>Din_c_5, A1=>nFWE_c, A0=>nFWE_c, DI0=>n2373,
|
|
M1=>nCCAS_N_3, CLK=>nCRAS_c, F0=>n2373, Q0=>FWEr, F1=>n2180,
|
|
Q1=>CBR);
|
|
SLICE_26I: SLICE_26
|
|
port map (DI0=>n2447_000_BUF1, CE=>RCLK_c_enable_28, CLK=>RCLK_c,
|
|
F0=>n2447_000_BUF1, Q0=>InitReady);
|
|
SLICE_27I: SLICE_27
|
|
port map (DI0=>n2447, CE=>RCLK_c_enable_16, CLK=>RCLK_c, F0=>n2447,
|
|
Q0=>LEDEN);
|
|
SLICE_30I: SLICE_30
|
|
port map (C1=>CBR, B1=>LEDEN, A1=>nCRAS_c, A0=>nCRAS_c, DI0=>nCRAS_c_inv,
|
|
M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_inv, Q0=>RASr, F1=>LED_c,
|
|
Q1=>RASr2);
|
|
SLICE_32I: SLICE_32
|
|
port map (C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, D0=>nRCAS_N_165,
|
|
C0=>Ready, B0=>n2381, A0=>nRCS_N_139, DI0=>n2036,
|
|
LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2036, Q0=>RA_0S, F1=>n2381);
|
|
SLICE_33I: SLICE_33
|
|
port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN,
|
|
B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready,
|
|
CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n6_adj_2);
|
|
SLICE_35I: SLICE_35
|
|
port map (D1=>InitReady, C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3,
|
|
C0=>Ready, B0=>n15_adj_4, A0=>InitReady, DI0=>RCKEEN_N_121,
|
|
CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN,
|
|
F1=>RCLK_c_enable_10);
|
|
SLICE_36I: SLICE_36
|
|
port map (D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132,
|
|
M1=>PHI2r, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, Q1=>PHI2r2);
|
|
SLICE_37I: SLICE_37
|
|
port map (DI0=>n2447_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c,
|
|
F0=>n2447_002_BUF1, Q0=>Ready);
|
|
SLICE_44I: SLICE_44
|
|
port map (D1=>FS_1, C1=>n2267, B1=>n13_adj_6, A1=>FS_4, C0=>InitReady,
|
|
B0=>CmdUFMCLK, A0=>n1893, DI0=>UFMCLK_N_224,
|
|
CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c,
|
|
F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1893);
|
|
SLICE_45I: SLICE_45
|
|
port map (D1=>n10, C1=>FS_10, B1=>FS_8, A1=>n7, D0=>n4, C0=>InitReady,
|
|
B0=>CmdUFMSDI, A0=>n2174, DI0=>UFMSDI_N_231,
|
|
CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c,
|
|
F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2174);
|
|
SLICE_50I: SLICE_50
|
|
port map (D1=>LEDEN, C1=>n1314, B1=>Din_c_1, A1=>Din_c_4, D0=>Din_c_3,
|
|
C0=>n2260, B0=>Din_c_2, A0=>Din_c_0, DI0=>XOR8MEG_N_110,
|
|
CE=>PHI2_N_120_enable_3, CLK=>PHI2_c, F0=>XOR8MEG_N_110,
|
|
Q0=>XOR8MEG, F1=>n2260);
|
|
SLICE_57I: SLICE_57
|
|
port map (D1=>FS_10, C1=>FS_11, B1=>n2375, A1=>n10, D0=>Cmdn8MEGEN,
|
|
C0=>UFMSDO_c, B0=>n2367, A0=>InitReady, DI0=>n8MEGEN_N_91,
|
|
CE=>RCLK_c_enable_15, CLK=>RCLK_c, F0=>n8MEGEN_N_91,
|
|
Q0=>n8MEGEN, F1=>n2367);
|
|
SLICE_59I: SLICE_59
|
|
port map (D1=>CBR, C1=>nRowColSel_N_35, B1=>RASr2, A1=>nRCS_N_142,
|
|
D0=>nRCAS_N_166, C0=>Ready, B0=>nRCAS_N_165, A0=>n2371,
|
|
DI0=>nRCAS_N_161, CE=>RCLK_c_enable_6, CLK=>RCLK_c,
|
|
F0=>nRCAS_N_161, Q0=>nRCAS_c, F1=>nRCAS_N_166);
|
|
SLICE_61I: SLICE_61
|
|
port map (D1=>nRCS_N_142, C1=>nRowColSel_N_35, B1=>RASr2, A1=>RCKE_c,
|
|
C0=>Ready, B0=>nRCS_N_141, A0=>nRCS_N_137, DI0=>nRCS_N_136,
|
|
CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c,
|
|
F1=>nRCS_N_141);
|
|
SLICE_62I: SLICE_62
|
|
port map (D1=>RASr2, C1=>nRowColSel_N_35, B1=>InitReady, A1=>nRCS_N_139,
|
|
D0=>nRowColSel_N_35, C0=>Ready, B0=>n2379, A0=>nRCS_N_137,
|
|
DI0=>nRRAS_N_156, CE=>RCLK_c_enable_6, CLK=>RCLK_c,
|
|
F0=>nRRAS_N_156, Q0=>nRRAS_c, F1=>nRCS_N_137);
|
|
SLICE_64I: SLICE_64
|
|
port map (B1=>nRCAS_N_165, A1=>nRWE_N_177, D0=>n2371, C0=>Ready,
|
|
B0=>nRWE_N_178, A0=>n1765, DI0=>nRWE_N_171,
|
|
CE=>RCLK_c_enable_5, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c,
|
|
F1=>n1765);
|
|
SLICE_65I: SLICE_65
|
|
port map (B1=>nRowColSel_N_34, A1=>nRowColSel_N_33, D0=>n2376, C0=>n1060,
|
|
B0=>n2372, A0=>FWEr, DI0=>n917, CE=>RCLK_c_enable_5,
|
|
CLK=>RCLK_c, F0=>n917, Q0=>nRowColSel, F1=>n1060);
|
|
SLICE_66I: SLICE_66
|
|
port map (B1=>CASr2, A1=>nRowColSel_N_33, B0=>nRowColSel_N_32,
|
|
A0=>nRowColSel_N_33, DI0=>n827, LSR=>RASr2, CLK=>RCLK_c,
|
|
F0=>n827, Q0=>nRowColSel_N_32, F1=>n2227);
|
|
SLICE_67I: SLICE_67
|
|
port map (B0=>nRowColSel_N_32, A0=>RASr2, DI0=>n1406,
|
|
LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1406,
|
|
Q0=>nRowColSel_N_33);
|
|
SLICE_68I: SLICE_68
|
|
port map (B1=>FS_0, A1=>FS_8, B0=>Bank_3, A0=>Bank_6, M0=>n1406,
|
|
LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n2287,
|
|
Q0=>nRowColSel_N_34, F1=>n13);
|
|
SLICE_69I: SLICE_69
|
|
port map (B1=>RASr2, A1=>RCKE_c, A0=>RASr2, DI0=>n2374, M1=>PHI2r2,
|
|
CLK=>RCLK_c, F0=>n2374, Q0=>nRowColSel_N_35, F1=>n2379,
|
|
Q1=>PHI2r3);
|
|
SLICE_70I: SLICE_70
|
|
port map (D1=>FS_10, C1=>InitReady, B1=>n2368, A1=>FS_11, D0=>InitReady,
|
|
C0=>CmdUFMCS, B0=>n64, A0=>n13_adj_6, DI0=>nUFMCS_N_199,
|
|
CE=>RCLK_c_enable_10, CLK=>RCLK_c, F0=>nUFMCS_N_199,
|
|
Q0=>nUFMCS_c, F1=>n64);
|
|
i30_SLICE_71I: i30_SLICE_71
|
|
port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr,
|
|
B0=>n2227, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>n15_adj_4);
|
|
SLICE_72I: SLICE_72
|
|
port map (D1=>Ready, C1=>nRowColSel_N_32, B1=>n6_adj_3, A1=>RASr2,
|
|
B0=>Ready_N_296, A0=>InitReady, F0=>n6_adj_3, F1=>Ready_N_292);
|
|
SLICE_73I: SLICE_73
|
|
port map (D1=>n2204, C1=>n2180, B1=>n26, A1=>n2369, D0=>n6_adj_2,
|
|
C0=>CmdEnable, B0=>MAin_c_0, A0=>MAin_c_1, F0=>n2204,
|
|
F1=>PHI2_N_120_enable_8);
|
|
SLICE_74I: SLICE_74
|
|
port map (D1=>Bank_5, C1=>n2287, B1=>n2277, A1=>Bank_2, D0=>nFWE_c,
|
|
C0=>n2204, B0=>n26, A0=>n2369, M1=>MAin_c_1, M0=>MAin_c_0,
|
|
LSR=>Ready, CLK=>nCRAS_c, F0=>n2220, Q0=>RowA_0, F1=>n26,
|
|
Q1=>RowA_1);
|
|
SLICE_75I: SLICE_75
|
|
port map (D1=>n2370, C1=>n2183, B1=>n2228, A1=>Din_c_5, B0=>Din_c_3,
|
|
A0=>Din_c_6, M1=>n732, M0=>n733, CE=>RCLK_c_enable_27,
|
|
CLK=>RCLK_c, F0=>n2183, Q0=>n732, F1=>n2055, Q1=>nRWE_N_177);
|
|
SLICE_76I: SLICE_76
|
|
port map (C1=>n10, B1=>FS_14, A1=>FS_12, D0=>InitReady, C0=>n2368,
|
|
B0=>FS_11, A0=>FS_10, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready,
|
|
CLK=>nCRAS_c, F0=>RCLK_c_enable_16, Q0=>RowA_8, F1=>n2368,
|
|
Q1=>RowA_9);
|
|
SLICE_77I: SLICE_77
|
|
port map (D1=>n2208, C1=>C1Submitted, B1=>n2191, A1=>Din_c_5,
|
|
D0=>MAin_c_0, C0=>Din_c_6, B0=>Din_c_3, A0=>Din_c_2, F0=>n2191,
|
|
F1=>n2210);
|
|
SLICE_78I: SLICE_78
|
|
port map (D1=>nRowColSel_N_35, C1=>nRWE_N_182, B1=>n1060, A1=>nRCS_N_146,
|
|
B0=>RASr2, A0=>RCKE_c, M1=>n728, M0=>n729,
|
|
CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRWE_N_182, Q0=>n728,
|
|
F1=>nRWE_N_178, Q1=>n727);
|
|
SLICE_79I: SLICE_79
|
|
port map (C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, C0=>nFWE_c,
|
|
B0=>n26, A0=>n2369, M1=>n730, M0=>nRWE_N_177,
|
|
CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>PHI2_N_120_enable_2,
|
|
Q0=>n730, F1=>n2369, Q1=>n729);
|
|
SLICE_80I: SLICE_80
|
|
port map (B1=>FS_14, A1=>FS_12, D0=>FS_11, C0=>InitReady, B0=>n2375,
|
|
A0=>n10, F0=>n2366, F1=>n2375);
|
|
SLICE_81I: SLICE_81
|
|
port map (B1=>CBR, A1=>FWEr, D0=>nRowColSel_N_33, C0=>n2378,
|
|
B0=>nRowColSel_N_34, A0=>nRCS_N_146, M1=>n726, M0=>n727,
|
|
CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRCS_N_142, Q0=>n726,
|
|
F1=>n2378, Q1=>Ready_N_296);
|
|
SLICE_82I: SLICE_82
|
|
port map (D1=>FS_17, C1=>FS_14, B1=>n12, A1=>FS_11, B0=>n13_adj_6,
|
|
A0=>FS_10, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready,
|
|
CLK=>nCRAS_c, F0=>RCLK_c_enable_28, Q0=>RowA_4, F1=>n13_adj_6,
|
|
Q1=>RowA_5);
|
|
SLICE_83I: SLICE_83
|
|
port map (D1=>n1314, C1=>n1277, B1=>CmdEnable, A1=>n2228, D0=>MAin_c_1,
|
|
C0=>MAin_c_0, B0=>n26, A0=>n2369, F0=>n1277,
|
|
F1=>PHI2_N_120_enable_3);
|
|
SLICE_84I: SLICE_84
|
|
port map (C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, D0=>n4_adj_7,
|
|
C0=>InitReady, B0=>n2377, A0=>n2367, M1=>n738, M0=>nRCAS_N_165,
|
|
CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RCLK_c_enable_15,
|
|
Q0=>n738, F1=>n2377, Q1=>n737);
|
|
SLICE_85I: SLICE_85
|
|
port map (D1=>n10, C1=>FS_11, B1=>FS_14, A1=>FS_12, D0=>FS_16, C0=>FS_15,
|
|
B0=>FS_13, A0=>FS_17, F0=>n10, F1=>n2267);
|
|
SLICE_86I: SLICE_86
|
|
port map (C1=>FS_6, B1=>FS_9, A1=>FS_3, D0=>n14, C0=>n13, B0=>n15,
|
|
A0=>FS_4, M1=>RASr2, M0=>PHI2_c, CLK=>RCLK_c, F0=>n4_adj_7,
|
|
Q0=>PHI2r, F1=>n14, Q1=>RASr3);
|
|
SLICE_87I: SLICE_87
|
|
port map (D1=>n6, C1=>nRowColSel_N_32, B1=>nRowColSel_N_33,
|
|
A1=>nRowColSel_N_35, B0=>nRowColSel_N_34, A0=>Ready,
|
|
M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n6,
|
|
Q0=>RBA_c_0, F1=>RCLK_c_enable_6, Q1=>RBA_c_1);
|
|
SLICE_88I: SLICE_88
|
|
port map (D1=>n2363, C1=>C1Submitted_N_237, B1=>ADSubmitted,
|
|
A1=>n7_adj_5, D0=>n2362, C0=>MAin_c_0, B0=>n2055, A0=>Din_c_2,
|
|
M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>C1Submitted_N_237,
|
|
Q0=>WRD_6, F1=>PHI2_N_120_enable_1, Q1=>WRD_7);
|
|
SLICE_89I: SLICE_89
|
|
port map (D1=>Din_c_5, C1=>Din_c_3, B1=>Din_c_4, A1=>n2220, D0=>Din_c_3,
|
|
C0=>Din_c_4, B0=>n2220, A0=>Din_c_5, M1=>Din_c_5, M0=>Din_c_4,
|
|
CLK=>nCCAS_c, F0=>PHI2_N_120_enable_6, Q0=>WRD_4,
|
|
F1=>PHI2_N_120_enable_7, Q1=>WRD_5);
|
|
SLICE_90I: SLICE_90
|
|
port map (D1=>Din_c_0, C1=>Din_c_4, B1=>Din_c_1, A1=>Din_c_7,
|
|
C0=>Din_c_0, B0=>Din_c_1, A0=>Din_c_7, M1=>Din_c_1,
|
|
M0=>Din_c_0, CLK=>nCCAS_c, F0=>n2370, Q0=>WRD_0, F1=>n2208,
|
|
Q1=>WRD_1);
|
|
SLICE_91I: SLICE_91
|
|
port map (C1=>MAin_c_1, B1=>n26, A1=>n2369, D0=>MAin_c_1, C0=>MAin_c_0,
|
|
B0=>n26, A0=>n2369, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready,
|
|
CLK=>nCRAS_c, F0=>n2225, Q0=>RowA_2, F1=>n2362, Q1=>RowA_3);
|
|
SLICE_92I: SLICE_92
|
|
port map (D1=>Ready, C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2,
|
|
D0=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>InitReady, A0=>RASr2,
|
|
M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>n2371, Q0=>WRD_2,
|
|
F1=>RCLK_c_enable_27, Q1=>WRD_3);
|
|
SLICE_93I: SLICE_93
|
|
port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9,
|
|
A0=>RowA_9, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>RA_1_9,
|
|
Q0=>Bank_0, F1=>RDQML_c, Q1=>Bank_1);
|
|
SLICE_94I: SLICE_94
|
|
port map (B1=>nRowColSel_N_35, A1=>Ready, D0=>nRowColSel_N_35,
|
|
C0=>nRowColSel_N_32, B0=>n1060, A0=>Ready, F0=>RCLK_c_enable_5,
|
|
F1=>n2372);
|
|
SLICE_95I: SLICE_95
|
|
port map (D1=>FS_5, C1=>FS_9, B1=>FS_7, A1=>n2375, D0=>FS_2, C0=>FS_1,
|
|
B0=>FS_7, A0=>FS_5, F0=>n15, F1=>n7);
|
|
SLICE_96I: SLICE_96
|
|
port map (B1=>CASr3, A1=>CBR, D0=>CASr2, C0=>FWEr, B0=>CASr3, A0=>CBR,
|
|
F0=>nRCS_N_146, F1=>n2376);
|
|
SLICE_97I: SLICE_97
|
|
port map (C1=>MAin_c_1, B1=>n2210, A1=>MAin_c_0, B0=>Din_c_2,
|
|
A0=>MAin_c_0, M1=>n734, M0=>n735, CE=>RCLK_c_enable_27,
|
|
CLK=>RCLK_c, F0=>n2254, Q0=>n734, F1=>n7_adj_5, Q1=>n733);
|
|
SLICE_98I: SLICE_98
|
|
port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_8,
|
|
A0=>RowA_8, M1=>nRCS_N_139, M0=>Ready_N_296,
|
|
CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RA_1_8, Q0=>nRCS_N_139,
|
|
F1=>RDQMH_c, Q1=>nRCAS_N_165);
|
|
SLICE_99I: SLICE_99
|
|
port map (D1=>Bank_1, C1=>Bank_4, B1=>MAin_c_3, A1=>MAin_c_7,
|
|
C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M0=>Din_c_0,
|
|
CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_7,
|
|
Q0=>CmdUFMSDI, F1=>n22);
|
|
SLICE_100I: SLICE_100
|
|
port map (D1=>Bank_0, C1=>Bank_7, B1=>MAin_c_4, A1=>MAin_c_6,
|
|
C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_2,
|
|
M0=>Din_c_1, CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_6,
|
|
Q0=>CmdUFMCLK, F1=>n2277, Q1=>CmdUFMCS);
|
|
SLICE_101I: SLICE_101
|
|
port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel,
|
|
B0=>MAin_c_5, A0=>RowA_5, M1=>Din_c_7, M0=>Din_c_6,
|
|
CLK=>PHI2_c, F0=>RA_1_5, Q0=>Bank_6, F1=>RA_1_0, Q1=>Bank_7);
|
|
SLICE_102I: SLICE_102
|
|
port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel,
|
|
B0=>MAin_c_4, A0=>RowA_4, M1=>Din_c_5, M0=>Din_c_4,
|
|
CLK=>PHI2_c, F0=>RA_1_4, Q0=>Bank_4, F1=>RA_1_1, Q1=>Bank_5);
|
|
SLICE_103I: SLICE_103
|
|
port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel,
|
|
B0=>MAin_c_3, A0=>RowA_3, M1=>Din_c_3, M0=>Din_c_2,
|
|
CLK=>PHI2_c, F0=>RA_1_3, Q0=>Bank_2, F1=>RA_1_2, Q1=>Bank_3);
|
|
SLICE_104I: SLICE_104
|
|
port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>nFWE_c, B0=>n26, A0=>n2369,
|
|
M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c,
|
|
F0=>n2363, Q0=>RowA_6, F1=>n984, Q1=>RowA_7);
|
|
SLICE_105I: SLICE_105
|
|
port map (B1=>FS_6, A1=>FS_11, D0=>FS_16, C0=>FS_15, B0=>FS_12,
|
|
A0=>FS_13, F0=>n12, F1=>n4);
|
|
SLICE_106I: SLICE_106
|
|
port map (B1=>Din_c_2, A1=>Din_c_0, B0=>Din_c_4, A0=>nFWE_c, M1=>n736,
|
|
M0=>n737, CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>n2228,
|
|
Q0=>n736, F1=>n2382, Q1=>n735);
|
|
RD_7_I: RD_7_B
|
|
port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7));
|
|
RD_6_I: RD_6_B
|
|
port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6));
|
|
RD_5_I: RD_5_B
|
|
port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5));
|
|
RD_4_I: RD_4_B
|
|
port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4));
|
|
RD_3_I: RD_3_B
|
|
port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3));
|
|
RD_2_I: RD_2_B
|
|
port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2));
|
|
RD_1_I: RD_1_B
|
|
port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1));
|
|
RD_0_I: RD_0_B
|
|
port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0));
|
|
Dout_7_I: Dout_7_B
|
|
port map (PADDO=>Dout_c, Dout7=>Dout(7));
|
|
Dout_6_I: Dout_6_B
|
|
port map (PADDO=>Dout_0S, Dout6=>Dout(6));
|
|
Dout_5_I: Dout_5_B
|
|
port map (PADDO=>Dout_1S, Dout5=>Dout(5));
|
|
Dout_4_I: Dout_4_B
|
|
port map (PADDO=>Dout_2S, Dout4=>Dout(4));
|
|
Dout_3_I: Dout_3_B
|
|
port map (PADDO=>Dout_3S, Dout3=>Dout(3));
|
|
Dout_2_I: Dout_2_B
|
|
port map (PADDO=>Dout_4S, Dout2=>Dout(2));
|
|
Dout_1_I: Dout_1_B
|
|
port map (PADDO=>Dout_5S, Dout1=>Dout(1));
|
|
Dout_0_I: Dout_0_B
|
|
port map (PADDO=>Dout_6S, Dout0=>Dout(0));
|
|
LEDI: LEDB
|
|
port map (PADDO=>LED_c, LEDS=>LED);
|
|
RBA_1_I: RBA_1_B
|
|
port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
|
|
RBA_0_I: RBA_0_B
|
|
port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
|
|
RA_11_I: RA_11_B
|
|
port map (PADDO=>RA_c, RA11=>RA(11));
|
|
RA_10_I: RA_10_B
|
|
port map (PADDO=>RA_0S, RA10=>RA(10));
|
|
RA_9_I: RA_9_B
|
|
port map (PADDO=>RA_1_9, RA9=>RA(9));
|
|
RA_8_I: RA_8_B
|
|
port map (PADDO=>RA_1_8, RA8=>RA(8));
|
|
RA_7_I: RA_7_B
|
|
port map (PADDO=>RA_1_7, RA7=>RA(7));
|
|
RA_6_I: RA_6_B
|
|
port map (PADDO=>RA_1_6, RA6=>RA(6));
|
|
RA_5_I: RA_5_B
|
|
port map (PADDO=>RA_1_5, RA5=>RA(5));
|
|
RA_4_I: RA_4_B
|
|
port map (PADDO=>RA_1_4, RA4=>RA(4));
|
|
RA_3_I: RA_3_B
|
|
port map (PADDO=>RA_1_3, RA3=>RA(3));
|
|
RA_2_I: RA_2_B
|
|
port map (PADDO=>RA_1_2, RA2=>RA(2));
|
|
RA_1_I: RA_1_B
|
|
port map (PADDO=>RA_1_1, RA1=>RA(1));
|
|
RA_0_I: RA_0_B
|
|
port map (PADDO=>RA_1_0, RA0=>RA(0));
|
|
nRCSI: nRCSB
|
|
port map (PADDO=>nRCS_c, nRCSS=>nRCS);
|
|
RCKEI: RCKEB
|
|
port map (PADDO=>RCKE_c, RCKES=>RCKE);
|
|
nRWEI: nRWEB
|
|
port map (PADDO=>nRWE_c, nRWES=>nRWE);
|
|
nRRASI: nRRASB
|
|
port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
|
|
nRCASI: nRCASB
|
|
port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
|
|
RDQMHI: RDQMHB
|
|
port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
|
|
RDQMLI: RDQMLB
|
|
port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
|
|
nUFMCSI: nUFMCSB
|
|
port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
|
|
UFMCLKI: UFMCLKB
|
|
port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
|
|
UFMSDII: UFMSDIB
|
|
port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
|
|
PHI2I: PHI2B
|
|
port map (PADDI=>PHI2_c, PHI2S=>PHI2);
|
|
MAin_9_I: MAin_9_B
|
|
port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
|
|
MAin_8_I: MAin_8_B
|
|
port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
|
|
MAin_7_I: MAin_7_B
|
|
port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
|
|
MAin_6_I: MAin_6_B
|
|
port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
|
|
MAin_5_I: MAin_5_B
|
|
port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
|
|
MAin_4_I: MAin_4_B
|
|
port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
|
|
MAin_3_I: MAin_3_B
|
|
port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
|
|
MAin_2_I: MAin_2_B
|
|
port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
|
|
MAin_1_I: MAin_1_B
|
|
port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
|
|
MAin_0_I: MAin_0_B
|
|
port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
|
|
CROW_1_I: CROW_1_B
|
|
port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
|
|
CROW_0_I: CROW_0_B
|
|
port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
|
|
Din_7_I: Din_7_B
|
|
port map (PADDI=>Din_c_7, Din7=>Din(7));
|
|
Din_6_I: Din_6_B
|
|
port map (PADDI=>Din_c_6, Din6=>Din(6));
|
|
Din_5_I: Din_5_B
|
|
port map (PADDI=>Din_c_5, Din5=>Din(5));
|
|
Din_4_I: Din_4_B
|
|
port map (PADDI=>Din_c_4, Din4=>Din(4));
|
|
Din_3_I: Din_3_B
|
|
port map (PADDI=>Din_c_3, Din3=>Din(3));
|
|
Din_2_I: Din_2_B
|
|
port map (PADDI=>Din_c_2, Din2=>Din(2));
|
|
Din_1_I: Din_1_B
|
|
port map (PADDI=>Din_c_1, Din1=>Din(1));
|
|
Din_0_I: Din_0_B
|
|
port map (PADDI=>Din_c_0, Din0=>Din(0));
|
|
nCCASI: nCCASB
|
|
port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
|
|
nCRASI: nCRASB
|
|
port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
|
|
nFWEI: nFWEB
|
|
port map (PADDI=>nFWE_c, nFWES=>nFWE);
|
|
RCLKI: RCLKB
|
|
port map (PADDI=>RCLK_c, RCLKS=>RCLK);
|
|
UFMSDOI: UFMSDOB
|
|
port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
|
|
VHI_INST: VHI
|
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port map (Z=>VCCI);
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PUR_INST: PUR
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port map (PUR=>VCCI);
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|
GSR_INST: GSR
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|
port map (GSR=>VCCI);
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end Structure;
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library IEEE, vital2000, MACHXO2;
|
|
configuration Structure_CON of RAM2GS is
|
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for Structure
|
|
end for;
|
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end Structure_CON;
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