155 lines
11 KiB
Plaintext
155 lines
11 KiB
Plaintext
Analysis & Synthesis report for RAM2GS
|
|
Sat Aug 12 18:40:54 2023
|
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|
|
|
|
|
---------------------
|
|
; Table of Contents ;
|
|
---------------------
|
|
1. Legal Notice
|
|
2. Analysis & Synthesis Summary
|
|
3. Analysis & Synthesis Settings
|
|
4. Parallel Compilation
|
|
5. Analysis & Synthesis Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
|
Your use of Intel Corporation's design tools, logic functions
|
|
and other software and tools, and any partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Intel Program License
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
the Intel FPGA IP License Agreement, or other applicable license
|
|
agreement, including, without limitation, that your use is for
|
|
the sole purpose of programming logic devices manufactured by
|
|
Intel and sold by Intel or its authorized distributors. Please
|
|
refer to the applicable agreement for further details, at
|
|
https://fpgasoftware.intel.com/eula.
|
|
|
|
|
|
|
|
+---------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Summary ;
|
|
+-----------------------------+---------------------------------------------+
|
|
; Analysis & Synthesis Status ; Failed - Sat Aug 12 18:40:54 2023 ;
|
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
|
; Revision Name ; RAM2GS ;
|
|
; Top-level Entity Name ; RAM2GS ;
|
|
; Family ; MAX V ;
|
|
+-----------------------------+---------------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Settings ;
|
|
+------------------------------------------------------------------+--------------------+--------------------+
|
|
; Option ; Setting ; Default Value ;
|
|
+------------------------------------------------------------------+--------------------+--------------------+
|
|
; Device ; 5M240ZT100C5 ; ;
|
|
; Top-level entity name ; RAM2GS ; RAM2GS ;
|
|
; Family name ; MAX V ; Cyclone V ;
|
|
; Use smart compilation ; Off ; Off ;
|
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
|
; Enable compact report table ; Off ; Off ;
|
|
; Restructure Multiplexers ; Auto ; Auto ;
|
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
|
; Preserve fewer node names ; On ; On ;
|
|
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
|
; State Machine Processing ; Auto ; Auto ;
|
|
; Safe State Machine ; Off ; Off ;
|
|
; Extract Verilog State Machines ; On ; On ;
|
|
; Extract VHDL State Machines ; On ; On ;
|
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
|
; Infer RAMs from Raw Logic ; On ; On ;
|
|
; Parallel Synthesis ; On ; On ;
|
|
; NOT Gate Push-Back ; On ; On ;
|
|
; Power-Up Don't Care ; On ; On ;
|
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
|
; Remove Duplicate Registers ; On ; On ;
|
|
; Ignore CARRY Buffers ; Off ; Off ;
|
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore LCELL Buffers ; Off ; Off ;
|
|
; Ignore SOFT Buffers ; On ; On ;
|
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
|
; Optimization Technique ; Balanced ; Balanced ;
|
|
; Carry Chain Length ; 70 ; 70 ;
|
|
; Auto Carry Chains ; On ; On ;
|
|
; Auto Open-Drain Pins ; On ; On ;
|
|
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
|
; Auto Clock Enable Replacement ; On ; On ;
|
|
; Allow Synchronous Control Signals ; On ; On ;
|
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
|
; Auto Resource Sharing ; Off ; Off ;
|
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
|
; Report Parameter Settings ; On ; On ;
|
|
; Report Source Assignments ; On ; On ;
|
|
; Report Connectivity Checks ; On ; On ;
|
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
|
; HDL message level ; Level2 ; Level2 ;
|
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
|
; Clock MUX Protection ; On ; On ;
|
|
; Block Design Naming ; Auto ; Auto ;
|
|
; Synthesis Effort ; Auto ; Auto ;
|
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
|
+------------------------------------------------------------------+--------------------+--------------------+
|
|
|
|
|
|
+------------------------------------------+
|
|
; Parallel Compilation ;
|
|
+----------------------------+-------------+
|
|
; Processors ; Number ;
|
|
+----------------------------+-------------+
|
|
; Number detected on machine ; 8 ;
|
|
; Maximum allowed ; 4 ;
|
|
; ; ;
|
|
; Average used ; 1.00 ;
|
|
; Maximum used ; 1 ;
|
|
; ; ;
|
|
; Usage by Processor ; % Time Used ;
|
|
; Processor 1 ; 100.0% ;
|
|
+----------------------------+-------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Analysis & Synthesis
|
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|
Info: Processing started: Sat Aug 12 18:40:41 2023
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v
|
|
Info (12023): Found entity 1: RAM4GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
|
|
Error (12007): Top-level design entity "RAM2GS" is undefined
|
|
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
|
|
Error: Peak virtual memory: 4687 megabytes
|
|
Error: Processing ended: Sat Aug 12 18:40:54 2023
|
|
Error: Elapsed time: 00:00:13
|
|
Error: Total CPU time (on all processors): 00:00:29
|
|
|
|
|