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RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
Zane Kaminski c958649a59 SPI/LCMXO RC
2024-01-06 21:52:05 -05:00

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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Nov 18 02:06:13 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Design file: ram2gs_lcmxo2_1200hc_impl1.ncd
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
Report: 48.464MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
Report: 102.197MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
147 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 162.097ns (weighted slack = 324.194ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 9.837ns (26.0% logic, 74.0% route), 5 logic levels.
Constraint Details:
9.837ns physical path delay Din[7]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 162.097ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 2.215 IOL_L2C.IN to R4C10D.A0 Bank[7]
CTOF_DEL --- 0.495 R4C10D.A0 to R4C10D.F0 SLICE_90
ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
9.837 (26.0% logic, 74.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 162.937ns (weighted slack = 325.874ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[1] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.997ns (28.4% logic, 71.6% route), 5 logic levels.
Constraint Details:
8.997ns physical path delay Din[1]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 162.937ns
Physical Path Details:
Data path Din[1]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_T10B.IN to R4C10D.D0 Bank[1]
CTOF_DEL --- 0.495 R4C10D.D0 to R4C10D.F0 SLICE_90
ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.997 (28.4% logic, 71.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.032ns (weighted slack = 326.064ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.902ns (28.7% logic, 71.3% route), 5 logic levels.
Constraint Details:
8.902ns physical path delay Din[6]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.032ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 1.802 IOL_L2D.IN to R2C9D.D1 Bank[6]
CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_80
ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.902 (28.7% logic, 71.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.085ns (weighted slack = 326.170ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.990ns (33.9% logic, 66.1% route), 6 logic levels.
Constraint Details:
8.990ns physical path delay Din[7]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.085ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2C.CLK to IOL_L2C.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 2.215 IOL_L2C.IN to R4C10D.A0 Bank[7]
CTOF_DEL --- 0.495 R4C10D.A0 to R4C10D.F0 SLICE_90
ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80
ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367
CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11
ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33
ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17
ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c)
--------
8.990 (33.9% logic, 66.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_L2C.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.118ns (weighted slack = 326.236ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.816ns (29.0% logic, 71.0% route), 5 logic levels.
Constraint Details:
8.816ns physical path delay Din[2]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.118ns
Physical Path Details:
Data path Din[2]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T12A.CLK to IOL_T12A.IN Din[2]_MGIOL (from PHI2_c)
ROUTE 1 1.716 IOL_T12A.IN to R2C9D.A1 Bank[2]
CTOF_DEL --- 0.495 R2C9D.A1 to R2C9D.F1 SLICE_80
ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.816 (29.0% logic, 71.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[2]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_T12A.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.196ns (weighted slack = 326.392ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[5] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.738ns (29.3% logic, 70.7% route), 5 logic levels.
Constraint Details:
8.738ns physical path delay Din[5]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.196ns
Physical Path Details:
Data path Din[5]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T9B.CLK to IOL_T9B.IN Din[5]_MGIOL (from PHI2_c)
ROUTE 1 1.638 IOL_T9B.IN to R2C9D.B1 Bank[5]
CTOF_DEL --- 0.495 R2C9D.B1 to R2C9D.F1 SLICE_80
ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.738 (29.3% logic, 70.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_T9B.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.537ns (weighted slack = 327.074ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[3] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.397ns (30.5% logic, 69.5% route), 5 logic levels.
Constraint Details:
8.397ns physical path delay Din[3]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.537ns
Physical Path Details:
Data path Din[3]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T10A.CLK to IOL_T10A.IN Din[3]_MGIOL (from PHI2_c)
ROUTE 1 1.297 IOL_T10A.IN to R2C9D.C1 Bank[3]
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_80
ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.397 (30.5% logic, 69.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_T10A.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.622ns (weighted slack = 327.244ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdUFMData (to PHI2_c -)
Delay: 8.312ns (24.8% logic, 75.2% route), 4 logic levels.
Constraint Details:
8.312ns physical path delay Din[0]_MGIOL to SLICE_19 meets
172.414ns delay constraint less
0.173ns skew and
0.307ns CE_SET requirement (totaling 171.934ns) by 163.622ns
Physical Path Details:
Data path Din[0]_MGIOL to SLICE_19:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L3A.CLK to IOL_L3A.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 2.143 IOL_L3A.IN to R2C9D.A0 Bank[0]
CTOF_DEL --- 0.495 R2C9D.A0 to R2C9D.F0 SLICE_80
ROUTE 6 1.104 R2C9D.F0 to R5C9A.D1 N_367
CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_23
ROUTE 8 1.295 R5C9A.F1 to R7C10B.C0 XOR8MEG18
CTOF_DEL --- 0.495 R7C10B.C0 to R7C10B.F0 SLICE_77
ROUTE 1 1.708 R7C10B.F0 to R7C11B.CE CmdUFMData_1_sqmuxa (to PHI2_c)
--------
8.312 (24.8% logic, 75.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_L3A.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R7C11B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[1] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.150ns (37.4% logic, 62.6% route), 6 logic levels.
Constraint Details:
8.150ns physical path delay Din[1]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.925ns
Physical Path Details:
Data path Din[1]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T10B.CLK to IOL_T10B.IN Din[1]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_T10B.IN to R4C10D.D0 Bank[1]
CTOF_DEL --- 0.495 R4C10D.D0 to R4C10D.F0 SLICE_90
ROUTE 1 0.958 R4C10D.F0 to R2C9D.D0 un1_CmdEnable20_0_0_o2_10
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_80
ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367
CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11
ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33
ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17
ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c)
--------
8.150 (37.4% logic, 62.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_T10B.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 164.020ns (weighted slack = 328.040ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[6] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.055ns (37.9% logic, 62.1% route), 6 logic levels.
Constraint Details:
8.055ns physical path delay Din[6]_MGIOL to SLICE_17 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 164.020ns
Physical Path Details:
Data path Din[6]_MGIOL to SLICE_17:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2D.CLK to IOL_L2D.IN Din[6]_MGIOL (from PHI2_c)
ROUTE 1 1.802 IOL_L2D.IN to R2C9D.D1 Bank[6]
CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_80
ROUTE 1 0.436 R2C9D.F1 to R2C9D.C0 un1_CmdEnable20_0_0_o2_11
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_80
ROUTE 6 1.048 R2C9D.F0 to R4C9A.B1 N_367
CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 SLICE_11
ROUTE 3 0.753 R4C9A.F1 to R4C8A.C0 CmdEnable16
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_33
ROUTE 1 0.964 R4C8A.F0 to R4C9B.A0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 R4C9B.A0 to R4C9B.F0 SLICE_17
ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c)
--------
8.055 (37.9% logic, 62.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.369 8.PADDI to IOL_L2D.CLK PHI2_c
--------
4.369 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 4.196 8.PADDI to R4C9B.CLK PHI2_c
--------
4.196 (0.0% logic, 100.0% route), 0 logic levels.
Report: 48.464MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
891 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.215ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2 (from RCLK_c +)
Destination: FF Data in nRWE_0io (to RCLK_c +)
Delay: 9.805ns (29.9% logic, 70.1% route), 6 logic levels.
Constraint Details:
9.805ns physical path delay SLICE_32 to nRWE_MGIOL meets
16.000ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 16.020ns) by 6.215ns
Physical Path Details:
Data path SLICE_32 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c)
ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2
CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62
ROUTE 6 1.078 R8C11B.F1 to R7C12C.D1 IS_0_sqmuxa_0_o2
CTOF_DEL --- 0.495 R7C12C.D1 to R7C12C.F1 SLICE_79
ROUTE 2 0.635 R7C12C.F1 to R7C12A.D1 IS_0_sqmuxa_0_o3
CTOF_DEL --- 0.495 R7C12A.D1 to R7C12A.F1 SLICE_28
ROUTE 1 0.744 R7C12A.F1 to R8C12B.C1 nRWE_s_i_a2_1_0
CTOF_DEL --- 0.495 R8C12B.C1 to R8C12B.F1 SLICE_68
ROUTE 1 0.744 R8C12B.F1 to R9C12D.C0 nRWE_s_i_tz_0
CTOF_DEL --- 0.495 R9C12D.C0 to R9C12D.F0 SLICE_75
ROUTE 1 1.714 R9C12D.F0 to IOL_B20D.OPOS N_252_i (to RCLK_c)
--------
9.805 (29.9% logic, 70.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c
--------
2.437 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.236ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 9.425ns (77.1% logic, 22.9% route), 3 logic levels.
Constraint Details:
9.425ns physical path delay ufmefb/EFBInst_0 to SLICE_45 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 6.236ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_45:
Name Fanout Delay (ns) Site Resource
WCLKI2WBDA --- 6.278 EFB.WBCLKI to EFB.WBDATO0 ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 1 1.512 EFB.WBDATO0 to R4C5C.C1 wb_dato[0]
CTOF_DEL --- 0.495 R4C5C.C1 to R4C5C.F1 SLICE_111
ROUTE 1 0.645 R4C5C.F1 to R5C5B.D0 n8MEGENe_1_0
CTOF_DEL --- 0.495 R5C5B.D0 to R5C5B.F0 SLICE_45
ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n8MEGENe_0 (to RCLK_c)
--------
9.425 (77.1% logic, 22.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c
--------
2.437 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_45:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R5C5B.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.365ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: EFB Port ufmefb/EFBInst_0(ASIC) (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 9.296ns (69.4% logic, 30.6% route), 3 logic levels.
Constraint Details:
9.296ns physical path delay ufmefb/EFBInst_0 to SLICE_30 meets
16.000ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 15.661ns) by 6.365ns
Physical Path Details:
Data path ufmefb/EFBInst_0 to SLICE_30:
Name Fanout Delay (ns) Site Resource
WCLKI2WBDA --- 5.461 EFB.WBCLKI to EFB.WBDATO1 ufmefb/EFBInst_0 (from RCLK_c)
ROUTE 1 2.152 EFB.WBDATO1 to R7C5A.A1 wb_dato[1]
CTOF_DEL --- 0.495 R7C5A.A1 to R7C5A.F1 SLICE_30
ROUTE 1 0.693 R7C5A.F1 to R7C5A.B0 LEDEN_6
CTOF_DEL --- 0.495 R7C5A.B0 to R7C5A.F0 SLICE_30
ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 LEDENe_0 (to RCLK_c)
--------
9.296 (69.4% logic, 30.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.437 63.PADDI to EFB.WBCLKI RCLK_c
--------
2.437 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R7C5A.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.454ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q InitReady (from RCLK_c +)
Destination: FF Data in nRWE_0io (to RCLK_c +)
Delay: 9.566ns (30.6% logic, 69.4% route), 6 logic levels.
Constraint Details:
9.566ns physical path delay SLICE_29 to nRWE_MGIOL meets
16.000ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 16.020ns) by 6.454ns
Physical Path Details:
Data path SLICE_29 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_29 (from RCLK_c)
ROUTE 40 1.724 R4C8D.Q0 to R8C11B.D1 InitReady
CTOF_DEL --- 0.495 R8C11B.D1 to R8C11B.F1 SLICE_62
ROUTE 6 1.078 R8C11B.F1 to R7C12C.D1 IS_0_sqmuxa_0_o2
CTOF_DEL --- 0.495 R7C12C.D1 to R7C12C.F1 SLICE_79
ROUTE 2 0.635 R7C12C.F1 to R7C12A.D1 IS_0_sqmuxa_0_o3
CTOF_DEL --- 0.495 R7C12A.D1 to R7C12A.F1 SLICE_28
ROUTE 1 0.744 R7C12A.F1 to R8C12B.C1 nRWE_s_i_a2_1_0
CTOF_DEL --- 0.495 R8C12B.C1 to R8C12B.F1 SLICE_68
ROUTE 1 0.744 R8C12B.F1 to R9C12D.C0 nRWE_s_i_tz_0
CTOF_DEL --- 0.495 R9C12D.C0 to R9C12D.F0 SLICE_75
ROUTE 1 1.714 R9C12D.F0 to IOL_B20D.OPOS N_252_i (to RCLK_c)
--------
9.566 (30.6% logic, 69.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.437 63.PADDI to IOL_B20D.CLK RCLK_c
--------
2.437 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.646ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[1] (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 9.373ns (31.2% logic, 68.8% route), 6 logic levels.
Constraint Details:
9.373ns physical path delay SLICE_27 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.172ns skew and
0.153ns DO_SET requirement (totaling 16.019ns) by 6.646ns
Physical Path Details:
Data path SLICE_27 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_27 (from RCLK_c)
ROUTE 7 1.445 R7C11C.Q0 to R8C12A.A1 IS[1]
CTOF_DEL --- 0.495 R8C12A.A1 to R8C12A.F1 SLICE_83
ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2
CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62
ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48
CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69
ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0
CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69
ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2
CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101
ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c)
--------
9.373 (31.2% logic, 68.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c
--------
2.436 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.656ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2 (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 9.363ns (31.3% logic, 68.7% route), 6 logic levels.
Constraint Details:
9.363ns physical path delay SLICE_32 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.172ns skew and
0.153ns DO_SET requirement (totaling 16.019ns) by 6.656ns
Physical Path Details:
Data path SLICE_32 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c)
ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2
CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62
ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2
CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62
ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48
CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69
ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0
CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69
ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2
CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101
ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c)
--------
9.363 (31.3% logic, 68.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c
--------
2.436 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.868ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[1] (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 9.151ns (26.6% logic, 73.4% route), 5 logic levels.
Constraint Details:
9.151ns physical path delay SLICE_27 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.172ns skew and
0.153ns DO_SET requirement (totaling 16.019ns) by 6.868ns
Physical Path Details:
Data path SLICE_27 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q0 SLICE_27 (from RCLK_c)
ROUTE 7 1.445 R7C11C.Q0 to R8C12A.A1 IS[1]
CTOF_DEL --- 0.495 R8C12A.A1 to R8C12A.F1 SLICE_83
ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2
CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62
ROUTE 2 1.308 R8C11B.F0 to R9C12C.A0 N_48
CTOF_DEL --- 0.495 R9C12C.A0 to R9C12C.F0 SLICE_101
ROUTE 1 0.967 R9C12C.F0 to R9C12C.A1 N_251_i_sx
CTOF_DEL --- 0.495 R9C12C.A1 to R9C12C.F1 SLICE_101
ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c)
--------
9.151 (26.6% logic, 73.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c
--------
2.436 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.878ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2 (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 9.141ns (26.6% logic, 73.4% route), 5 logic levels.
Constraint Details:
9.141ns physical path delay SLICE_32 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.172ns skew and
0.153ns DO_SET requirement (totaling 16.019ns) by 6.878ns
Physical Path Details:
Data path SLICE_32 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C12C.CLK to R4C12C.Q1 SLICE_32 (from RCLK_c)
ROUTE 10 1.963 R4C12C.Q1 to R8C11B.A1 RASr2
CTOF_DEL --- 0.495 R8C11B.A1 to R8C11B.F1 SLICE_62
ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2
CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62
ROUTE 2 1.308 R8C11B.F0 to R9C12C.A0 N_48
CTOF_DEL --- 0.495 R9C12C.A0 to R9C12C.F0 SLICE_101
ROUTE 1 0.967 R9C12C.F0 to R9C12C.A1 N_251_i_sx
CTOF_DEL --- 0.495 R9C12C.A1 to R9C12C.F1 SLICE_101
ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c)
--------
9.141 (26.6% logic, 73.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R4C12C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c
--------
2.436 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.895ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q InitReady (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 9.124ns (32.1% logic, 67.9% route), 6 logic levels.
Constraint Details:
9.124ns physical path delay SLICE_29 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.172ns skew and
0.153ns DO_SET requirement (totaling 16.019ns) by 6.895ns
Physical Path Details:
Data path SLICE_29 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C8D.CLK to R4C8D.Q0 SLICE_29 (from RCLK_c)
ROUTE 40 1.724 R4C8D.Q0 to R8C11B.D1 InitReady
CTOF_DEL --- 0.495 R8C11B.D1 to R8C11B.F1 SLICE_62
ROUTE 6 0.445 R8C11B.F1 to R8C11B.C0 IS_0_sqmuxa_0_o2
CTOF_DEL --- 0.495 R8C11B.C0 to R8C11B.F0 SLICE_62
ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48
CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69
ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0
CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69
ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2
CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101
ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c)
--------
9.124 (32.1% logic, 67.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R4C8D.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c
--------
2.436 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.966ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[2] (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Delay: 9.053ns (32.3% logic, 67.7% route), 6 logic levels.
Constraint Details:
9.053ns physical path delay SLICE_27 to nRCAS_MGIOL meets
16.000ns delay constraint less
-0.172ns skew and
0.153ns DO_SET requirement (totaling 16.019ns) by 6.966ns
Physical Path Details:
Data path SLICE_27 to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C11C.CLK to R7C11C.Q1 SLICE_27 (from RCLK_c)
ROUTE 6 1.125 R7C11C.Q1 to R8C12A.C1 IS[2]
CTOF_DEL --- 0.495 R8C12A.C1 to R8C12A.F1 SLICE_83
ROUTE 3 0.973 R8C12A.F1 to R8C11B.A0 un1_nRCAS_6_sqmuxa_i_o2
CTOF_DEL --- 0.495 R8C11B.A0 to R8C11B.F0 SLICE_62
ROUTE 2 0.632 R8C11B.F0 to R9C11A.D0 N_48
CTOF_DEL --- 0.495 R9C11A.D0 to R9C11A.F0 SLICE_69
ROUTE 1 0.626 R9C11A.F0 to R9C11A.D1 nRCS_9_u_i_o3_0_0
CTOF_DEL --- 0.495 R9C11A.D1 to R9C11A.F1 SLICE_69
ROUTE 1 0.744 R9C11A.F1 to R9C12C.C1 nRCS_9_u_i_o3_0_2
CTOF_DEL --- 0.495 R9C12C.C1 to R9C12C.F1 SLICE_101
ROUTE 1 2.026 R9C12C.F1 to IOL_R10C.OPOS N_251_i (to RCLK_c)
--------
9.053 (32.3% logic, 67.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.264 63.PADDI to R7C11C.CLK RCLK_c
--------
2.264 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to nRCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 48 2.436 63.PADDI to IOL_R10C.CLK RCLK_c
--------
2.436 (0.0% logic, 100.0% route), 0 logic levels.
Report: 102.197MHz is the maximum frequency for this preference.
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 48.464 MHz| 5
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.197 MHz| 6
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Sat Nov 18 02:06:13 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Design file: ram2gs_lcmxo2_1200hc_impl1.ncd
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
147 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9D.CLK to R4C9D.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 0.132 R4C9D.Q0 to R4C9D.A0 ADSubmitted
CTOF_DEL --- 0.101 R4C9D.A0 to R4C9D.F0 SLICE_10
ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 ADSubmitted_r_0_0 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMShift (from PHI2_c -)
Destination: FF Data in CmdUFMShift (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_20 to SLICE_20 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C9A.CLK to R7C9A.Q0 SLICE_20 (from PHI2_c)
ROUTE 2 0.132 R7C9A.Q0 to R7C9A.A0 CmdUFMShift
CTOF_DEL --- 0.101 R7C9A.A0 to R7C9A.F0 SLICE_20
ROUTE 1 0.000 R7C9A.F0 to R7C9A.DI0 CmdUFMShift_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.385ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 0.372ns (62.9% logic, 37.1% route), 2 logic levels.
Constraint Details:
0.372ns physical path delay SLICE_11 to SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.385ns
Physical Path Details:
Data path SLICE_11 to SLICE_11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_11 (from PHI2_c)
ROUTE 2 0.138 R4C9A.Q0 to R4C9A.C0 C1Submitted
CTOF_DEL --- 0.101 R4C9A.C0 to R4C9A.F0 SLICE_11
ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 C1Submitted_RNO (to PHI2_c)
--------
0.372 (62.9% logic, 37.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.458ns (51.1% logic, 48.9% route), 2 logic levels.
Constraint Details:
0.458ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.471ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c)
ROUTE 2 0.224 R4C9B.Q0 to R4C9B.B0 CmdEnable
CTOF_DEL --- 0.101 R4C9B.B0 to R4C9B.F0 SLICE_17
ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c)
--------
0.458 (51.1% logic, 48.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.616ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdLEDEN (from PHI2_c -)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
Constraint Details:
0.603ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.616ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C8C.CLK to R7C8C.Q0 SLICE_18 (from PHI2_c)
ROUTE 2 0.212 R7C8C.Q0 to R7C8C.A1 CmdLEDEN
CTOF_DEL --- 0.101 R7C8C.A1 to R7C8C.F1 SLICE_18
ROUTE 1 0.056 R7C8C.F1 to R7C8C.C0 CmdLEDEN_4_u_i_m2_i_0
CTOF_DEL --- 0.101 R7C8C.C0 to R7C8C.F0 SLICE_18
ROUTE 1 0.000 R7C8C.F0 to R7C8C.DI0 N_17_i (to PHI2_c)
--------
0.603 (55.6% logic, 44.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C8C.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C8C.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.622ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.609ns (55.0% logic, 45.0% route), 3 logic levels.
Constraint Details:
0.609ns physical path delay SLICE_11 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.622ns
Physical Path Details:
Data path SLICE_11 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9A.CLK to R4C9A.Q0 SLICE_11 (from PHI2_c)
ROUTE 2 0.137 R4C9A.Q0 to R5C9D.D0 C1Submitted
CTOF_DEL --- 0.101 R5C9D.D0 to R5C9D.F0 SLICE_76
ROUTE 1 0.137 R5C9D.F0 to R4C9B.C0 un1_CmdEnable20_i
CTOF_DEL --- 0.101 R4C9B.C0 to R4C9B.F0 SLICE_17
ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 CmdEnable_s (to PHI2_c)
--------
0.609 (55.0% logic, 45.0% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.705ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Cmdn8MEGEN (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 0.692ns (48.4% logic, 51.6% route), 3 logic levels.
Constraint Details:
0.692ns physical path delay SLICE_24 to SLICE_24 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.705ns
Physical Path Details:
Data path SLICE_24 to SLICE_24:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 SLICE_24 (from PHI2_c)
ROUTE 2 0.135 R7C8B.Q0 to R7C8B.D1 Cmdn8MEGEN
CTOF_DEL --- 0.101 R7C8B.D1 to R7C8B.F1 SLICE_24
ROUTE 1 0.222 R7C8B.F1 to R7C8B.B0 Cmdn8MEGEN_4_u_i_m2_i_0
CTOF_DEL --- 0.101 R7C8B.B0 to R7C8B.F0 SLICE_24
ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 N_15_i (to PHI2_c)
--------
0.692 (48.4% logic, 51.6% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C8B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C8B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.728ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdUFMShift (to PHI2_c -)
Delay: 0.700ns (33.4% logic, 66.6% route), 2 logic levels.
Constraint Details:
0.700ns physical path delay SLICE_17 to SLICE_20 meets
-0.028ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.028ns) by 0.728ns
Physical Path Details:
Data path SLICE_17 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c)
ROUTE 2 0.277 R4C9B.Q0 to R5C9A.C1 CmdEnable
CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_23
ROUTE 8 0.189 R5C9A.F1 to R7C9A.CE XOR8MEG18 (to PHI2_c)
--------
0.700 (33.4% logic, 66.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.770ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdValid_fast (to PHI2_c -)
Delay: 0.757ns (44.3% logic, 55.7% route), 3 logic levels.
Constraint Details:
0.757ns physical path delay SLICE_17 to SLICE_23 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.770ns
Physical Path Details:
Data path SLICE_17 to SLICE_23:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_17 (from PHI2_c)
ROUTE 2 0.277 R4C9B.Q0 to R5C9A.C1 CmdEnable
CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_23
ROUTE 8 0.145 R5C9A.F1 to R5C9A.B0 XOR8MEG18
CTOF_DEL --- 0.101 R5C9A.B0 to R5C9A.F0 SLICE_23
ROUTE 1 0.000 R5C9A.F0 to R5C9A.DI0 N_34_fast (to PHI2_c)
--------
0.757 (44.3% logic, 55.7% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R4C9B.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R5C9A.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.782ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdUFMWrite (from PHI2_c -)
Destination: FF Data in CmdUFMWrite (to PHI2_c -)
Delay: 0.769ns (43.6% logic, 56.4% route), 3 logic levels.
Constraint Details:
0.769ns physical path delay SLICE_21 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.782ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C8D.CLK to R7C8D.Q0 SLICE_21 (from PHI2_c)
ROUTE 2 0.224 R7C8D.Q0 to R7C8D.B1 CmdUFMWrite
CTOF_DEL --- 0.101 R7C8D.B1 to R7C8D.F1 SLICE_21
ROUTE 1 0.210 R7C8D.F1 to R7C8D.A0 N_415
CTOF_DEL --- 0.101 R7C8D.A0 to R7C8D.F0 SLICE_21
ROUTE 1 0.000 R7C8D.F0 to R7C8D.DI0 CmdUFMWrite_3 (to PHI2_c)
--------
0.769 (43.6% logic, 56.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C8D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 21 1.423 8.PADDI to R7C8D.CLK PHI2_c
--------
1.423 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
891 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_12 to SLICE_12 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_12 (from RCLK_c)
ROUTE 1 0.152 R5C10B.Q0 to R5C10B.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R5C10B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R5C10B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr (from RCLK_c +)
Destination: FF Data in RASr2 (to RCLK_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_32 to SLICE_32 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_32 to SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C12C.CLK to R4C12C.Q0 SLICE_32 (from RCLK_c)
ROUTE 2 0.154 R4C12C.Q0 to R4C12C.M1 RASr (to RCLK_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R4C12C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R4C12C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.322ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r2 (from RCLK_c +)
Destination: FF Data in PHI2r3 (to RCLK_c +)
Delay: 0.303ns (43.9% logic, 56.1% route), 1 logic levels.
Constraint Details:
0.303ns physical path delay SLICE_31 to SLICE_31 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.322ns
Physical Path Details:
Data path SLICE_31 to SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_31 (from RCLK_c)
ROUTE 5 0.170 R5C8B.Q0 to R5C8B.M1 PHI2r2 (to RCLK_c)
--------
0.303 (43.9% logic, 56.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R5C8B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R5C8B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.326ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_dati[7] (from RCLK_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to RCLK_c +)
Delay: 0.307ns (43.3% logic, 56.7% route), 1 logic levels.
Constraint Details:
0.307ns physical path delay SLICE_55 to ufmefb/EFBInst_0 meets
-0.073ns WBDATI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.019ns) by 0.326ns
Physical Path Details:
Data path SLICE_55 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C6C.CLK to R3C6C.Q1 SLICE_55 (from RCLK_c)
ROUTE 2 0.174 R3C6C.Q1 to EFB.WBDATI7 wb_dati[7] (to RCLK_c)
--------
0.307 (43.3% logic, 56.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R3C6C.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.842 63.PADDI to EFB.WBCLKI RCLK_c
--------
0.842 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from RCLK_c +)
Destination: FF Data in FS[0] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from RCLK_c)
ROUTE 3 0.132 R2C7A.Q1 to R2C7A.A1 FS[0]
CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0
ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C7A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C7A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in FS[17] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C9B.CLK to R2C9B.Q0 SLICE_1 (from RCLK_c)
ROUTE 7 0.132 R2C9B.Q0 to R2C9B.A0 FS[17]
CTOF_DEL --- 0.101 R2C9B.A0 to R2C9B.F0 SLICE_1
ROUTE 1 0.000 R2C9B.F0 to R2C9B.DI0 FS_s[17] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C9B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C9B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in FS[15] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C9A.CLK to R2C9A.Q0 SLICE_2 (from RCLK_c)
ROUTE 6 0.132 R2C9A.Q0 to R2C9A.A0 FS[15]
CTOF_DEL --- 0.101 R2C9A.A0 to R2C9A.F0 SLICE_2
ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 FS_s[15] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C9A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C9A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in FS[14] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C8D.CLK to R2C8D.Q1 SLICE_3 (from RCLK_c)
ROUTE 19 0.132 R2C8D.Q1 to R2C8D.A1 FS[14]
CTOF_DEL --- 0.101 R2C8D.A1 to R2C8D.F1 SLICE_3
ROUTE 1 0.000 R2C8D.F1 to R2C8D.DI1 FS_s[14] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C8D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R2C8D.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LEDEN (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_30 to SLICE_30 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_30 to SLICE_30:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C5A.CLK to R7C5A.Q0 SLICE_30 (from RCLK_c)
ROUTE 4 0.132 R7C5A.Q0 to R7C5A.A0 LEDEN
CTOF_DEL --- 0.101 R7C5A.A0 to R7C5A.F0 SLICE_30
ROUTE 1 0.000 R7C5A.F0 to R7C5A.DI0 LEDENe_0 (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R7C5A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R7C5A.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q n8MEGEN (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_45 to SLICE_45 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_45 to SLICE_45:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C5B.CLK to R5C5B.Q0 SLICE_45 (from RCLK_c)
ROUTE 3 0.132 R5C5B.Q0 to R5C5B.A0 n8MEGEN
CTOF_DEL --- 0.101 R5C5B.A0 to R5C5B.F0 SLICE_45
ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n8MEGENe_0 (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_45:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R5C5B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_45:
Name Fanout Delay (ns) Site Resource
ROUTE 48 0.788 63.PADDI to R5C5B.CLK RCLK_c
--------
0.788 (0.0% logic, 100.0% route), 0 logic levels.
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1038 paths, 4 nets, and 750 connections (74.18% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
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