403 lines
15 KiB
Plaintext
403 lines
15 KiB
Plaintext
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Lattice Mapping Report File for Design Module 'RAM2GS'
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Design Information
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------------------
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Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
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RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
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RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
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rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
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O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
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LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui
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Target Vendor: LATTICE
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Target Device: LCMXO2-640HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2
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Mapped on: 10/09/21 01:19:14
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Design Summary
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--------------
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Number of registers: 119 out of 877 (14%)
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PFU registers: 119 out of 640 (19%)
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PIO registers: 0 out of 237 (0%)
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Number of SLICEs: 131 out of 320 (41%)
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SLICEs as Logic/ROM: 131 out of 320 (41%)
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SLICEs as RAM: 0 out of 240 (0%)
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SLICEs as Carry: 10 out of 320 (3%)
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Number of LUT4s: 255 out of 640 (40%)
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Number used as logic LUTs: 235
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Number used as distributed RAM: 0
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Number used as ripple logic: 20
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Number used as shift registers: 0
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Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
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Number of block RAMs: 0 out of 2 (0%)
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Number of GSRs: 0 out of 1 (0%)
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EFB used : Yes
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JTAG used : No
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Readback used : No
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Oscillator used : No
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Startup used : No
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POR : On
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Bandgap : On
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Number of Power Controller: 0 out of 1 (0%)
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of DCCA: 0 out of 8 (0%)
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Number of DCMA: 0 out of 2 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 5
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Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
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Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
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Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
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Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
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Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
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Number of Clock Enables: 14
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Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
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Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
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Page 1
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Design: RAM2GS Date: 10/09/21 01:19:14
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Design Summary (cont)
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---------------------
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Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
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Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
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Net InitReady: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
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Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
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Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
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Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
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Net Ready_N_280: 1 loads, 1 LSLICEs
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Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
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Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
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Number of LSRs: 8
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Net RASr2: 1 loads, 1 LSLICEs
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Net nRowColSel_N_34: 1 loads, 1 LSLICEs
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Net wb_rst: 1 loads, 0 LSLICEs
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Net nRWE_N_210: 1 loads, 1 LSLICEs
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Net C1Submitted_N_232: 2 loads, 2 LSLICEs
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Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
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Net nRowColSel_N_35: 1 loads, 1 LSLICEs
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Net Ready: 7 loads, 7 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net InitReady: 36 loads
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Net FS_10: 32 loads
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Net FS_11: 32 loads
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Net FS_9: 26 loads
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Net FS_7: 25 loads
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Net FS_8: 23 loads
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Net FS_5: 21 loads
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Net FS_6: 21 loads
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Net FS_12: 20 loads
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Net Ready: 18 loads
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Number of warnings: 0
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Number of errors: 0
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Design Errors/Warnings
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----------------------
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No errors or warnings present.
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IO (PIO) Attributes
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-------------------
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| RCLK | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| nFWE | INPUT | LVTTL33 | |
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Page 2
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Design: RAM2GS Date: 10/09/21 01:19:14
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| nCRAS | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| nCCAS | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[0] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[1] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[2] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[3] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[4] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[5] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[6] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Din[7] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| CROW[0] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| CROW[1] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[0] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[1] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[2] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[3] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[4] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[5] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[6] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[7] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[8] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[9] | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| PHI2 | INPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RDQML | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RDQMH | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| nRCAS | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| nRRAS | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| nRWE | OUTPUT | LVTTL33 | |
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Page 3
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Design: RAM2GS Date: 10/09/21 01:19:14
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| RCKE | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| nRCS | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[0] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[1] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[2] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[3] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[4] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[5] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[6] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[7] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[8] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[9] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[10] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RA[11] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RBA[0] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RBA[1] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| LED | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[0] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[1] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[2] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[3] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[4] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[5] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[6] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[7] | OUTPUT | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[0] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[1] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[2] | BIDIR | LVTTL33 | |
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Page 4
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Design: RAM2GS Date: 10/09/21 01:19:14
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| RD[3] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[4] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[5] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[6] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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| RD[7] | BIDIR | LVTTL33 | |
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+---------------------+-----------+-----------+------------+
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Removed logic
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-------------
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Block i2 undriven or does not drive anything - clipped.
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Block GSR_INST undriven or does not drive anything - clipped.
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Signal PHI2_N_151 was merged into signal PHI2_c
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Signal nRWE_N_209 was merged into signal nRWE_N_210
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Signal RCLK_c_enable_22 was merged into signal InitReady
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Signal n2557 was merged into signal nRowColSel_N_34
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Signal n4935 was merged into signal Ready
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Signal n4933 was merged into signal nRowColSel_N_35
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Signal GND_net undriven or does not drive anything - clipped.
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Signal VCC_net undriven or does not drive anything - clipped.
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Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
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Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
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Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
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Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
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Block i4008 was optimized away.
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Block nRWE_I_53_1_lut was optimized away.
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Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
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Block i1683_1_lut was optimized away.
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Block i1044_1_lut_rep_86 was optimized away.
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Block i1684_1_lut_rep_84 was optimized away.
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Block i1 was optimized away.
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Embedded Functional Block Connection Summary
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--------------------------------------------
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Desired WISHBONE clock frequency: 50.0 MHz
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Clock source: wb_clk
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Reset source: wb_rst
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Functions mode:
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I2C #1 (Primary) Function: DISABLED
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I2C #2 (Secondary) Function: DISABLED
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SPI Function: DISABLED
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Timer/Counter Function: DISABLED
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Timer/Counter Mode: NO_WB
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UFM Connection: DISABLED
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PLL0 Connection: DISABLED
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PLL1 Connection: DISABLED
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I2C Function Summary:
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--------------------
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Page 5
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Design: RAM2GS Date: 10/09/21 01:19:14
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Embedded Functional Block Connection Summary (cont)
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---------------------------------------------------
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None
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SPI Function Summary:
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--------------------
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None
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Timer/Counter Function Summary:
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------------------------------
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None
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UFM Function Summary:
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--------------------
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UFM Utilization: General Purpose Flash Memory
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Available General
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Purpose Flash Memory: 191 Pages (191*128 Bits)
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EBR Blocks with Unique
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Initialization Data: 0
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WID EBR Instance
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--- ------------
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ASIC Components
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---------------
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Instance Name: ufmefb
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Type: EFB
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Run Time and Memory Usage
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 37 MB
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Page 6
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
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reserved.
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