337 lines
14 KiB
Plaintext
337 lines
14 KiB
Plaintext
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Lattice Mapping Report File for Design Module 'RAM2GS'
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Design Information
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------------------
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Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
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-ioreg b RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd
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-pr RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:
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/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640
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HC_impl1_synplify.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-
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640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
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D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
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Target Vendor: LATTICE
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Target Device: LCMXO2-640HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
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Mapped on: 08/15/23 23:30:05
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Design Summary
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--------------
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Number of registers: 93 out of 877 (11%)
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PFU registers: 64 out of 640 (10%)
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PIO registers: 29 out of 237 (12%)
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Number of SLICEs: 81 out of 320 (25%)
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SLICEs as Logic/ROM: 81 out of 320 (25%)
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SLICEs as RAM: 0 out of 240 (0%)
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SLICEs as Carry: 10 out of 320 (3%)
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Number of LUT4s: 159 out of 640 (25%)
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Number used as logic LUTs: 139
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Number used as distributed RAM: 0
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Number used as ripple logic: 20
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Number used as shift registers: 0
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Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
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Number of block RAMs: 0 out of 2 (0%)
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Number of GSRs: 0 out of 1 (0%)
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EFB used : No
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JTAG used : No
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Readback used : No
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Oscillator used : No
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Startup used : No
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POR : On
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Bandgap : On
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Number of Power Controller: 0 out of 1 (0%)
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of DCCA: 0 out of 8 (0%)
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Number of DCMA: 0 out of 2 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 4
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Net PHI2_c: 18 loads, 8 rising, 10 falling (Driver: PIO PHI2 )
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Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
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Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
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Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
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Number of Clock Enables: 6
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Net XOR8MEG18: 3 loads, 3 LSLICEs
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Net i2_i: 1 loads, 0 LSLICEs
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Page 1
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Design: RAM2GS Date: 08/15/23 23:30:05
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Design Summary (cont)
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---------------------
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Net N_26: 1 loads, 1 LSLICEs
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Net N_28: 1 loads, 1 LSLICEs
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Net N_188_i: 2 loads, 2 LSLICEs
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Net CmdUFMCLK_1_sqmuxa: 3 loads, 0 LSLICEs
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Number of LSRs: 3
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Net RA10s_i: 1 loads, 0 LSLICEs
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Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
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Net RASr2: 2 loads, 2 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net InitReady: 17 loads
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Net Ready: 15 loads
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Net Ready_fast: 14 loads
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Net Din_c[5]: 12 loads
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Net nRowColSel: 12 loads
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Net S[1]: 12 loads
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Net RASr2: 10 loads
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Net CO0: 9 loads
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Net Din_c[3]: 9 loads
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Net Din_c[4]: 9 loads
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Number of warnings: 6
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Number of errors: 0
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Design Errors/Warnings
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----------------------
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WARNING - map: Output register UFMSDI$r0 is replicated for UFMSDI_pad.
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WARNING - map: Output register nUFMCS$r1 is replicated for nUFMCS_pad.
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WARNING - map: Output register RCKE$r2 is replicated for RCKE_pad.
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WARNING - map: Register Bank_0io[0] cannot be packed into IOC as intended by its
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primitive type or preference due to command option or architecture
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limitation. The register was packed into SLICE instead.
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WARNING - map: Register Bank_0io[1] cannot be packed into IOC as intended by its
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primitive type or preference due to command option or architecture
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limitation. The register was packed into SLICE instead.
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WARNING - map: Register Bank_0io[2] cannot be packed into IOC as intended by its
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primitive type or preference due to command option or architecture
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limitation. The register was packed into SLICE instead.
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IO (PIO) Attributes
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-------------------
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| RD[0] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| Dout[0] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| PHI2 | INPUT | LVCMOS33 | IN |
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Page 2
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Design: RAM2GS Date: 08/15/23 23:30:05
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| UFMSDO | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| UFMSDI | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| UFMCLK | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nUFMCS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RDQML | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RDQMH | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nRCAS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRRAS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| nRWE | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RCKE | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RCLK | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nRCS | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[7] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[6] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[5] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[4] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[3] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[2] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RD[1] | BIDIR | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[11] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[10] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RA[9] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[8] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[7] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[6] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[5] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[4] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[3] | OUTPUT | LVCMOS33 | |
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Page 3
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Design: RAM2GS Date: 08/15/23 23:30:05
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| RA[2] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[1] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RA[0] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| RBA[1] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| RBA[0] | OUTPUT | LVCMOS33 | OUT |
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+---------------------+-----------+-----------+------------+
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| LED | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nFWE | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nCRAS | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| nCCAS | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[7] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[6] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[5] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[4] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[3] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[2] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Dout[1] | OUTPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| Din[7] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[6] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[5] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[4] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[3] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[2] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[1] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| Din[0] | INPUT | LVCMOS33 | IN |
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+---------------------+-----------+-----------+------------+
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| CROW[1] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| CROW[0] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[9] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[8] | INPUT | LVCMOS33 | |
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Page 4
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Design: RAM2GS Date: 08/15/23 23:30:05
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IO (PIO) Attributes (cont)
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--------------------------
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+---------------------+-----------+-----------+------------+
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| MAin[7] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[6] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[5] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[4] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[3] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[2] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[1] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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| MAin[0] | INPUT | LVCMOS33 | |
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+---------------------+-----------+-----------+------------+
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Removed logic
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-------------
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Block GSR_INST undriven or does not drive anything - clipped.
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Signal nCRAS_c_i was merged into signal nCRAS_c
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Signal RASr2_i was merged into signal RASr2
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Signal XOR8MEG.CN was merged into signal PHI2_c
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Signal GND undriven or does not drive anything - clipped.
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Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
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Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
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Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
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Signal N_1 undriven or does not drive anything - clipped.
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Block nCRAS_pad_RNIBPVB was optimized away.
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Block RASr2_RNIAFR1 was optimized away.
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Block XOR8MEG.CN was optimized away.
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Block GND was optimized away.
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Run Time and Memory Usage
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 36 MB
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Page 5
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
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reserved.
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