418 lines
17 KiB
Plaintext
418 lines
17 KiB
Plaintext
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Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-640HC
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Package: TQFP100
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Performance: 4
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Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
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Tue Aug 15 22:56:32 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
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Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
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Preference file: ram2gs_lcmxo2_640hc_impl1.prf
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Device,speed: LCMXO2-640HC,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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170 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 161.824ns (weighted slack = 323.648ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q Bank_0io[3] (from PHI2_c +)
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Destination: FF Data in CmdEnable (to PHI2_c -)
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Delay: 10.424ns (36.2% logic, 63.8% route), 7 logic levels.
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Constraint Details:
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10.424ns physical path delay Din[3]_MGIOL to SLICE_18 meets
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172.414ns delay constraint less
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0.166ns DIN_SET requirement (totaling 172.248ns) by 161.824ns
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Physical Path Details:
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Data path Din[3]_MGIOL to SLICE_18:
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Name Fanout Delay (ns) Site Resource
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C2INP_DEL --- 0.577 *[3]_MGIOL.CLK to *n[3]_MGIOL.IN Din[3]_MGIOL (from PHI2_c)
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ROUTE 1 e 1.234 *n[3]_MGIOL.IN to SLICE_43.C1 Bank[3]
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CTOF_DEL --- 0.495 SLICE_43.C1 to SLICE_43.F1 SLICE_43
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ROUTE 1 e 1.234 SLICE_43.F1 to SLICE_69.D0 un1_Bank_1_4
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CTOF_DEL --- 0.495 SLICE_69.D0 to SLICE_69.F0 SLICE_69
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ROUTE 5 e 1.234 SLICE_69.F0 to SLICE_60.D0 un1_Bank_1
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CTOF_DEL --- 0.495 SLICE_60.D0 to SLICE_60.F0 SLICE_60
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ROUTE 2 e 1.234 SLICE_60.F0 to SLICE_46.A1 ADWR
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CTOF_DEL --- 0.495 SLICE_46.A1 to SLICE_46.F1 SLICE_46
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ROUTE 3 e 0.480 SLICE_46.F1 to SLICE_46.D0 un1_ADWR
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CTOF_DEL --- 0.495 SLICE_46.D0 to SLICE_46.F0 SLICE_46
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ROUTE 1 e 1.234 SLICE_46.F0 to SLICE_18.C0 un1_CMDWR
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CTOOFX_DEL --- 0.721 SLICE_18.C0 to SLICE_18.OFX0 SLICE_18
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ROUTE 1 e 0.001 SLICE_18.OFX0 to SLICE_18.DI0 CmdEnable_s (to PHI2_c)
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--------
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10.424 (36.2% logic, 63.8% route), 7 logic levels.
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Report: 47.214MHz is the maximum frequency for this preference.
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================================================================================
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Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 338.168ns
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The internal maximum frequency of the following component is 150.150 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCCAS
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Delay: 6.660ns -- based on Minimum Pulse Width
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Report: 150.150MHz is the maximum frequency for this preference.
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================================================================================
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Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 338.168ns
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The internal maximum frequency of the following component is 150.150 MHz
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Logical Details: Cell type Pin name Component name
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Destination: PIO PAD nCRAS
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Delay: 6.660ns -- based on Minimum Pulse Width
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Report: 150.150MHz is the maximum frequency for this preference.
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================================================================================
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Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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590 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 4.412ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q FS[17] (from RCLK_c +)
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Destination: FF Data in LEDEN (to RCLK_c +)
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Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
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Constraint Details:
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11.306ns physical path delay SLICE_1 to SLICE_27 meets
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16.000ns delay constraint less
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0.282ns CE_SET requirement (totaling 15.718ns) by 4.412ns
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Physical Path Details:
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Data path SLICE_1 to SLICE_27:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c)
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ROUTE 3 e 1.234 SLICE_1.Q0 to SLICE_72.D1 FS[17]
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CTOF_DEL --- 0.495 SLICE_72.D1 to SLICE_72.F1 SLICE_72
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ROUTE 1 e 1.234 SLICE_72.F1 to SLICE_64.C1 UFMSDI_ens2_i_o2_0_3
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CTOF_DEL --- 0.495 SLICE_64.C1 to SLICE_64.F1 SLICE_64
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ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_59.C1 N_129
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CTOF_DEL --- 0.495 SLICE_59.C1 to SLICE_59.F1 SLICE_59
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ROUTE 2 e 0.480 SLICE_59.F1 to SLICE_59.D0 N_145
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CTOF_DEL --- 0.495 SLICE_59.D0 to SLICE_59.F0 SLICE_59
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ROUTE 2 e 1.234 SLICE_59.F0 to SLICE_56.B0 N_139_8
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CTOF_DEL --- 0.495 SLICE_56.B0 to SLICE_56.F0 SLICE_56
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ROUTE 1 e 1.234 SLICE_56.F0 to SLICE_54.C0 N_140
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CTOF_DEL --- 0.495 SLICE_54.C0 to SLICE_54.F0 SLICE_54
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ROUTE 1 e 1.234 SLICE_54.F0 to SLICE_27.CE N_28 (to RCLK_c)
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--------
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11.306 (30.3% logic, 69.7% route), 7 logic levels.
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Report: 86.296MHz is the maximum frequency for this preference.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.214 MHz| 7
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 86.296 MHz| 7
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Timing summary (Setup):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
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Tue Aug 15 22:56:32 2023
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
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Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
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Preference file: ram2gs_lcmxo2_640hc_impl1.prf
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Device,speed: LCMXO2-640HC,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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170 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q ADSubmitted (from PHI2_c -)
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Destination: FF Data in ADSubmitted (to PHI2_c -)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay SLICE_10 to SLICE_10 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path SLICE_10 to SLICE_10:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
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ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
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CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
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ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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================================================================================
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Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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590 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.351ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q CASr (from RCLK_c +)
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Destination: FF Data in CASr2 (to RCLK_c +)
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Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
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Constraint Details:
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0.332ns physical path delay SLICE_14 to SLICE_14 meets
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-0.019ns M_HLD and
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0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
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Physical Path Details:
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Data path SLICE_14 to SLICE_14:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from RCLK_c)
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ROUTE 1 e 0.199 SLICE_14.Q0 to SLICE_14.M1 CASr (to RCLK_c)
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--------
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0.332 (40.1% logic, 59.9% route), 1 logic levels.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
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FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
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FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
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Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19
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Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Timing summary (Hold):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
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Timing summary (Setup and Hold):
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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