mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-25 00:31:24 +00:00
4094 lines
127 KiB
Plaintext
4094 lines
127 KiB
Plaintext
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// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
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// ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd
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// Netlist created on Tue Aug 15 22:56:31 2023
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// Netlist written on Tue Aug 15 22:56:32 2023
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// Design is for device LCMXO2-640HC
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// Design is for package TQFP100
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// Design is for performance grade 4
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`timescale 1 ns / 1 ps
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module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
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RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS,
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UFMCLK, UFMSDI, UFMSDO );
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input PHI2;
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input [9:0] MAin;
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input [1:0] CROW;
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input [7:0] Din;
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input nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
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output [7:0] Dout;
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output LED;
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output [1:0] RBA;
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output [11:0] RA;
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output [7:0] RD;
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output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
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wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] ,
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\FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] ,
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\FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] ,
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\FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] ,
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\FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] ,
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\FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] ,
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\FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] ,
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\FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] ,
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CmdEnable17_5, CmdEnable17_4, ADWR, CmdEnable16, CmdEnable17,
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un1_ADWR, ADSubmitted, ADSubmitted_r, PHI2_c, un1_Bank_1, \MAin_c[2] ,
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CmdEnable16_5, C1WR_3, C1Submitted, C1Submitted_s, nFWE_c, nCCAS_c,
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nCCAS_c_i, CASr, RD_1_i, CASr2, \S[1] , RASr2, \IS[3] , CO0, N_166_i,
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Ready_0_sqmuxa_0_a3_2, CmdEnable, un1_CMDWR, CmdEnable_s, N_36,
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\Din_c[5] , \Din_c[1] , N_94, N_60, N_59, LEDEN, N_14_i, XOR8MEG18,
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CmdLEDEN, \Din_c[3] , CmdSubmitted, CmdSubmitted_1_sqmuxa, N_412_0,
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CmdUFMCLK_1_sqmuxa, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, Cmdn8MEGEN,
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\MAin_c[1] , ADWR_6, ADWR_3, nFWE_c_i, nCRAS_c, FWEr, CMDWR_2, Ready,
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N_151, \IS[0] , N_60_i_i, RA10s_i, \IS[2] , \IS[1] , N_180_i,
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IS_n1_0_x2, N_48_i, N_58_i_i, N_137_5, N_137_3, InitReady, InitReady3,
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N_413_0, N_74_i, N_28, CBR, nCRAS_c_i_0, RASr, LED_c, \S_0_i_o2[1] ,
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RCKEEN_8_u_1_0, RCKEEN_8_u_0_0, RCKEEN_8, RCKEEN, Ready_fast,
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\CROW_c[1] , RASr3, RCKE_2, RCKE_c, \RBAd_0[1] , N_158, N_414_0,
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Ready_0_sqmuxa, N_415_0, \MAin_c[0] , \RowAd_0[1] , \RowAd_0[0] ,
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\RowA[0] , \RowA[1] , \MAin_c[3] , \RowAd_0[3] , \RowAd_0[2] ,
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\RowA[2] , \RowA[3] , \MAin_c[5] , \MAin_c[4] , \RowAd_0[5] ,
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\RowAd_0[4] , \RowA[4] , \RowA[5] , \MAin_c[7] , \MAin_c[6] ,
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\RowAd_0[7] , \RowAd_0[6] , \RowA[6] , \RowA[7] , \MAin_c[9] ,
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\MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] , \RowA[8] , \RowA[9] ,
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nRCAS_0_sqmuxa_1, CmdUFMSDI, N_145, UFMSDI_ens2_i_a0, nUFMCS15,
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UFMSDI_c, UFMSDI_RNO, N_141_i, \Din_c[7] , \Din_c[6] , \Din_c[4] ,
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un1_Din_3, XOR8MEG_3_u_1, XOR8MEG, \Din_c[0] , XOR8MEG_3, \Bank[4] ,
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\Bank[3] , \Bank[1] , \Bank[0] , UFMSDO_c, N_131, N_26, un1_Bank_1_4,
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CASr3, N_168, nRowColSel_0_0, nRRAS_0_sqmuxa, nRowColSel,
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UFMCLK_r_i_a2_2_2, CmdUFMCS, nUFMCS_c, nUFMCS_s_0_m4_yy,
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nUFMCS_s_0_N_5_i, N_129, d_m3_0_a2_0, CmdUFMCLK, i1_i, N_50, N_154,
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un1_nRCAS_6_sqmuxa_i_0, N_45, N_146_i_1, N_27_i_1, N_146_i,
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nRRAS_5_u_i_0, N_24_i, nRWE_s_i_a3_1_0, nRWE_s_i_tz_0, PHI2r3, PHI2r2,
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un1_PHI2r3_0, N_140, un1_FS_14_i_a2_0_1, N_139_8, N_139_6, N_139,
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un1_FS_13_i_a2_1, UFMSDI_ens2_i_a2_4_2, N_34, ADWR_2, N_24, N_27_i_sn,
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N_153, C1WR_1, UFMSDI_ens2_i_o2_0_3, PHI2r, i2_i, N_27_i, \Din_c[2] ,
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CmdEnable16_4, CmdEnable16_3, \Bank[2] , \Bank[7] , un1_Bank_1_3,
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\Bank[6] , \Bank[5] , nRWE_0io_RNO_1, nRWE_0io_RNO_0, N_147_i,
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\RA_c[9] , RDQML_c, \RA_c[8] , RDQMH_c, \RA_c[0] , \RA_c[7] ,
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\RA_c[1] , \RA_c[6] , \RA_c[2] , \RA_c[5] , \RA_c[3] , \RA_c[4] ,
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\CROW_c[0] , RA11d_0, \RBAd_0[0] , \WRD[0] , \UFMSDI_c$n0 , UFMCLK_c,
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\nUFMCS_c$n1 , nRCAS_c, nRRAS_c, nRWE_c, \RCKE_c$n2 , nRCS_c,
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\WRD[7] , \WRD[6] , \WRD[5] , \WRD[4] , \WRD[3] , \WRD[2] , \WRD[1] ,
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\RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI;
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SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ),
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.Q1(\FS[0] ), .FCO(\FS_cry[0] ));
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SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c),
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.FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] ));
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SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ),
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.DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ),
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.Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] ));
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SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ),
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.DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ),
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.Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] ));
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SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ),
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.DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ),
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.Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] ));
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SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ),
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.DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ),
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.Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] ));
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SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ),
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.DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ),
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.Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] ));
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SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ),
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.DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ),
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.Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] ));
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SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ),
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.DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ),
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.Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] ));
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SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ),
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.DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ),
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.Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
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SLICE_10 SLICE_10( .C1(CmdEnable17_5), .B1(CmdEnable17_4), .A1(ADWR),
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.D0(CmdEnable16), .C0(CmdEnable17), .B0(un1_ADWR), .A0(ADSubmitted),
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.DI0(ADSubmitted_r), .CLK(PHI2_c), .F0(ADSubmitted_r), .Q0(ADSubmitted),
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.F1(CmdEnable17));
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SLICE_13 SLICE_13( .D1(un1_Bank_1), .C1(\MAin_c[2] ), .B1(CmdEnable16_5),
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.A1(C1WR_3), .C0(CmdEnable16), .B0(un1_ADWR), .A0(C1Submitted),
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.DI0(C1Submitted_s), .CLK(PHI2_c), .F0(C1Submitted_s), .Q0(C1Submitted),
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.F1(CmdEnable16));
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SLICE_14 SLICE_14( .B1(nFWE_c), .A1(nCCAS_c), .A0(nCCAS_c), .DI0(nCCAS_c_i),
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.M1(CASr), .CLK(RCLK_c), .F0(nCCAS_c_i), .Q0(CASr), .F1(RD_1_i),
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.Q1(CASr2));
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SLICE_17 SLICE_17( .D1(\S[1] ), .C1(RASr2), .B1(\IS[3] ), .A1(CO0),
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.B0(\S[1] ), .A0(CO0), .DI0(N_166_i), .LSR(RASr2), .CLK(RCLK_c),
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.F0(N_166_i), .Q0(CO0), .F1(Ready_0_sqmuxa_0_a3_2));
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SLICE_18 SLICE_18( .B1(ADSubmitted), .A1(CmdEnable), .D0(C1Submitted),
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.C0(un1_CMDWR), .B0(CmdEnable), .A0(CmdEnable17), .DI0(CmdEnable_s),
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.M0(CmdEnable16), .CLK(PHI2_c), .OFX0(CmdEnable_s), .Q0(CmdEnable));
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SLICE_19 SLICE_19( .C1(N_36), .B1(\Din_c[5] ), .A1(\Din_c[1] ), .D0(N_94),
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.C0(N_60), .B0(N_59), .A0(LEDEN), .DI0(N_14_i), .CE(XOR8MEG18),
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.CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN), .F1(N_60));
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SLICE_20 SLICE_20( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36),
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.A1(XOR8MEG18), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa),
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.DI0(N_412_0), .CLK(PHI2_c), .F0(N_412_0), .Q0(CmdSubmitted),
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.F1(CmdUFMCLK_1_sqmuxa));
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SLICE_21 SLICE_21( .C1(N_36), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(n8MEGEN),
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.B0(N_94), .A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_12_i), .CE(XOR8MEG18),
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.CLK(PHI2_c), .F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(N_94));
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SLICE_22 SLICE_22( .D1(nFWE_c), .C1(\MAin_c[1] ), .B1(ADWR_6), .A1(ADWR_3),
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.A0(nFWE_c), .DI0(nFWE_c_i), .CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr),
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.F1(CMDWR_2));
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SLICE_23 SLICE_23( .D1(Ready), .C1(N_151), .B1(\IS[3] ), .A1(\IS[0] ),
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.C0(Ready), .B0(N_151), .A0(\IS[0] ), .DI0(N_60_i_i), .CLK(RCLK_c),
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.F0(N_60_i_i), .Q0(\IS[0] ), .F1(RA10s_i));
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SLICE_24 SLICE_24( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ),
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.A0(\IS[0] ), .DI1(N_180_i), .DI0(IS_n1_0_x2), .CE(N_48_i), .CLK(RCLK_c),
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.F0(IS_n1_0_x2), .Q0(\IS[1] ), .F1(N_180_i), .Q1(\IS[2] ));
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SLICE_25 SLICE_25( .D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ),
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.DI0(N_58_i_i), .CE(N_48_i), .CLK(RCLK_c), .F0(N_58_i_i), .Q0(\IS[3] ));
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SLICE_26 SLICE_26( .D1(N_137_5), .C1(N_137_3), .B1(\FS[16] ), .A1(\FS[10] ),
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.B0(InitReady), .A0(InitReady3), .DI0(N_413_0), .CLK(RCLK_c), .F0(N_413_0),
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.Q0(InitReady), .F1(InitReady3));
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SLICE_27 SLICE_27( .B0(InitReady), .A0(CmdLEDEN), .DI0(N_74_i), .CE(N_28),
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.CLK(RCLK_c), .F0(N_74_i), .Q0(LEDEN));
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SLICE_29 SLICE_29( .C1(nCRAS_c), .B1(LEDEN), .A1(CBR), .A0(nCRAS_c),
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.DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr),
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.F1(LED_c), .Q1(RASr2));
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SLICE_31 SLICE_31( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2),
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.A1(Ready), .D0(Ready), .C0(RCKEEN_8_u_1_0), .B0(RCKEEN_8_u_0_0), .A0(CBR),
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.DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN),
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.F1(RCKEEN_8_u_0_0));
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SLICE_32 SLICE_32( .B1(Ready_fast), .A1(\CROW_c[1] ), .D0(RCKEEN),
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.C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(RASr2), .CLK(RCLK_c),
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.F0(RCKE_2), .Q0(RCKE_c), .F1(\RBAd_0[1] ), .Q1(RASr3));
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SLICE_33 SLICE_33( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .D0(InitReady),
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.C0(N_158), .B0(Ready_0_sqmuxa_0_a3_2), .A0(Ready), .DI0(N_414_0),
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.CLK(RCLK_c), .F0(N_414_0), .Q0(Ready), .F1(N_158));
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SLICE_34 SLICE_34( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_158),
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.A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_415_0),
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.CLK(RCLK_c), .F0(N_415_0), .Q0(Ready_fast), .F1(Ready_0_sqmuxa));
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SLICE_35 SLICE_35( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast),
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.A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c),
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.F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] ));
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SLICE_36 SLICE_36( .B1(Ready_fast), .A1(\MAin_c[3] ), .B0(Ready_fast),
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.A0(\MAin_c[2] ), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c),
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.F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] ));
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SLICE_37 SLICE_37( .B1(Ready_fast), .A1(\MAin_c[5] ), .B0(Ready_fast),
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.A0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c),
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.F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] ));
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SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[7] ), .B0(Ready_fast),
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.A0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c),
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.F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] ));
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SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[9] ), .B0(Ready_fast),
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.A0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c),
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.F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] ));
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SLICE_40 SLICE_40( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR),
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.B0(\S[1] ), .A0(CO0), .DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c),
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.F0(\S_0_i_o2[1] ), .Q0(\S[1] ), .F1(nRCAS_0_sqmuxa_1));
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SLICE_41 SLICE_41( .D1(CmdUFMSDI), .C1(N_145), .B1(UFMSDI_ens2_i_a0),
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.A1(nUFMCS15), .B0(nUFMCS15), .A0(UFMSDI_c), .DI0(UFMSDI_RNO),
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.M0(N_141_i), .CLK(RCLK_c), .OFX0(UFMSDI_RNO), .Q0(UFMSDI_c));
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SLICE_42 SLICE_42( .D1(\Din_c[7] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ),
|
|
.A1(\Din_c[4] ), .D0(un1_Din_3), .C0(XOR8MEG_3_u_1), .B0(XOR8MEG),
|
|
.A0(\Din_c[0] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c),
|
|
.F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(un1_Din_3));
|
|
SLICE_43 SLICE_43( .D1(\Bank[4] ), .C1(\Bank[3] ), .B1(\Bank[1] ),
|
|
.A1(\Bank[0] ), .C0(UFMSDO_c), .B0(InitReady), .A0(Cmdn8MEGEN),
|
|
.DI0(N_131), .CE(N_26), .CLK(RCLK_c), .F0(N_131), .Q0(n8MEGEN),
|
|
.F1(un1_Bank_1_4));
|
|
SLICE_44 SLICE_44( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ),
|
|
.C0(Ready), .B0(N_168), .A0(CO0), .DI0(nRowColSel_0_0),
|
|
.LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel),
|
|
.F1(N_168));
|
|
SLICE_45 SLICE_45( .D1(UFMCLK_r_i_a2_2_2), .C1(nUFMCS15), .B1(InitReady),
|
|
.A1(CmdUFMCS), .D0(nUFMCS_c), .C0(nUFMCS_s_0_m4_yy), .B0(nUFMCS15),
|
|
.A0(N_141_i), .DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i),
|
|
.Q0(nUFMCS_c), .F1(nUFMCS_s_0_m4_yy));
|
|
SLICE_46 SLICE_46( .D1(un1_Bank_1), .C1(\MAin_c[2] ), .B1(C1WR_3), .A1(ADWR),
|
|
.D0(un1_ADWR), .C0(un1_Bank_1), .B0(\MAin_c[2] ), .A0(CMDWR_2),
|
|
.F0(un1_CMDWR), .F1(un1_ADWR));
|
|
SLICE_47 SLICE_47( .D1(N_129), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ),
|
|
.D0(d_m3_0_a2_0), .C0(nUFMCS15), .B0(InitReady), .A0(CmdUFMCLK), .F0(i1_i),
|
|
.F1(nUFMCS15));
|
|
SLICE_48 SLICE_48( .D1(N_137_5), .C1(N_137_3), .B1(InitReady), .A1(\FS[16] ),
|
|
.C0(UFMCLK_r_i_a2_2_2), .B0(N_50), .A0(InitReady), .F0(d_m3_0_a2_0),
|
|
.F1(UFMCLK_r_i_a2_2_2));
|
|
SLICE_49 SLICE_49( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2),
|
|
.D0(\S[1] ), .C0(Ready), .B0(N_154), .A0(N_151),
|
|
.F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_151));
|
|
SLICE_50 SLICE_50( .D1(\Din_c[0] ), .C1(\Din_c[5] ), .B1(Cmdn8MEGEN),
|
|
.A1(N_45), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ), .F0(N_45),
|
|
.F1(Cmdn8MEGEN_4_u_i_0));
|
|
SLICE_51 SLICE_51( .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), .A1(CBR),
|
|
.D0(\S[1] ), .C0(N_146_i_1), .B0(nRCAS_0_sqmuxa_1), .A0(N_27_i_1),
|
|
.F0(N_146_i), .F1(N_146_i_1));
|
|
SLICE_52 SLICE_52( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), .D0(\IS[0] ),
|
|
.C0(N_151), .B0(N_154), .A0(nRRAS_5_u_i_0), .F0(N_24_i), .F1(N_154));
|
|
SLICE_53 SLICE_53( .D1(nRWE_s_i_a3_1_0), .C1(nRRAS_0_sqmuxa), .B1(RCKE_c),
|
|
.A1(RASr2), .C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa),
|
|
.F1(nRWE_s_i_tz_0));
|
|
SLICE_54 SLICE_54( .B1(PHI2r3), .A1(PHI2r2), .D0(un1_PHI2r3_0), .C0(N_140),
|
|
.B0(InitReady), .A0(CmdSubmitted), .F0(N_28), .F1(un1_PHI2r3_0));
|
|
SLICE_55 SLICE_55( .C1(un1_FS_14_i_a2_0_1), .B1(N_139_8), .A1(N_139_6),
|
|
.D0(un1_PHI2r3_0), .C0(N_139), .B0(InitReady), .A0(CmdSubmitted),
|
|
.F0(N_26), .F1(N_139));
|
|
SLICE_56 SLICE_56( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ),
|
|
.C0(un1_FS_13_i_a2_1), .B0(N_139_8), .A0(N_139_6), .F0(N_140),
|
|
.F1(un1_FS_13_i_a2_1));
|
|
SLICE_57 SLICE_57( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36),
|
|
.A1(XOR8MEG18), .D0(un1_Bank_1), .C0(\MAin_c[2] ), .B0(CmdEnable),
|
|
.A0(CMDWR_2), .F0(XOR8MEG18), .F1(CmdSubmitted_1_sqmuxa));
|
|
SLICE_58 SLICE_58( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ),
|
|
.D0(UFMSDI_ens2_i_a2_4_2), .C0(N_129), .B0(N_34), .A0(InitReady),
|
|
.F0(UFMSDI_ens2_i_a0), .F1(UFMSDI_ens2_i_a2_4_2));
|
|
SLICE_59 SLICE_59( .C1(N_129), .B1(InitReady), .A1(\FS[8] ), .D0(N_145),
|
|
.C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[4] ), .F0(N_139_8), .F1(N_145));
|
|
SLICE_60 SLICE_60( .B1(\MAin_c[0] ), .A1(\MAin_c[7] ), .D0(un1_Bank_1),
|
|
.C0(\MAin_c[1] ), .B0(ADWR_3), .A0(ADWR_2), .F0(ADWR), .F1(ADWR_3));
|
|
SLICE_61 SLICE_61( .C1(\S[1] ), .B1(N_24), .A1(CBR), .D0(nRRAS_5_u_i_0),
|
|
.C0(N_154), .B0(N_151), .A0(\IS[0] ), .F0(N_24), .F1(N_27_i_sn));
|
|
SLICE_62 SLICE_62( .B1(\IS[2] ), .A1(\IS[1] ), .D0(Ready), .C0(N_153),
|
|
.B0(N_151), .A0(\IS[0] ), .F0(nRWE_s_i_a3_1_0), .F1(N_153));
|
|
SLICE_63 SLICE_63( .B1(nFWE_c), .A1(\MAin_c[7] ), .D0(\MAin_c[1] ),
|
|
.C0(\MAin_c[0] ), .B0(C1WR_1), .A0(ADWR_6), .M1(\Din_c[1] ),
|
|
.M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR_3), .Q0(\Bank[0] ), .F1(C1WR_1),
|
|
.Q1(\Bank[1] ));
|
|
SLICE_64 SLICE_64( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[15] ),
|
|
.D0(N_129), .C0(\FS[11] ), .B0(\FS[4] ), .A0(\FS[1] ), .F0(N_50),
|
|
.F1(N_129));
|
|
SLICE_65 SLICE_65( .B1(nUFMCS15), .A1(N_141_i), .D0(PHI2r3), .C0(PHI2r2),
|
|
.B0(InitReady), .A0(CmdSubmitted), .M1(PHI2r2), .M0(PHI2r), .CLK(RCLK_c),
|
|
.F0(N_141_i), .Q0(PHI2r2), .F1(i2_i), .Q1(PHI2r3));
|
|
SLICE_66 SLICE_66( .D1(Ready), .C1(N_27_i_sn), .B1(N_27_i_1), .A1(N_24_i),
|
|
.D0(FWEr), .C0(CO0), .B0(CASr3), .A0(CASr2), .F0(N_27_i_1), .F1(N_27_i));
|
|
SLICE_67 SLICE_67( .D1(\MAin_c[6] ), .C1(\MAin_c[5] ), .B1(\MAin_c[4] ),
|
|
.A1(\MAin_c[3] ), .C0(nFWE_c), .B0(\MAin_c[2] ), .A0(ADWR_6), .F0(ADWR_2),
|
|
.F1(ADWR_6));
|
|
SLICE_68 SLICE_68( .B1(\Din_c[5] ), .A1(\Din_c[0] ), .D0(\Din_c[6] ),
|
|
.C0(\Din_c[2] ), .B0(CmdEnable16_4), .A0(CmdEnable16_3), .M0(\Din_c[2] ),
|
|
.CLK(PHI2_c), .F0(CmdEnable16_5), .Q0(\Bank[2] ), .F1(CmdEnable16_3));
|
|
SLICE_69 SLICE_69( .B1(\Bank[7] ), .A1(\Bank[2] ), .D0(un1_Bank_1_4),
|
|
.C0(un1_Bank_1_3), .B0(\Bank[6] ), .A0(\Bank[5] ), .F0(un1_Bank_1),
|
|
.F1(un1_Bank_1_3));
|
|
SLICE_70 SLICE_70( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36),
|
|
.A1(CmdLEDEN), .C0(\Din_c[7] ), .B0(\Din_c[6] ), .A0(\Din_c[4] ),
|
|
.F0(N_36), .F1(N_59));
|
|
SLICE_71 SLICE_71( .C1(CO0), .B1(CASr3), .A1(CASr2), .D0(nRWE_s_i_tz_0),
|
|
.C0(nRWE_0io_RNO_1), .B0(nRWE_0io_RNO_0), .A0(nRCAS_0_sqmuxa_1),
|
|
.F0(N_147_i), .F1(nRWE_0io_RNO_0));
|
|
SLICE_72 SLICE_72( .D1(\FS[17] ), .C1(\FS[14] ), .B1(\FS[13] ),
|
|
.A1(\FS[12] ), .D0(\FS[17] ), .C0(\FS[15] ), .B0(\FS[13] ), .A0(\FS[12] ),
|
|
.F0(N_137_5), .F1(UFMSDI_ens2_i_o2_0_3));
|
|
SLICE_73 SLICE_73( .D1(\Din_c[7] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ),
|
|
.A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[5] ), .B0(\Din_c[4] ),
|
|
.A0(\Din_c[1] ), .M0(CASr2), .CLK(RCLK_c), .F0(CmdEnable17_5), .Q0(CASr3),
|
|
.F1(CmdEnable16_4));
|
|
SLICE_74 SLICE_74( .D1(LEDEN), .C1(\Din_c[3] ), .B1(\Din_c[2] ),
|
|
.A1(\Din_c[1] ), .D0(\Din_c[6] ), .C0(\Din_c[3] ), .B0(\Din_c[2] ),
|
|
.A0(\Din_c[0] ), .M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(CmdEnable17_4),
|
|
.Q0(CBR), .F1(XOR8MEG_3_u_1));
|
|
SLICE_75 SLICE_75( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel),
|
|
.B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQML_c));
|
|
SLICE_76 SLICE_76( .D1(\S[1] ), .C1(Ready), .B1(FWEr), .A1(CBR), .D0(\S[1] ),
|
|
.C0(FWEr), .B0(CO0), .A0(CASr2), .F0(RCKEEN_8_u_1_0), .F1(nRWE_0io_RNO_1));
|
|
SLICE_77 SLICE_77( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ),
|
|
.B0(Ready), .A0(N_151), .F0(N_48_i), .F1(nRRAS_5_u_i_0));
|
|
SLICE_78 SLICE_78( .D1(\FS[5] ), .C1(\FS[3] ), .B1(\FS[2] ), .A1(\FS[0] ),
|
|
.C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .F0(N_34),
|
|
.F1(un1_FS_14_i_a2_0_1));
|
|
SLICE_79 SLICE_79( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel),
|
|
.B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQMH_c));
|
|
SLICE_80 SLICE_80( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ),
|
|
.C0(nRowColSel), .B0(\RowA[0] ), .A0(\MAin_c[0] ), .F0(\RA_c[0] ),
|
|
.F1(\RA_c[7] ));
|
|
SLICE_81 SLICE_81( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ),
|
|
.C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ),
|
|
.F1(\RA_c[6] ));
|
|
SLICE_82 SLICE_82( .C1(nRowColSel), .B1(\RowA[5] ), .A1(\MAin_c[5] ),
|
|
.C0(nRowColSel), .B0(\RowA[2] ), .A0(\MAin_c[2] ), .F0(\RA_c[2] ),
|
|
.F1(\RA_c[5] ));
|
|
SLICE_83 SLICE_83( .C1(nRowColSel), .B1(\RowA[4] ), .A1(\MAin_c[4] ),
|
|
.C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ),
|
|
.F1(\RA_c[4] ));
|
|
SLICE_84 SLICE_84( .B1(Ready_fast), .A1(\CROW_c[0] ), .D0(n8MEGEN),
|
|
.C0(XOR8MEG), .B0(Ready_fast), .A0(\Din_c[6] ), .F0(RA11d_0),
|
|
.F1(\RBAd_0[0] ));
|
|
SLICE_85 SLICE_85( .D1(\FS[10] ), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[1] ),
|
|
.B0(\FS[14] ), .A0(\FS[11] ), .F0(N_137_3), .F1(N_139_6));
|
|
RD_0_ \RD[0]_I ( .IOLDO(\WRD[0] ), .PADDT(RD_1_i), .RD0(RD[0]));
|
|
RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ),
|
|
.CLK(nCCAS_c));
|
|
Dout_0_ \Dout[0]_I ( .PADDO(\MAin_c[3] ), .Dout0(Dout[0]));
|
|
PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
|
|
PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r));
|
|
UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
|
|
UFMSDI UFMSDI_I( .IOLDO(\UFMSDI_c$n0 ), .UFMSDI(UFMSDI));
|
|
UFMSDI_MGIOL UFMSDI_MGIOL( .IOLDO(\UFMSDI_c$n0 ), .OPOS(UFMSDI_RNO),
|
|
.CLK(RCLK_c));
|
|
UFMCLK UFMCLK_I( .IOLDO(UFMCLK_c), .UFMCLK(UFMCLK));
|
|
UFMCLK_MGIOL UFMCLK_MGIOL( .IOLDO(UFMCLK_c), .OPOS(i1_i), .CE(i2_i),
|
|
.CLK(RCLK_c));
|
|
nUFMCS nUFMCS_I( .IOLDO(\nUFMCS_c$n1 ), .nUFMCS(nUFMCS));
|
|
nUFMCS_MGIOL nUFMCS_MGIOL( .IOLDO(\nUFMCS_c$n1 ), .OPOS(nUFMCS_s_0_N_5_i),
|
|
.CLK(RCLK_c));
|
|
RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
|
|
RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
|
|
nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS));
|
|
nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_146_i), .CLK(RCLK_c));
|
|
nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS));
|
|
nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_24_i), .CLK(RCLK_c));
|
|
nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
|
|
nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_147_i), .CLK(RCLK_c));
|
|
RCKE RCKE_I( .IOLDO(\RCKE_c$n2 ), .RCKE(RCKE));
|
|
RCKE_MGIOL RCKE_MGIOL( .IOLDO(\RCKE_c$n2 ), .OPOS(RCKE_2), .CLK(RCLK_c));
|
|
RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
|
|
nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS));
|
|
nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_27_i), .CLK(RCLK_c));
|
|
RD_7_ \RD[7]_I ( .IOLDO(\WRD[7] ), .PADDT(RD_1_i), .RD7(RD[7]));
|
|
RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ),
|
|
.CLK(nCCAS_c));
|
|
RD_6_ \RD[6]_I ( .IOLDO(\WRD[6] ), .PADDT(RD_1_i), .RD6(RD[6]));
|
|
RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ),
|
|
.CLK(nCCAS_c));
|
|
RD_5_ \RD[5]_I ( .IOLDO(\WRD[5] ), .PADDT(RD_1_i), .RD5(RD[5]));
|
|
RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ),
|
|
.CLK(nCCAS_c));
|
|
RD_4_ \RD[4]_I ( .IOLDO(\WRD[4] ), .PADDT(RD_1_i), .RD4(RD[4]));
|
|
RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ),
|
|
.CLK(nCCAS_c));
|
|
RD_3_ \RD[3]_I ( .IOLDO(\WRD[3] ), .PADDT(RD_1_i), .RD3(RD[3]));
|
|
RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ),
|
|
.CLK(nCCAS_c));
|
|
RD_2_ \RD[2]_I ( .IOLDO(\WRD[2] ), .PADDT(RD_1_i), .RD2(RD[2]));
|
|
RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ),
|
|
.CLK(nCCAS_c));
|
|
RD_1_ \RD[1]_I ( .IOLDO(\WRD[1] ), .PADDT(RD_1_i), .RD1(RD[1]));
|
|
RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ),
|
|
.CLK(nCCAS_c));
|
|
RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
|
|
RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0),
|
|
.CLK(PHI2_c));
|
|
RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
|
|
RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(N_153), .LSR(RA10s_i),
|
|
.CLK(RCLK_c));
|
|
RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
|
|
RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
|
|
RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
|
|
RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
|
|
RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
|
|
RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
|
|
RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
|
|
RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
|
|
RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
|
|
RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
|
|
RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1]));
|
|
RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ),
|
|
.CLK(nCRAS_c));
|
|
RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0]));
|
|
RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ),
|
|
.CLK(nCRAS_c));
|
|
LED LED_I( .PADDO(LED_c), .LED(LED));
|
|
nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
|
|
nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
|
|
nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
|
|
Dout_7_ \Dout[7]_I ( .PADDO(nCRAS_c), .Dout7(Dout[7]));
|
|
Dout_6_ \Dout[6]_I ( .PADDO(\MAin_c[9] ), .Dout6(Dout[6]));
|
|
Dout_5_ \Dout[5]_I ( .PADDO(\MAin_c[8] ), .Dout5(Dout[5]));
|
|
Dout_4_ \Dout[4]_I ( .PADDO(\MAin_c[7] ), .Dout4(Dout[4]));
|
|
Dout_3_ \Dout[3]_I ( .PADDO(\MAin_c[6] ), .Dout3(Dout[3]));
|
|
Dout_2_ \Dout[2]_I ( .PADDO(\MAin_c[5] ), .Dout2(Dout[2]));
|
|
Dout_1_ \Dout[1]_I ( .PADDO(\MAin_c[4] ), .Dout1(Dout[1]));
|
|
Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
|
|
Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] ));
|
|
Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
|
|
Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] ));
|
|
Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
|
|
Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] ));
|
|
Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
|
|
Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] ));
|
|
Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
|
|
Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] ));
|
|
Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
|
|
Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CE(CmdUFMCLK_1_sqmuxa),
|
|
.CLK(PHI2_c), .IN(CmdUFMCS));
|
|
Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
|
|
Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa),
|
|
.CLK(PHI2_c), .IN(CmdUFMCLK));
|
|
Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
|
|
Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa),
|
|
.CLK(PHI2_c), .IN(CmdUFMSDI));
|
|
CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
|
|
CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
|
|
MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
|
|
MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
|
|
MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
|
|
MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
|
|
MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
|
|
MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
|
|
MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
|
|
MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
|
|
MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
|
|
MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
|
|
VHI VHI_INST( .Z(VCCI));
|
|
PUR PUR_INST( .PUR(VCCI));
|
|
GSR GSR_INST( .GSR(VCCI));
|
|
endmodule
|
|
|
|
module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly;
|
|
|
|
vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
|
|
|
|
FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module vcc ( output PWR1 );
|
|
|
|
VHI INST1( .Z(PWR1));
|
|
endmodule
|
|
|
|
module gnd ( output PWR0 );
|
|
|
|
VLO INST1( .Z(PWR0));
|
|
endmodule
|
|
|
|
module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
|
|
|
|
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
|
|
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
|
|
defparam inst1.INIT0 = 16'h000A;
|
|
defparam inst1.INIT1 = 16'h300A;
|
|
defparam inst1.INJECT1_0 = "NO";
|
|
defparam inst1.INJECT1_1 = "NO";
|
|
endmodule
|
|
|
|
module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1());
|
|
|
|
specify
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
|
|
|
|
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
|
|
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
|
|
defparam inst1.INIT0 = 16'h5002;
|
|
defparam inst1.INIT1 = 16'h300A;
|
|
defparam inst1.INJECT1_0 = "NO";
|
|
defparam inst1.INJECT1_1 = "NO";
|
|
endmodule
|
|
|
|
module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
|
|
|
|
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
|
|
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
|
|
defparam inst1.INIT0 = 16'h300A;
|
|
defparam inst1.INIT1 = 16'h300A;
|
|
defparam inst1.INJECT1_0 = "NO";
|
|
defparam inst1.INJECT1_1 = "NO";
|
|
endmodule
|
|
|
|
module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_10 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
|
|
|
|
lut4 CmdEnable17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40003 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut4 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40003 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module inverter ( input I, output Z );
|
|
|
|
INV INST1( .A(I), .Z(Z));
|
|
endmodule
|
|
|
|
module SLICE_13 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
|
|
|
|
lut40004 CmdEnable16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40005 C1Submitted_s( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40004 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40005 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_14 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
|
|
|
|
lut40006 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40007 nCCAS_pad_RNISUR8( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40006 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40007 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_17 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40008 Ready_0_sqmuxa_0_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40009 \S_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre0010 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40008 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40009 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q );
|
|
|
|
FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module SLICE_18 ( input B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
|
|
wire GNDI, \SLICE_18/SLICE_18_K1_H1 , \SLICE_18/CmdEnable_s/GATE_H0 , VCCI,
|
|
CLK_NOTIN, DI0_dly, CLK_dly;
|
|
|
|
lut40011 SLICE_18_K1( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(\SLICE_18/SLICE_18_K1_H1 ));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40012 \CmdEnable_s/GATE ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(\SLICE_18/CmdEnable_s/GATE_H0 ));
|
|
vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
selmux2 SLICE_18_K0K1MUX( .D0(\SLICE_18/CmdEnable_s/GATE_H0 ),
|
|
.D1(\SLICE_18/SLICE_18_K1_H1 ), .SD(M0), .Z(OFX0));
|
|
|
|
specify
|
|
(B1 => OFX0) = (0:0:0,0:0:0);
|
|
(A1 => OFX0) = (0:0:0,0:0:0);
|
|
(D0 => OFX0) = (0:0:0,0:0:0);
|
|
(C0 => OFX0) = (0:0:0,0:0:0);
|
|
(B0 => OFX0) = (0:0:0,0:0:0);
|
|
(A0 => OFX0) = (0:0:0,0:0:0);
|
|
(M0 => OFX0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40011 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40012 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hAC8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module selmux2 ( input D0, D1, SD, output Z );
|
|
|
|
MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
|
|
endmodule
|
|
|
|
module SLICE_19 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
|
|
Q0, F1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40013 CmdLEDEN_4_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40014 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40013 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40014 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_20 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
|
|
|
|
lut40015 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40006 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40015 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40016 Cmdn8MEGEN_4_u_i_a2_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40017 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40016 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40017 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_22 ( input D1, C1, B1, A1, A0, DI0, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
|
|
|
|
lut40018 CMDWR_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40007 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40018 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_23 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly;
|
|
|
|
lut40019 RA10_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40020 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40019 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40020 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_24 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
|
|
F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40021 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40022 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40021 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40022 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_25 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40023 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40023 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_26 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly;
|
|
|
|
lut40004 InitReady3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40006 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_27 ( input B0, A0, DI0, CE, CLK, output F0, Q0 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40024 LEDEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40024 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_29 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
|
|
|
|
lut40025 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40007 RASr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40025 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
|
|
Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
lut40026 RCKEEN_8_u_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40027 RCKEEN_8_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40026 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40027 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_32 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0,
|
|
F1, Q1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
|
|
|
|
lut40028 \RBAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40028 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40029 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_33 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly;
|
|
|
|
lut40030 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40030 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40031 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_34 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly;
|
|
|
|
lut40032 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40006 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40032 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_35 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40028 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40028 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40028 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40028 \RowAd[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_37 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40024 \RowAd[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40028 \RowAd[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40028 \RowAd[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40028 \RowAd[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_39 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40024 \RowAd[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40028 \RowAd[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40015 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40006 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre0010 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_41 ( input D1, C1, B1, A1, B0, A0, DI0, M0, CLK, output OFX0, Q0 );
|
|
wire \SLICE_41/SLICE_41_K1_H1 , GNDI, \SLICE_41/UFMSDI_RNO/GATE_H0 , VCCI,
|
|
DI0_dly, CLK_dly;
|
|
|
|
lut40033 SLICE_41_K1( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(\SLICE_41/SLICE_41_K1_H1 ));
|
|
lut40034 \UFMSDI_RNO/GATE ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(\SLICE_41/UFMSDI_RNO/GATE_H0 ));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
selmux2 SLICE_41_K0K1MUX( .D0(\SLICE_41/UFMSDI_RNO/GATE_H0 ),
|
|
.D1(\SLICE_41/SLICE_41_K1_H1 ), .SD(M0), .Z(OFX0));
|
|
|
|
specify
|
|
(D1 => OFX0) = (0:0:0,0:0:0);
|
|
(C1 => OFX0) = (0:0:0,0:0:0);
|
|
(B1 => OFX0) = (0:0:0,0:0:0);
|
|
(A1 => OFX0) = (0:0:0,0:0:0);
|
|
(B0 => OFX0) = (0:0:0,0:0:0);
|
|
(A0 => OFX0) = (0:0:0,0:0:0);
|
|
(M0 => OFX0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40033 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1110) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40034 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
|
|
F0, Q0, F1 );
|
|
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40035 un1_Din_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40036 XOR8MEG_3_u( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40035 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40036 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hA0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
|
|
Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40004 un1_Bank_1_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40037 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40037 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output
|
|
F0, Q0, F1 );
|
|
wire VCCI, DI0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40038 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40039 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre0010 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40038 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40039 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
|
|
Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
lut40040 nUFMCS_s_0_m4_yy( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40041 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre0042 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40040 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40041 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5F4E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module vmuxregsre0042 ( input D0, D1, SD, SP, CK, LSR, output Q );
|
|
|
|
FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40043 un1_ADWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40044 un1_CMDWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40043 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40044 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40035 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40045 UFMCLK_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40045 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0B00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_48 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40015 UFMCLK_r_i_a2_2_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40046 UFMCLK_0io_RNO_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40046 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40019 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40047 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40047 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_50 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40048 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40049 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40048 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40049 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF4F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_51 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40050 nRCAS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40051 nRCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40050 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40051 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_52 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40052 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40053 nRRAS_5_u_i_0_RNILD5I( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40052 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40053 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_53 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40054 nRWE_s_i_tz_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40055 \S_RNICVV51[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40054 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40055 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_54 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40056 un1_PHI2r3_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40057 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40056 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40057 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_55 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut4 un1_FS_14_i_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40057 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40058 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut4 un1_FS_13_i_a2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40058 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40059 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40004 XOR8MEG18( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40059 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40032 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40060 UFMSDI_ens2_i_a0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40060 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_59 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40013 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40015 un1_FS_13_i_a2_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_60 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40028 ADWR_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40004 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40061 nRCS_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40062 nRRAS_5_u_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40061 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40062 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF32) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_62 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40006 RA10_2_sqmuxa_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40063 nRWE_s_i_a3_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40063 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_63 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1,
|
|
Q1 );
|
|
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
|
|
|
|
lut40064 C1WR_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40008 C1WR_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \Bank_0io[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \Bank_0io[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
|
|
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40064 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40052 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40065 UFMCLK_r_i_m2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40065 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_65 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1,
|
|
Q1 );
|
|
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
|
|
|
|
lut40006 UFMCLK_0io_RNO_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40066 PHI2r3_RNITCN41( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre PHI2r2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
|
|
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40066 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40067 nRCS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40068 nRCAS_r_i_a3_1_1_tz( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40067 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40068 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_67 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40004 ADWR_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40016 ADWR_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, M0_dly, CLK_dly;
|
|
|
|
lut40064 CmdEnable16_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40008 CmdEnable16_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \Bank_0io[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_69 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40056 un1_Bank_1_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40004 un1_Bank_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40069 CmdLEDEN_4_u_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40070 Cmdn8MEGEN_4_u_i_o2_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40069 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40070 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40071 nRWE_0io_RNO_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40072 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40071 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40072 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40073 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40004 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40073 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire VCCI, GNDI, M0_dly, CLK_dly;
|
|
|
|
lut40058 CmdEnable16_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40038 CmdEnable17_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly;
|
|
|
|
lut40074 XOR8MEG_3_u_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40075 CmdEnable17_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40074 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h040C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40075 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_75 ( input B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40076 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40077 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40076 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40077 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
|
|
lut40078 nRWE_0io_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40079 RCKEEN_8_u_1_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40078 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40079 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h70CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_77 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40080 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40081 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40080 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40081 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40035 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40082 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40082 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_79 ( input B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40024 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40077 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40077 \un9_RA[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_81 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40077 \un9_RA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_82 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \un9_RA[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40077 \un9_RA[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_83 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \un9_RA[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40077 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_84 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40028 \RBAd[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40083 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40083 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hC048) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_85 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40058 un1_FS_13_i_a2_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40028 InitReady3_0_a2_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_0_ ( input IOLDO, PADDT, output RD0 );
|
|
|
|
xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .PAD(RD0));
|
|
|
|
specify
|
|
(IOLDO => RD0) = (0:0:0,0:0:0);
|
|
(PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf ( input I, T, output PAD );
|
|
|
|
OBW INST1( .I(I), .T(T), .O(PAD));
|
|
endmodule
|
|
|
|
module RD_0__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module mfflsre ( input D0, SP, CK, LSR, output Q );
|
|
|
|
FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module Dout_0_ ( input PADDO, output Dout0 );
|
|
|
|
xo2iobuf0084 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
|
|
|
|
specify
|
|
(PADDO => Dout0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0084 ( input I, output PAD );
|
|
|
|
OB INST5( .I(I), .O(PAD));
|
|
endmodule
|
|
|
|
module PHI2 ( output PADDI, input PHI2 );
|
|
|
|
xo2iobuf0085 PHI2_pad( .Z(PADDI), .PAD(PHI2));
|
|
|
|
specify
|
|
(PHI2 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge PHI2, 0:0:0);
|
|
$width (negedge PHI2, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0085 ( output Z, input PAD );
|
|
|
|
IBPD INST1( .I(PAD), .O(Z));
|
|
endmodule
|
|
|
|
module PHI2_MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module smuxlregsre ( input D0, SP, CK, LSR, output Q );
|
|
|
|
IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module UFMSDO ( output PADDI, input UFMSDO );
|
|
|
|
xo2iobuf0086 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
|
|
|
|
specify
|
|
(UFMSDO => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge UFMSDO, 0:0:0);
|
|
$width (negedge UFMSDO, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0086 ( output Z, input PAD );
|
|
|
|
IB INST1( .I(PAD), .O(Z));
|
|
endmodule
|
|
|
|
module UFMSDI ( input IOLDO, output UFMSDI );
|
|
|
|
xo2iobuf0084 UFMSDI_pad( .I(IOLDO), .PAD(UFMSDI));
|
|
|
|
specify
|
|
(IOLDO => UFMSDI) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module UFMSDI_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \UFMSDI$r0 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module UFMCLK ( input IOLDO, output UFMCLK );
|
|
|
|
xo2iobuf0084 UFMCLK_pad( .I(IOLDO), .PAD(UFMCLK));
|
|
|
|
specify
|
|
(IOLDO => UFMCLK) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module UFMCLK_MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre UFMCLK_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nUFMCS ( input IOLDO, output nUFMCS );
|
|
|
|
xo2iobuf0084 nUFMCS_pad( .I(IOLDO), .PAD(nUFMCS));
|
|
|
|
specify
|
|
(IOLDO => nUFMCS) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nUFMCS_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0087 \nUFMCS$r1 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module mfflsre0087 ( input D0, SP, CK, LSR, output Q );
|
|
|
|
FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module RDQML ( input PADDO, output RDQML );
|
|
|
|
xo2iobuf0084 RDQML_pad( .I(PADDO), .PAD(RDQML));
|
|
|
|
specify
|
|
(PADDO => RDQML) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RDQMH ( input PADDO, output RDQMH );
|
|
|
|
xo2iobuf0084 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
|
|
|
|
specify
|
|
(PADDO => RDQMH) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRCAS ( input IOLDO, output nRCAS );
|
|
|
|
xo2iobuf0084 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
|
|
|
|
specify
|
|
(IOLDO => nRCAS) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0087 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRRAS ( input IOLDO, output nRRAS );
|
|
|
|
xo2iobuf0084 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
|
|
|
|
specify
|
|
(IOLDO => nRRAS) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0087 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRWE ( input IOLDO, output nRWE );
|
|
|
|
xo2iobuf0084 nRWE_pad( .I(IOLDO), .PAD(nRWE));
|
|
|
|
specify
|
|
(IOLDO => nRWE) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0087 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RCKE ( input IOLDO, output RCKE );
|
|
|
|
xo2iobuf0084 RCKE_pad( .I(IOLDO), .PAD(RCKE));
|
|
|
|
specify
|
|
(IOLDO => RCKE) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RCKE_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \RCKE$r2 ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RCLK ( output PADDI, input RCLK );
|
|
|
|
xo2iobuf0086 RCLK_pad( .Z(PADDI), .PAD(RCLK));
|
|
|
|
specify
|
|
(RCLK => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RCLK, 0:0:0);
|
|
$width (negedge RCLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRCS ( input IOLDO, output nRCS );
|
|
|
|
xo2iobuf0084 nRCS_pad( .I(IOLDO), .PAD(nRCS));
|
|
|
|
specify
|
|
(IOLDO => nRCS) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRCS_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0087 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_7_ ( input IOLDO, PADDT, output RD7 );
|
|
|
|
xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .PAD(RD7));
|
|
|
|
specify
|
|
(IOLDO => RD7) = (0:0:0,0:0:0);
|
|
(PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_7__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_6_ ( input IOLDO, PADDT, output RD6 );
|
|
|
|
xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .PAD(RD6));
|
|
|
|
specify
|
|
(IOLDO => RD6) = (0:0:0,0:0:0);
|
|
(PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_6__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_5_ ( input IOLDO, PADDT, output RD5 );
|
|
|
|
xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .PAD(RD5));
|
|
|
|
specify
|
|
(IOLDO => RD5) = (0:0:0,0:0:0);
|
|
(PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_5__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_4_ ( input IOLDO, PADDT, output RD4 );
|
|
|
|
xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .PAD(RD4));
|
|
|
|
specify
|
|
(IOLDO => RD4) = (0:0:0,0:0:0);
|
|
(PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_4__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_3_ ( input IOLDO, PADDT, output RD3 );
|
|
|
|
xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .PAD(RD3));
|
|
|
|
specify
|
|
(IOLDO => RD3) = (0:0:0,0:0:0);
|
|
(PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_3__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_2_ ( input IOLDO, PADDT, output RD2 );
|
|
|
|
xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .PAD(RD2));
|
|
|
|
specify
|
|
(IOLDO => RD2) = (0:0:0,0:0:0);
|
|
(PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_2__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_1_ ( input IOLDO, PADDT, output RD1 );
|
|
|
|
xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .PAD(RD1));
|
|
|
|
specify
|
|
(IOLDO => RD1) = (0:0:0,0:0:0);
|
|
(PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_1__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_11_ ( input IOLDO, output RA11 );
|
|
|
|
xo2iobuf0084 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
|
|
|
|
specify
|
|
(IOLDO => RA11) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_10_ ( input IOLDO, output RA10 );
|
|
|
|
xo2iobuf0084 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
|
|
|
|
specify
|
|
(IOLDO => RA10) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
|
|
wire VCCI, OPOS_dly, CLK_dly, LSR_dly;
|
|
|
|
mfflsre0088 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module mfflsre0088 ( input D0, SP, CK, LSR, output Q );
|
|
|
|
FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module RA_9_ ( input PADDO, output RA9 );
|
|
|
|
xo2iobuf0084 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
|
|
|
|
specify
|
|
(PADDO => RA9) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_8_ ( input PADDO, output RA8 );
|
|
|
|
xo2iobuf0084 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
|
|
|
|
specify
|
|
(PADDO => RA8) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_7_ ( input PADDO, output RA7 );
|
|
|
|
xo2iobuf0084 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
|
|
|
|
specify
|
|
(PADDO => RA7) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_6_ ( input PADDO, output RA6 );
|
|
|
|
xo2iobuf0084 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
|
|
|
|
specify
|
|
(PADDO => RA6) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_5_ ( input PADDO, output RA5 );
|
|
|
|
xo2iobuf0084 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
|
|
|
|
specify
|
|
(PADDO => RA5) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_4_ ( input PADDO, output RA4 );
|
|
|
|
xo2iobuf0084 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
|
|
|
|
specify
|
|
(PADDO => RA4) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_3_ ( input PADDO, output RA3 );
|
|
|
|
xo2iobuf0084 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
|
|
|
|
specify
|
|
(PADDO => RA3) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_2_ ( input PADDO, output RA2 );
|
|
|
|
xo2iobuf0084 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
|
|
|
|
specify
|
|
(PADDO => RA2) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_1_ ( input PADDO, output RA1 );
|
|
|
|
xo2iobuf0084 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
|
|
|
|
specify
|
|
(PADDO => RA1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RA_0_ ( input PADDO, output RA0 );
|
|
|
|
xo2iobuf0084 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
|
|
|
|
specify
|
|
(PADDO => RA0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RBA_1_ ( input IOLDO, output RBA1 );
|
|
|
|
xo2iobuf0084 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
|
|
|
|
specify
|
|
(IOLDO => RBA1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RBA_0_ ( input IOLDO, output RBA0 );
|
|
|
|
xo2iobuf0084 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
|
|
|
|
specify
|
|
(IOLDO => RBA0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module LED ( input PADDO, output LED );
|
|
|
|
xo2iobuf0089 LED_pad( .I(PADDO), .PAD(LED));
|
|
|
|
specify
|
|
(PADDO => LED) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0089 ( input I, output PAD );
|
|
|
|
OB INST5( .I(I), .O(PAD));
|
|
endmodule
|
|
|
|
module nFWE ( output PADDI, input nFWE );
|
|
|
|
xo2iobuf0090 nFWE_pad( .Z(PADDI), .PAD(nFWE));
|
|
|
|
specify
|
|
(nFWE => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge nFWE, 0:0:0);
|
|
$width (negedge nFWE, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0090 ( output Z, input PAD );
|
|
|
|
IBPU INST1( .I(PAD), .O(Z));
|
|
endmodule
|
|
|
|
module nCRAS ( output PADDI, input nCRAS );
|
|
|
|
xo2iobuf0090 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
|
|
|
|
specify
|
|
(nCRAS => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge nCRAS, 0:0:0);
|
|
$width (negedge nCRAS, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nCCAS ( output PADDI, input nCCAS );
|
|
|
|
xo2iobuf0090 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
|
|
|
|
specify
|
|
(nCCAS => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge nCCAS, 0:0:0);
|
|
$width (negedge nCCAS, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_7_ ( input PADDO, output Dout7 );
|
|
|
|
xo2iobuf0084 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
|
|
|
|
specify
|
|
(PADDO => Dout7) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_6_ ( input PADDO, output Dout6 );
|
|
|
|
xo2iobuf0084 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
|
|
|
|
specify
|
|
(PADDO => Dout6) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_5_ ( input PADDO, output Dout5 );
|
|
|
|
xo2iobuf0084 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
|
|
|
|
specify
|
|
(PADDO => Dout5) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_4_ ( input PADDO, output Dout4 );
|
|
|
|
xo2iobuf0084 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
|
|
|
|
specify
|
|
(PADDO => Dout4) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_3_ ( input PADDO, output Dout3 );
|
|
|
|
xo2iobuf0084 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
|
|
|
|
specify
|
|
(PADDO => Dout3) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_2_ ( input PADDO, output Dout2 );
|
|
|
|
xo2iobuf0084 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
|
|
|
|
specify
|
|
(PADDO => Dout2) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_1_ ( input PADDO, output Dout1 );
|
|
|
|
xo2iobuf0084 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
|
|
|
|
specify
|
|
(PADDO => Dout1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_7_ ( output PADDI, input Din7 );
|
|
|
|
xo2iobuf0086 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
|
|
|
|
specify
|
|
(Din7 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din7, 0:0:0);
|
|
$width (negedge Din7, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_7__MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_6_ ( output PADDI, input Din6 );
|
|
|
|
xo2iobuf0086 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
|
|
|
|
specify
|
|
(Din6 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din6, 0:0:0);
|
|
$width (negedge Din6, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_6__MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_5_ ( output PADDI, input Din5 );
|
|
|
|
xo2iobuf0086 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
|
|
|
|
specify
|
|
(Din5 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din5, 0:0:0);
|
|
$width (negedge Din5, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_5__MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_4_ ( output PADDI, input Din4 );
|
|
|
|
xo2iobuf0086 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
|
|
|
|
specify
|
|
(Din4 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din4, 0:0:0);
|
|
$width (negedge Din4, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_4__MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_3_ ( output PADDI, input Din3 );
|
|
|
|
xo2iobuf0086 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
|
|
|
|
specify
|
|
(Din3 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din3, 0:0:0);
|
|
$width (negedge Din3, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_3__MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_2_ ( output PADDI, input Din2 );
|
|
|
|
xo2iobuf0086 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
|
|
|
|
specify
|
|
(Din2 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din2, 0:0:0);
|
|
$width (negedge Din2, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_2__MGIOL ( input DI, CE, CLK, output IN );
|
|
wire CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly;
|
|
|
|
smuxlregsre CmdUFMCS( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IN));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_1_ ( output PADDI, input Din1 );
|
|
|
|
xo2iobuf0086 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
|
|
|
|
specify
|
|
(Din1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din1, 0:0:0);
|
|
$width (negedge Din1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_1__MGIOL ( input DI, CE, CLK, output IN );
|
|
wire CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly;
|
|
|
|
smuxlregsre CmdUFMCLK( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IN));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_0_ ( output PADDI, input Din0 );
|
|
|
|
xo2iobuf0086 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
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|
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specify
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|
(Din0 => PADDI) = (0:0:0,0:0:0);
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|
$width (posedge Din0, 0:0:0);
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|
$width (negedge Din0, 0:0:0);
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|
endspecify
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|
|
|
endmodule
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|
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|
module Din_0__MGIOL ( input DI, CE, CLK, output IN );
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|
wire CLK_NOTIN, GNDI, DI_dly, CLK_dly, CE_dly;
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|
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|
smuxlregsre CmdUFMSDI( .D0(DI_dly), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IN));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
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|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
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|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module CROW_1_ ( output PADDI, input CROW1 );
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|
|
|
xo2iobuf0086 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
|
|
|
|
specify
|
|
(CROW1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge CROW1, 0:0:0);
|
|
$width (negedge CROW1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module CROW_0_ ( output PADDI, input CROW0 );
|
|
|
|
xo2iobuf0086 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
|
|
|
|
specify
|
|
(CROW0 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge CROW0, 0:0:0);
|
|
$width (negedge CROW0, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_9_ ( output PADDI, input MAin9 );
|
|
|
|
xo2iobuf0086 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
|
|
|
|
specify
|
|
(MAin9 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin9, 0:0:0);
|
|
$width (negedge MAin9, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_8_ ( output PADDI, input MAin8 );
|
|
|
|
xo2iobuf0086 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
|
|
|
|
specify
|
|
(MAin8 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin8, 0:0:0);
|
|
$width (negedge MAin8, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_7_ ( output PADDI, input MAin7 );
|
|
|
|
xo2iobuf0086 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
|
|
|
|
specify
|
|
(MAin7 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin7, 0:0:0);
|
|
$width (negedge MAin7, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_6_ ( output PADDI, input MAin6 );
|
|
|
|
xo2iobuf0086 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
|
|
|
|
specify
|
|
(MAin6 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin6, 0:0:0);
|
|
$width (negedge MAin6, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_5_ ( output PADDI, input MAin5 );
|
|
|
|
xo2iobuf0086 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
|
|
|
|
specify
|
|
(MAin5 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin5, 0:0:0);
|
|
$width (negedge MAin5, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_4_ ( output PADDI, input MAin4 );
|
|
|
|
xo2iobuf0086 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
|
|
|
|
specify
|
|
(MAin4 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin4, 0:0:0);
|
|
$width (negedge MAin4, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_3_ ( output PADDI, input MAin3 );
|
|
|
|
xo2iobuf0086 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
|
|
|
|
specify
|
|
(MAin3 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin3, 0:0:0);
|
|
$width (negedge MAin3, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_2_ ( output PADDI, input MAin2 );
|
|
|
|
xo2iobuf0086 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
|
|
|
|
specify
|
|
(MAin2 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin2, 0:0:0);
|
|
$width (negedge MAin2, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_1_ ( output PADDI, input MAin1 );
|
|
|
|
xo2iobuf0086 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
|
|
|
|
specify
|
|
(MAin1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin1, 0:0:0);
|
|
$width (negedge MAin1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module MAin_0_ ( output PADDI, input MAin0 );
|
|
|
|
xo2iobuf0086 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
|
|
|
|
specify
|
|
(MAin0 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge MAin0, 0:0:0);
|
|
$width (negedge MAin0, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|