mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-28 21:49:21 +00:00
507 lines
22 KiB
HTML
507 lines
22 KiB
HTML
<HTML>
|
|
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
|
|
<STYLE TYPE="text/css">
|
|
<!--
|
|
body,pre{
|
|
font-family:'Courier New', monospace;
|
|
color: #000000;
|
|
font-size:88%;
|
|
background-color: #ffffff;
|
|
}
|
|
h1 {
|
|
font-weight: bold;
|
|
margin-top: 24px;
|
|
margin-bottom: 10px;
|
|
border-bottom: 3px solid #000; font-size: 1em;
|
|
}
|
|
h2 {
|
|
font-weight: bold;
|
|
margin-top: 18px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.90em;
|
|
}
|
|
h3 {
|
|
font-weight: bold;
|
|
margin-top: 12px;
|
|
margin-bottom: 5px;
|
|
font-size: 0.80em;
|
|
}
|
|
p {
|
|
font-size:78%;
|
|
}
|
|
P.Table {
|
|
margin-top: 4px;
|
|
margin-bottom: 4px;
|
|
margin-right: 4px;
|
|
margin-left: 4px;
|
|
}
|
|
table
|
|
{
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
border-collapse: collapse;
|
|
}
|
|
th {
|
|
font-weight:bold;
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
text-align:left;
|
|
font-size:78%;
|
|
}
|
|
td {
|
|
padding: 4px;
|
|
border-width: 1px 1px 1px 1px;
|
|
border-style: solid solid solid solid;
|
|
border-color: black black black black;
|
|
vertical-align:top;
|
|
font-size:78%;
|
|
}
|
|
a {
|
|
color:#013C9A;
|
|
text-decoration:none;
|
|
}
|
|
|
|
a:visited {
|
|
color:#013C9A;
|
|
}
|
|
|
|
a:hover, a:active {
|
|
text-decoration:underline;
|
|
color:#5BAFD4;
|
|
}
|
|
.pass
|
|
{
|
|
background-color: #00ff00;
|
|
}
|
|
.fail
|
|
{
|
|
background-color: #ff0000;
|
|
}
|
|
.comment
|
|
{
|
|
font-size: 90%;
|
|
font-style: italic;
|
|
}
|
|
|
|
-->
|
|
</STYLE>
|
|
</HEAD>
|
|
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
|
|
|
|
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
|
|
Design name: RAM2GS
|
|
NCD version: 3.3
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-640HC
|
|
Package: TQFP100
|
|
Performance: 4
|
|
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
|
Package Status: Final Version 1.39.
|
|
Performance Hardware Data Status: Final Version 34.4.
|
|
Setup and Hold Report
|
|
|
|
--------------------------------------------------------------------------------
|
|
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
|
Tue Aug 15 22:56:32 2023
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
|
------------------
|
|
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
|
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
|
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
|
Device,speed: LCMXO2-640HC,4
|
|
Report level: verbose report, limited to 1 item per preference
|
|
--------------------------------------------------------------------------------
|
|
|
|
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
|
|
|
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 170 items scored, 0 timing errors detected.
|
|
Report: 47.214MHz is the maximum frequency for this preference.
|
|
|
|
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
Report: 150.150MHz is the maximum frequency for this preference.
|
|
|
|
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
Report: 150.150MHz is the maximum frequency for this preference.
|
|
|
|
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 590 items scored, 0 timing errors detected.
|
|
Report: 86.296MHz is the maximum frequency for this preference.
|
|
|
|
BLOCK ASYNCPATHS
|
|
BLOCK RESETPATHS
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
|
170 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 161.824ns (weighted slack = 323.648ns)
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q Bank_0io[3] (from PHI2_c +)
|
|
Destination: FF Data in CmdEnable (to PHI2_c -)
|
|
|
|
Delay: 10.424ns (36.2% logic, 63.8% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
10.424ns physical path delay Din[3]_MGIOL to SLICE_18 meets
|
|
172.414ns delay constraint less
|
|
0.166ns DIN_SET requirement (totaling 172.248ns) by 161.824ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path Din[3]_MGIOL to SLICE_18:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
C2INP_DEL --- 0.577 *[3]_MGIOL.CLK to *n[3]_MGIOL.IN Din[3]_MGIOL (from PHI2_c)
|
|
ROUTE 1 e 1.234 *n[3]_MGIOL.IN to SLICE_43.C1 Bank[3]
|
|
CTOF_DEL --- 0.495 SLICE_43.C1 to SLICE_43.F1 SLICE_43
|
|
ROUTE 1 e 1.234 SLICE_43.F1 to SLICE_69.D0 un1_Bank_1_4
|
|
CTOF_DEL --- 0.495 SLICE_69.D0 to SLICE_69.F0 SLICE_69
|
|
ROUTE 5 e 1.234 SLICE_69.F0 to SLICE_60.D0 un1_Bank_1
|
|
CTOF_DEL --- 0.495 SLICE_60.D0 to SLICE_60.F0 SLICE_60
|
|
ROUTE 2 e 1.234 SLICE_60.F0 to SLICE_46.A1 ADWR
|
|
CTOF_DEL --- 0.495 SLICE_46.A1 to SLICE_46.F1 SLICE_46
|
|
ROUTE 3 e 0.480 SLICE_46.F1 to SLICE_46.D0 un1_ADWR
|
|
CTOF_DEL --- 0.495 SLICE_46.D0 to SLICE_46.F0 SLICE_46
|
|
ROUTE 1 e 1.234 SLICE_46.F0 to SLICE_18.C0 un1_CMDWR
|
|
CTOOFX_DEL --- 0.721 SLICE_18.C0 to SLICE_18.OFX0 SLICE_18
|
|
ROUTE 1 e 0.001 SLICE_18.OFX0 to SLICE_18.DI0 CmdEnable_s (to PHI2_c)
|
|
--------
|
|
10.424 (36.2% logic, 63.8% route), 7 logic levels.
|
|
|
|
Report: 47.214MHz is the maximum frequency for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 338.168ns
|
|
The internal maximum frequency of the following component is 150.150 MHz
|
|
|
|
Logical Details: Cell type Pin name Component name
|
|
|
|
Destination: PIO PAD nCCAS
|
|
|
|
Delay: 6.660ns -- based on Minimum Pulse Width
|
|
|
|
Report: 150.150MHz is the maximum frequency for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 338.168ns
|
|
The internal maximum frequency of the following component is 150.150 MHz
|
|
|
|
Logical Details: Cell type Pin name Component name
|
|
|
|
Destination: PIO PAD nCRAS
|
|
|
|
Delay: 6.660ns -- based on Minimum Pulse Width
|
|
|
|
Report: 150.150MHz is the maximum frequency for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
|
590 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.412ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q FS[17] (from RCLK_c +)
|
|
Destination: FF Data in LEDEN (to RCLK_c +)
|
|
|
|
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
11.306ns physical path delay SLICE_1 to SLICE_27 meets
|
|
16.000ns delay constraint less
|
|
0.282ns CE_SET requirement (totaling 15.718ns) by 4.412ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_1 to SLICE_27:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c)
|
|
ROUTE 3 e 1.234 SLICE_1.Q0 to SLICE_72.D1 FS[17]
|
|
CTOF_DEL --- 0.495 SLICE_72.D1 to SLICE_72.F1 SLICE_72
|
|
ROUTE 1 e 1.234 SLICE_72.F1 to SLICE_64.C1 UFMSDI_ens2_i_o2_0_3
|
|
CTOF_DEL --- 0.495 SLICE_64.C1 to SLICE_64.F1 SLICE_64
|
|
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_59.C1 N_129
|
|
CTOF_DEL --- 0.495 SLICE_59.C1 to SLICE_59.F1 SLICE_59
|
|
ROUTE 2 e 0.480 SLICE_59.F1 to SLICE_59.D0 N_145
|
|
CTOF_DEL --- 0.495 SLICE_59.D0 to SLICE_59.F0 SLICE_59
|
|
ROUTE 2 e 1.234 SLICE_59.F0 to SLICE_56.B0 N_139_8
|
|
CTOF_DEL --- 0.495 SLICE_56.B0 to SLICE_56.F0 SLICE_56
|
|
ROUTE 1 e 1.234 SLICE_56.F0 to SLICE_54.C0 N_140
|
|
CTOF_DEL --- 0.495 SLICE_54.C0 to SLICE_54.F0 SLICE_54
|
|
ROUTE 1 e 1.234 SLICE_54.F0 to SLICE_27.CE N_28 (to RCLK_c)
|
|
--------
|
|
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
|
|
|
Report: 86.296MHz is the maximum frequency for this preference.
|
|
|
|
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 47.214 MHz| 7
|
|
| | |
|
|
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
|
| | |
|
|
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
|
| | |
|
|
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 86.296 MHz| 7
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
All preferences were met.
|
|
|
|
|
|
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
|
------------------------
|
|
|
|
Found 4 clocks:
|
|
|
|
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: RCLK_c Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
|
|
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: PHI2_c Source: PHI2.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19
|
|
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: RCLK_c Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
|
|
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
Cumulative negative slack: 0
|
|
|
|
Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
|
|
|
|
--------------------------------------------------------------------------------
|
|
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
|
Tue Aug 15 22:56:32 2023
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
|
------------------
|
|
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
|
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
|
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
|
Device,speed: LCMXO2-640HC,M
|
|
Report level: verbose report, limited to 1 item per preference
|
|
--------------------------------------------------------------------------------
|
|
|
|
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
|
|
|
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 170 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 590 items scored, 0 timing errors detected.
|
|
|
|
BLOCK ASYNCPATHS
|
|
BLOCK RESETPATHS
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
|
170 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.447ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q ADSubmitted (from PHI2_c -)
|
|
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
|
|
|
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.434ns physical path delay SLICE_10 to SLICE_10 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_10 to SLICE_10:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
|
|
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
|
|
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
|
|
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
|
|
--------
|
|
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
|
590 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.351ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q CASr (from RCLK_c +)
|
|
Destination: FF Data in CASr2 (to RCLK_c +)
|
|
|
|
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.332ns physical path delay SLICE_14 to SLICE_14 meets
|
|
-0.019ns M_HLD and
|
|
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_14 to SLICE_14:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from RCLK_c)
|
|
ROUTE 1 e 0.199 SLICE_14.Q0 to SLICE_14.M1 CASr (to RCLK_c)
|
|
--------
|
|
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
|
|
|
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
|
|
| | |
|
|
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
|
|
| | |
|
|
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
|
|
| | |
|
|
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
All preferences were met.
|
|
|
|
|
|
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
|
------------------------
|
|
|
|
Found 4 clocks:
|
|
|
|
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: RCLK_c Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
|
|
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: PHI2_c Source: PHI2.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19
|
|
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: RCLK_c Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
|
|
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
Cumulative negative slack: 0
|
|
|
|
Constraints cover 760 paths, 4 nets, and 422 connections (60.03% coverage)
|
|
|
|
|
|
|
|
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
|
---------------
|
|
|
|
Timing errors: 0 (setup), 0 (hold)
|
|
Score: 0 (setup), 0 (hold)
|
|
Cumulative negative slack: 0 (0+0)
|
|
--------------------------------------------------------------------------------
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
<BR>
|
|
</PRE></FONT>
|
|
</BODY>
|
|
</HTML>
|