RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1_synplify.lpf
Zane Kaminski 8cbf2f47ad RC?
2023-08-16 05:11:25 -04:00

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#
# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
#
# Period Constraints
FREQUENCY PORT "PHI2" 2.9 MHz;
FREQUENCY PORT "nCCAS" 2.9 MHz;
FREQUENCY PORT "nCRAS" 2.9 MHz;
FREQUENCY PORT "RCLK" 62.5 MHz;
# Output Constraints
# Input Constraints
# Point-to-point Delay Constraints
# Block Path Constraints
BLOCK ASYNCPATHS;
# End of generated Logical Preferences.