mirror of
https://github.com/garrettsworkshop/RAM2GS.git
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24886 lines
864 KiB
VHDL
24886 lines
864 KiB
VHDL
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-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
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-- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd
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-- Netlist created on Wed Aug 16 04:50:39 2023
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-- Netlist written on Wed Aug 16 04:50:41 2023
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-- Design is for device LCMXO256C
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-- Design is for package TQFP100
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-- Design is for performance grade 3
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-- entity vmuxregsre
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity vmuxregsre is
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
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end vmuxregsre;
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architecture Structure of vmuxregsre is
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component FL1P3DX
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generic (GSR: String);
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port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic;
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CK: in Std_logic; SD: in Std_logic; CD: in Std_logic;
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Q: out Std_logic);
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end component;
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begin
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INST01: FL1P3DX
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generic map (GSR => "DISABLED")
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port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
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end Structure;
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-- entity vcc
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity vcc is
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port (PWR1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
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end vcc;
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architecture Structure of vcc is
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component VHI
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port (Z: out Std_logic);
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end component;
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begin
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INST1: VHI
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port map (Z=>PWR1);
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end Structure;
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-- entity gnd
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity gnd is
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port (PWR0: out Std_logic);
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ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
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end gnd;
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architecture Structure of gnd is
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component VLO
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port (Z: out Std_logic);
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end component;
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begin
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INST1: VLO
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port map (Z=>PWR0);
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end Structure;
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-- entity ccu2B
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity ccu2B is
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
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CO1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE;
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end ccu2B;
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architecture Structure of ccu2B is
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component CCU2
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generic (INIT0: String; INIT1: String; INJECT1_0: String;
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INJECT1_1: String);
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port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic;
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C0: in Std_logic; D0: in Std_logic; A1: in Std_logic;
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B1: in Std_logic; C1: in Std_logic; D1: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic;
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COUT1: out Std_logic);
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end component;
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begin
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inst1: CCU2
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generic map (INIT0 => "0x300a", INIT1 => "0x300a", INJECT1_0 => "NO",
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INJECT1_1 => "NO")
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port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
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C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
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end Structure;
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-- entity SLICE_0
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity SLICE_0 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_0";
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_A1_CLK : VitalDelayType := 0 ns;
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tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_A0_CLK : VitalDelayType := 0 ns;
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tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns);
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port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
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Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
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end SLICE_0;
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architecture Structure of SLICE_0 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A1_ipd : std_logic := 'X';
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signal A1_dly : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal A0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal FCO_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal SLICE_0_FS_cry_0_0_S1: Std_logic;
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signal GNDI: Std_logic;
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signal SLICE_0_FS_cry_0_0_S0: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component ccu2B
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
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CO1: out Std_logic);
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end component;
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begin
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FS_1: vmuxregsre
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port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S1, SD=>VCCI, SP=>VCCI,
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CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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FS_0: vmuxregsre
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port map (D0=>VCCI, D1=>SLICE_0_FS_cry_0_0_S0, SD=>VCCI, SP=>VCCI,
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CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
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FS_cry_0_0: ccu2B
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port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
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C1=>GNDI, D1=>GNDI, CI=>VCCI, S0=>SLICE_0_FS_cry_0_0_S0,
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S1=>SLICE_0_FS_cry_0_0_S1, CO0=>open, CO1=>FCO_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
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VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out)
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE FCO_zd : std_logic := 'X';
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VARIABLE FCO_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_A1_CLK : x01 := '0';
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VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_A0_CLK : x01 := '0';
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VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => A1_dly,
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TestSignalName => "A1",
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TestDelay => tisd_A1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_A1_CLK_noedge_posedge,
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SetupLow => tsetup_A1_CLK_noedge_posedge,
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HoldHigh => thold_A1_CLK_noedge_posedge,
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HoldLow => thold_A1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => A1_CLK_TimingDatash,
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Violation => tviol_A1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => A0_dly,
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TestSignalName => "A0",
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TestDelay => tisd_A0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_A0_CLK_noedge_posedge,
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SetupLow => tsetup_A0_CLK_noedge_posedge,
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HoldHigh => thold_A0_CLK_noedge_posedge,
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HoldLow => thold_A0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => A0_CLK_TimingDatash,
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Violation => tviol_A0_CLK,
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MsgSeverity => warning);
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END IF;
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Q0_zd := Q0_out;
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Q1_zd := Q1_out;
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FCO_zd := FCO_out;
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
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Paths => (0 => (InputChangeTime => A1_dly'last_event,
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PathDelay => tpd_A1_FCO,
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PathCondition => TRUE),
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1 => (InputChangeTime => A0_dly'last_event,
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PathDelay => tpd_A0_FCO,
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PathCondition => TRUE)),
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GlitchData => FCO_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity ccu20001
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity ccu20001 is
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
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CO1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
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end ccu20001;
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architecture Structure of ccu20001 is
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component CCU2
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generic (INIT0: String; INIT1: String; INJECT1_0: String;
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INJECT1_1: String);
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port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic;
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C0: in Std_logic; D0: in Std_logic; A1: in Std_logic;
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B1: in Std_logic; C1: in Std_logic; D1: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic;
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COUT1: out Std_logic);
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end component;
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begin
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inst1: CCU2
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generic map (INIT0 => "0x300a", INIT1 => "0x5002", INJECT1_0 => "NO",
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INJECT1_1 => "NO")
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port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
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C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1);
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end Structure;
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-- entity SLICE_1
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity SLICE_1 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_1";
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_A1_CLK : VitalDelayType := 0 ns;
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tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_A0_CLK : VitalDelayType := 0 ns;
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tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_FCI_CLK : VitalDelayType := 0 ns;
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tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
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port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
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FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
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end SLICE_1;
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architecture Structure of SLICE_1 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A1_ipd : std_logic := 'X';
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signal A1_dly : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal A0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal FCI_ipd : std_logic := 'X';
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signal FCI_dly : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal SLICE_1_FS_cry_0_16_S1: Std_logic;
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signal GNDI: Std_logic;
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signal SLICE_1_FS_cry_0_16_S0: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component ccu20001
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_17: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_16: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_1_FS_cry_0_16_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_16: ccu20001
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_1_FS_cry_0_16_S0,
|
|
S1=>SLICE_1_FS_cry_0_16_S1, CO0=>open, CO1=>open);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_2
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_2 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_2";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_A1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_A0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_FCI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
|
|
|
|
end SLICE_2;
|
|
|
|
architecture Structure of SLICE_2 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A1_dly : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal A0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal FCI_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal SLICE_2_FS_cry_0_14_S1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_2_FS_cry_0_14_S0: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_15: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_14: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_2_FS_cry_0_14_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_14: ccu2B
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_cry_0_14_S0,
|
|
S1=>SLICE_2_FS_cry_0_14_S1, CO0=>open, CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_3
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_3 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_3";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_A1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_A0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_FCI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
|
|
|
|
end SLICE_3;
|
|
|
|
architecture Structure of SLICE_3 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A1_dly : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal A0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal FCI_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal SLICE_3_FS_cry_0_12_S1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_3_FS_cry_0_12_S0: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_13: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_12: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_3_FS_cry_0_12_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_12: ccu2B
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_3_FS_cry_0_12_S0,
|
|
S1=>SLICE_3_FS_cry_0_12_S1, CO0=>open, CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_4
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_4 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_4";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_A1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_A0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_FCI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
|
|
|
|
end SLICE_4;
|
|
|
|
architecture Structure of SLICE_4 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A1_dly : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal A0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal FCI_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal SLICE_4_FS_cry_0_10_S1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_4_FS_cry_0_10_S0: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_11: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_10: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_4_FS_cry_0_10_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_10: ccu2B
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_4_FS_cry_0_10_S0,
|
|
S1=>SLICE_4_FS_cry_0_10_S1, CO0=>open, CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_5
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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|
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entity SLICE_5 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_5";
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|
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
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tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_A1_CLK : VitalDelayType := 0 ns;
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tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_A0_CLK : VitalDelayType := 0 ns;
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tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_FCI_CLK : VitalDelayType := 0 ns;
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tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
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|
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port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
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FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
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FCO: out Std_logic);
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|
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ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
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end SLICE_5;
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architecture Structure of SLICE_5 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A1_ipd : std_logic := 'X';
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signal A1_dly : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal A0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal FCI_ipd : std_logic := 'X';
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signal FCI_dly : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal FCO_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal SLICE_5_FS_cry_0_8_S1: Std_logic;
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signal GNDI: Std_logic;
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signal SLICE_5_FS_cry_0_8_S0: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component ccu2B
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
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CO1: out Std_logic);
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end component;
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begin
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FS_9: vmuxregsre
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port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S1, SD=>VCCI, SP=>VCCI,
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CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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FS_8: vmuxregsre
|
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port map (D0=>VCCI, D1=>SLICE_5_FS_cry_0_8_S0, SD=>VCCI, SP=>VCCI,
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CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
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FS_cry_0_8: ccu2B
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port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
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C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_5_FS_cry_0_8_S0,
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S1=>SLICE_5_FS_cry_0_8_S1, CO0=>open, CO1=>FCO_out);
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|
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-- INPUT PATH DELAYs
|
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WireDelay : BLOCK
|
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BEGIN
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
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END BLOCK;
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|
|
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-- Setup and Hold DELAYs
|
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SignalDelay : BLOCK
|
|
BEGIN
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VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
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VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
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END BLOCK;
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|
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VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
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VARIABLE Q0_zd : std_logic := 'X';
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|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
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|
VARIABLE Q1_zd : std_logic := 'X';
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|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
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|
VARIABLE FCO_zd : std_logic := 'X';
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VARIABLE FCO_GlitchData : VitalGlitchDataType;
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|
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|
VARIABLE tviol_A1_CLK : x01 := '0';
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VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_A0_CLK : x01 := '0';
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VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_FCI_CLK : x01 := '0';
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VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
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|
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|
BEGIN
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|
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => A1_dly,
|
|
TestSignalName => "A1",
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TestDelay => tisd_A1_CLK,
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|
RefSignal => CLK_dly,
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|
RefSignalName => "CLK",
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|
RefDelay => ticd_CLK,
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|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
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|
SetupLow => tsetup_A1_CLK_noedge_posedge,
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|
HoldHigh => thold_A1_CLK_noedge_posedge,
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|
HoldLow => thold_A1_CLK_noedge_posedge,
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|
CheckEnabled => TRUE,
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|
RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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|
TimingData => A1_CLK_TimingDatash,
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|
Violation => tviol_A1_CLK,
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|
MsgSeverity => warning);
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|
VitalSetupHoldCheck (
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TestSignal => A0_dly,
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TestSignalName => "A0",
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TestDelay => tisd_A0_CLK,
|
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RefSignal => CLK_dly,
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|
RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_A0_CLK_noedge_posedge,
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|
SetupLow => tsetup_A0_CLK_noedge_posedge,
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|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
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|
HeaderMsg => InstancePath,
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|
TimingData => A0_CLK_TimingDatash,
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|
Violation => tviol_A0_CLK,
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|
MsgSeverity => warning);
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|
VitalSetupHoldCheck (
|
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TestSignal => FCI_dly,
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|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
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|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
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HoldHigh => thold_FCI_CLK_noedge_posedge,
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|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
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|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
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|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
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|
END IF;
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|
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|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
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|
GlitchData => Q0_GlitchData,
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|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_6
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_6 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_6";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_A1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_A0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_FCI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
|
|
|
|
end SLICE_6;
|
|
|
|
architecture Structure of SLICE_6 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A1_dly : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal A0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal FCI_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal SLICE_6_FS_cry_0_6_S1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_6_FS_cry_0_6_S0: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_7: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_6: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_6_FS_cry_0_6_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_6: ccu2B
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_cry_0_6_S0,
|
|
S1=>SLICE_6_FS_cry_0_6_S1, CO0=>open, CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_7
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_7 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_7";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_A1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_A0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_FCI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
|
|
|
|
end SLICE_7;
|
|
|
|
architecture Structure of SLICE_7 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A1_dly : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal A0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal FCI_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal SLICE_7_FS_cry_0_4_S1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_7_FS_cry_0_4_S0: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_5: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_4: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_7_FS_cry_0_4_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_4: ccu2B
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_7_FS_cry_0_4_S0,
|
|
S1=>SLICE_7_FS_cry_0_4_S1, CO0=>open, CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_8
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_8 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_8";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_A1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_A0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_FCI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
|
|
|
|
end SLICE_8;
|
|
|
|
architecture Structure of SLICE_8 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A1_dly : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal A0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal FCI_dly : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal SLICE_8_FS_cry_0_2_S1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_8_FS_cry_0_2_S0: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu2B
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic;
|
|
CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S1, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>SLICE_8_FS_cry_0_2_S0, SD=>VCCI, SP=>VCCI,
|
|
CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_2: ccu2B
|
|
port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_8_FS_cry_0_2_S0,
|
|
S1=>SLICE_8_FS_cry_0_2_S1, CO0=>open, CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK);
|
|
VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out,
|
|
FCO_out)
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_A1_CLK : x01 := '0';
|
|
VARIABLE A1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_A0_CLK : x01 := '0';
|
|
VARIABLE A0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_FCI_CLK : x01 := '0';
|
|
VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A1_dly,
|
|
TestSignalName => "A1",
|
|
TestDelay => tisd_A1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A1_CLK_noedge_posedge,
|
|
HoldHigh => thold_A1_CLK_noedge_posedge,
|
|
HoldLow => thold_A1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A1_CLK_TimingDatash,
|
|
Violation => tviol_A1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => A0_dly,
|
|
TestSignalName => "A0",
|
|
TestDelay => tisd_A0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_A0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_A0_CLK_noedge_posedge,
|
|
HoldHigh => thold_A0_CLK_noedge_posedge,
|
|
HoldLow => thold_A0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => A0_CLK_TimingDatash,
|
|
Violation => tviol_A0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => FCI_dly,
|
|
TestSignalName => "FCI",
|
|
TestDelay => tisd_FCI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_FCI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_FCI_CLK_noedge_posedge,
|
|
HoldHigh => thold_FCI_CLK_noedge_posedge,
|
|
HoldLow => thold_FCI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => FCI_CLK_TimingDatash,
|
|
Violation => tviol_FCI_CLK,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_dly'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_dly'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_dly'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut4
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut4 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
|
|
|
|
end lut4;
|
|
|
|
architecture Structure of lut4 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x8000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40002
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40002 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE;
|
|
|
|
end lut40002;
|
|
|
|
architecture Structure of lut40002 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x00F2")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity inverter
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity inverter is
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
|
|
|
|
end inverter;
|
|
|
|
architecture Structure of inverter is
|
|
component INV
|
|
port (A: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST1: INV
|
|
port map (A=>I, Z=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_9
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_9 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_9";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
|
|
|
|
end SLICE_9;
|
|
|
|
architecture Structure of SLICE_9 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40002
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable17_0_a2: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
ADSubmitted_r: lut40002
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
ADSubmitted: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40003
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40003 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
|
|
|
|
end lut40003;
|
|
|
|
architecture Structure of lut40003 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x8080")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40004
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40004 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
|
|
|
|
end lut40004;
|
|
|
|
architecture Structure of lut40004 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xAEEE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_14
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_14 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_14";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE;
|
|
|
|
end SLICE_14;
|
|
|
|
architecture Structure of SLICE_14 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40003
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40004
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable16_0_a2: lut40003
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
C1Submitted_RNO: lut40004
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
C1Submitted: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40005
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40005 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
|
|
|
|
end lut40005;
|
|
|
|
architecture Structure of lut40005 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0800")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40006
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40006 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
|
|
|
|
end lut40006;
|
|
|
|
architecture Structure of lut40006 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xDDDD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0007
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0007 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0007;
|
|
|
|
architecture Structure of vmuxregsre0007 is
|
|
component FL1P3IY
|
|
generic (GSR: String);
|
|
port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic;
|
|
CK: in Std_logic; SD: in Std_logic; CD: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST01: FL1P3IY
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity SLICE_19
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_19 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_19";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE;
|
|
|
|
end SLICE_19;
|
|
|
|
architecture Structure of SLICE_19 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40006
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Ready_0_sqmuxa_0_a3_2: lut40005
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
S_RNO_0: lut40006
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
S_0: vmuxregsre0007
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40008
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40008 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE;
|
|
|
|
end lut40008;
|
|
|
|
architecture Structure of lut40008 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xEEEE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40009
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40009 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
|
|
|
|
end lut40009;
|
|
|
|
architecture Structure of lut40009 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xAC8C")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity selmux2
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity selmux2 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
|
|
|
|
end selmux2;
|
|
|
|
architecture Structure of selmux2 is
|
|
component MUX21
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST1: MUX21
|
|
port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_20
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_20 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_20";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
OFX0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
|
|
|
|
end SLICE_20;
|
|
|
|
architecture Structure of SLICE_20 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal OFX0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_20_SLICE_20_K1_H1: Std_logic;
|
|
signal SLICE_20_CmdEnable_s_GATE_H0: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40008
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40009
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component selmux2
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
SLICE_20_K1: lut40008
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI,
|
|
Z=>SLICE_20_SLICE_20_K1_H1);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdEnable_s_GATE: lut40009
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd,
|
|
Z=>SLICE_20_CmdEnable_s_GATE_H0);
|
|
CmdEnable: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
SLICE_20_K0K1MUX: selmux2
|
|
port map (D0=>SLICE_20_CmdEnable_s_GATE_H0, D1=>SLICE_20_SLICE_20_K1_H1,
|
|
SD=>M0_ipd, Z=>OFX0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
|
|
VARIABLE OFX0_zd : std_logic := 'X';
|
|
VARIABLE OFX0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
OFX0_zd := OFX0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_OFX0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_OFX0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_OFX0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_OFX0,
|
|
PathCondition => TRUE),
|
|
4 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_OFX0,
|
|
PathCondition => TRUE),
|
|
5 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_OFX0,
|
|
PathCondition => TRUE),
|
|
6 => (InputChangeTime => M0_ipd'last_event,
|
|
PathDelay => tpd_M0_OFX0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => OFX0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40010
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40010 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
|
|
|
|
end lut40010;
|
|
|
|
architecture Structure of lut40010 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0404")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40011
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40011 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
|
|
|
|
end lut40011;
|
|
|
|
architecture Structure of lut40011 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0203")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_21
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_21 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_21";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
|
|
|
|
end SLICE_21;
|
|
|
|
architecture Structure of SLICE_21 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40010
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Cmdn8MEGEN_4_u_i_a2_2: lut40010
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdLEDEN_RNO: lut40011
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdLEDEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40012
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40012 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
|
|
|
|
end lut40012;
|
|
|
|
architecture Structure of lut40012 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xEEEE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_22
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_22 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_22";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
|
|
|
|
end SLICE_22;
|
|
|
|
architecture Structure of SLICE_22 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_14_i_a2: lut40005
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
CmdSubmitted_RNO: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdSubmitted: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40013
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40013 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
|
|
|
|
end lut40013;
|
|
|
|
architecture Structure of lut40013 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x33AB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40014
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40014 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
|
|
|
|
end lut40014;
|
|
|
|
architecture Structure of lut40014 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x5151")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_26
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_26 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_26";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
|
|
|
|
end SLICE_26;
|
|
|
|
architecture Structure of SLICE_26 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40013
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Cmdn8MEGEN_4_u_i_0: lut40013
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
Cmdn8MEGEN_RNO: lut40014
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Cmdn8MEGEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40015
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40015 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
|
|
|
|
end lut40015;
|
|
|
|
architecture Structure of lut40015 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFF32")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40016
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40016 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
|
|
|
|
end lut40016;
|
|
|
|
architecture Structure of lut40016 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xA9A9")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_29
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_29 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_29";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
|
|
|
|
end SLICE_29;
|
|
|
|
architecture Structure of SLICE_29 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40015
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40016
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_5_u_i: lut40015
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
IS_RNO_0: lut40016
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
IS_0: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40017
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40017 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
|
|
|
|
end lut40017;
|
|
|
|
architecture Structure of lut40017 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x7878")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40018
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40018 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
|
|
|
|
end lut40018;
|
|
|
|
architecture Structure of lut40018 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x6666")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_30
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_30 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_30";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
|
|
|
|
end SLICE_30;
|
|
|
|
architecture Structure of SLICE_30 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40017
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
IS_RNO_2: lut40017
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
IS_n1_0_x2: lut40018
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
IS_2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
IS_1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40019
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40019 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
|
|
|
|
end lut40019;
|
|
|
|
architecture Structure of lut40019 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFFEF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40020
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40020 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
|
|
|
|
end lut40020;
|
|
|
|
architecture Structure of lut40020 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x6AAA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_31
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_31 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_31";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
|
|
|
|
end SLICE_31;
|
|
|
|
architecture Structure of SLICE_31 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40019
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40020
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA10_RNO: lut40019
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
IS_RNO_3: lut40020
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
IS_3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40021
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40021 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
|
|
|
|
end lut40021;
|
|
|
|
architecture Structure of lut40021 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x4555")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_32
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_32 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_32";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
|
|
|
|
end SLICE_32;
|
|
|
|
architecture Structure of SLICE_32 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_ens2_i_a0: lut40021
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
InitReady_RNO: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
InitReady: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40022
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40022 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
|
|
|
|
end lut40022;
|
|
|
|
architecture Structure of lut40022 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFBFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40023
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40023 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
|
|
|
|
end lut40023;
|
|
|
|
architecture Structure of lut40023 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x8B8B")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_33
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_33 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_33";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE;
|
|
|
|
end SLICE_33;
|
|
|
|
architecture Structure of SLICE_33 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40022
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40023
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
LED_pad_RNO: lut40022
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
LEDEN_5_i_m2: lut40023
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
LEDEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40024
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40024 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
|
|
|
|
end lut40024;
|
|
|
|
architecture Structure of lut40024 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x2222")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40025
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40025 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
|
|
|
|
end lut40025;
|
|
|
|
architecture Structure of lut40025 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xC6C6")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_39
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_39 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_39";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
|
|
|
|
end SLICE_39;
|
|
|
|
architecture Structure of SLICE_39 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40024
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40025
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG_3_u_0_a3_0: lut40024
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RA11_2: lut40025
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
RA11: vmuxregsre0007
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly,
|
|
LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40026
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40026 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
|
|
|
|
end lut40026;
|
|
|
|
architecture Structure of lut40026 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x70CF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40027
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40027 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
|
|
|
|
end lut40027;
|
|
|
|
architecture Structure of lut40027 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xDCCC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_41
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_41 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_41";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
|
|
|
|
end SLICE_41;
|
|
|
|
architecture Structure of SLICE_41 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40026
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40027
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RCKEEN_8_u_1_0: lut40026
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
RCKEEN_8_u: lut40027
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
PHI2r2: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RCKEEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40028
|
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity lut40028 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
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end lut40028;
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architecture Structure of lut40028 is
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component ROM16X1
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generic (initval: String);
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port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
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AD3: in Std_logic; DO0: out Std_logic);
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end component;
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begin
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INST10: ROM16X1
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generic map (initval => "0x0200")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity lut40029
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity lut40029 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
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end lut40029;
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architecture Structure of lut40029 is
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component ROM16X1
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generic (initval: String);
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port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
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AD3: in Std_logic; DO0: out Std_logic);
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end component;
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begin
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INST10: ROM16X1
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generic map (initval => "0xFE30")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity SLICE_42
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity SLICE_42 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_42";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
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B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
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M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
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Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
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end SLICE_42;
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architecture Structure of SLICE_42 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal D1_ipd : std_logic := 'X';
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal DI0_ipd : std_logic := 'X';
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signal DI0_dly : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal GNDI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40028
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40029
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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nRWE_RNO_5: lut40028
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
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RCKE_2_0: lut40029
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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PHI2r: vmuxregsre
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port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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RCKE: vmuxregsre
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port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(D1_ipd, D1, tipd_D1);
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(D0_ipd, D0, tipd_D0);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
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VitalWireDelay(M1_ipd, M1, tipd_M1);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
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VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
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B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_DI0_CLK : x01 := '0';
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VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_M1_CLK : x01 := '0';
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VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => DI0_dly,
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TestSignalName => "DI0",
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TestDelay => tisd_DI0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI0_CLK_noedge_posedge,
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SetupLow => tsetup_DI0_CLK_noedge_posedge,
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HoldHigh => thold_DI0_CLK_noedge_posedge,
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HoldLow => thold_DI0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI0_CLK_TimingDatash,
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Violation => tviol_DI0_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => M1_dly,
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TestSignalName => "M1",
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TestDelay => tisd_M1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M1_CLK_noedge_posedge,
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SetupLow => tsetup_M1_CLK_noedge_posedge,
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HoldHigh => thold_M1_CLK_noedge_posedge,
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HoldLow => thold_M1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M1_CLK_TimingDatash,
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Violation => tviol_M1_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => D0_ipd'last_event,
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PathDelay => tpd_D0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => C0_ipd'last_event,
|
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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2 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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3 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
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PathDelay => tpd_D1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => C1_ipd'last_event,
|
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PathDelay => tpd_C1_F1,
|
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PathCondition => TRUE),
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2 => (InputChangeTime => B1_ipd'last_event,
|
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PathDelay => tpd_B1_F1,
|
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PathCondition => TRUE),
|
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3 => (InputChangeTime => A1_ipd'last_event,
|
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PathDelay => tpd_A1_F1,
|
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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|
|
-- entity lut40030
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40030 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
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|
|
|
end lut40030;
|
|
|
|
architecture Structure of lut40030 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x5072")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40031
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40031 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
|
|
|
|
end lut40031;
|
|
|
|
architecture Structure of lut40031 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xAEAA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_43
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_43 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_43";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
|
|
|
|
end SLICE_43;
|
|
|
|
architecture Structure of SLICE_43 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40030
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40031
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RCKEEN_8_u_RNO: lut40030
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
Ready_RNO: lut40031
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
PHI2r3: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Ready: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_44
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_44 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_44";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
|
|
|
|
end SLICE_44;
|
|
|
|
architecture Structure of SLICE_44 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal M1_NOTIN: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40028
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Ready_0_sqmuxa_0_a3: lut40028
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
Ready_fast_RNO: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RASr: vmuxregsre
|
|
port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
M1_INVERTERIN: inverter
|
|
port map (I=>M1_dly, Z=>M1_NOTIN);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Ready_fast: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40032
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40032 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
|
|
|
|
end lut40032;
|
|
|
|
architecture Structure of lut40032 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0202")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_50
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_50 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_50";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
|
|
|
|
end SLICE_50;
|
|
|
|
architecture Structure of SLICE_50 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40032
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRowColSel_RNO: lut40032
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
S_0_i_o2_1: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
S_1: vmuxregsre0007
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly,
|
|
LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40033
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40033 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
|
|
|
|
end lut40033;
|
|
|
|
architecture Structure of lut40033 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xF2F7")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40034
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40034 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
|
|
|
|
end lut40034;
|
|
|
|
architecture Structure of lut40034 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x1032")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_51
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_51 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_51";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
|
|
|
|
end SLICE_51;
|
|
|
|
architecture Structure of SLICE_51 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40033
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMCLK_RNO_0: lut40033
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
UFMCLK_RNO: lut40034
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RASr2: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
UFMCLK: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40035
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40035 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
|
|
|
|
end lut40035;
|
|
|
|
architecture Structure of lut40035 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x3B33")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40036
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40036 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
|
|
|
|
end lut40036;
|
|
|
|
architecture Structure of lut40036 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x3210")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_52
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_52 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_52";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
|
|
|
|
end SLICE_52;
|
|
|
|
architecture Structure of SLICE_52 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40035
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40036
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2r3_RNITCN41: lut40035
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
UFMSDI_RNO: lut40036
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RASr3: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
UFMSDI: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40037
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40037 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
|
|
|
|
end lut40037;
|
|
|
|
architecture Structure of lut40037 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xACAC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_55
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_55 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_55";
|
|
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
|
|
|
|
end SLICE_55;
|
|
|
|
architecture Structure of SLICE_55 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_4: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
WRD_5: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_4: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly,
|
|
F0_out, Q0_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40038
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity lut40038 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
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end lut40038;
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architecture Structure of lut40038 is
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component ROM16X1
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generic (initval: String);
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port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
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AD3: in Std_logic; DO0: out Std_logic);
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end component;
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begin
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INST10: ROM16X1
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generic map (initval => "0x4000")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity lut40039
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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|
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entity lut40039 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
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end lut40039;
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architecture Structure of lut40039 is
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component ROM16X1
|
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generic (initval: String);
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port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
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AD3: in Std_logic; DO0: out Std_logic);
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end component;
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begin
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INST10: ROM16X1
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generic map (initval => "0x2C2C")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity SLICE_56
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library IEEE, vital2000, MACHXO;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO.COMPONENTS.ALL;
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entity SLICE_56 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_56";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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|
tperiod_CLK : VitalDelayType := 0 ns;
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|
tpw_CLK_posedge : VitalDelayType := 0 ns;
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|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
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|
tisd_M1_CLK : VitalDelayType := 0 ns;
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|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
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|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
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|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
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|
|
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
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A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
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CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
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|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
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|
|
|
end SLICE_56;
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|
|
|
architecture Structure of SLICE_56 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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|
|
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signal D1_ipd : std_logic := 'X';
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
|
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signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
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|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
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|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
C1WR_0_a2_0_11: lut40038
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
UFMSDI_ens2_i_o2: lut40039
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
WRD_7: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_6: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
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|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
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|
VitalWireDelay(B1_ipd, B1, tipd_B1);
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|
VitalWireDelay(A1_ipd, A1, tipd_A1);
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|
VitalWireDelay(C0_ipd, C0, tipd_C0);
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|
VitalWireDelay(B0_ipd, B0, tipd_B0);
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|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
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|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40040
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40040 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
|
|
|
|
end lut40040;
|
|
|
|
architecture Structure of lut40040 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xF7F0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_57
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_57 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_57";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
|
|
|
|
end SLICE_57;
|
|
|
|
architecture Structure of SLICE_57 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40040
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG_3_u_0_a3_2: lut40005
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
XOR8MEG_3_u_0_a3_3: lut40040
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
XOR8MEG: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40041
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40041 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
|
|
|
|
end lut40041;
|
|
|
|
architecture Structure of lut40041 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0101")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_58
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_58 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_58";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
|
|
|
|
end SLICE_58;
|
|
|
|
architecture Structure of SLICE_58 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40023
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40041
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_en_ss0_0_a2_0: lut40041
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
n8MEGEN_5_i_m2: lut40023
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
n8MEGEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40042
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40042 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
|
|
|
|
end lut40042;
|
|
|
|
architecture Structure of lut40042 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0BFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40043
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40043 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
|
|
|
|
end lut40043;
|
|
|
|
architecture Structure of lut40043 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x2232")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0044
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0044 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0044 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0044;
|
|
|
|
architecture Structure of vmuxregsre0044 is
|
|
component FL1P3BX
|
|
generic (GSR: String);
|
|
port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic;
|
|
CK: in Std_logic; SD: in Std_logic; PD: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST01: FL1P3BX
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity SLICE_59
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_59 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_59";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
|
|
|
|
end SLICE_59;
|
|
|
|
architecture Structure of SLICE_59 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40042
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40043
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0044
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_nRCAS_6_sqmuxa_i_0: lut40042
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCAS_RNO: lut40043
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRCAS: vmuxregsre0044
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40045
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40045 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
|
|
|
|
end lut40045;
|
|
|
|
architecture Structure of lut40045 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xE6EE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40046
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40046 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
|
|
|
|
end lut40046;
|
|
|
|
architecture Structure of lut40046 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x3233")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_60
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_60 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_60";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
|
|
|
|
end SLICE_60;
|
|
|
|
architecture Structure of SLICE_60 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0044
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40045
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40046
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_RNO_0: lut40045
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCS_RNO: lut40046
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRCS: vmuxregsre0044
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40047
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40047 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
|
|
|
|
end lut40047;
|
|
|
|
architecture Structure of lut40047 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x5400")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40048
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40048 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
|
|
|
|
end lut40048;
|
|
|
|
architecture Structure of lut40048 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x5051")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_61
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_61 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_61";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE;
|
|
|
|
end SLICE_61;
|
|
|
|
architecture Structure of SLICE_61 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0044
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40047
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40048
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_5_u_i_0: lut40047
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRRAS_RNO: lut40048
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRRAS: vmuxregsre0044
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40049
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40049 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
|
|
|
|
end lut40049;
|
|
|
|
architecture Structure of lut40049 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x2000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40050
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40050 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
|
|
|
|
end lut40050;
|
|
|
|
architecture Structure of lut40050 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xF4F7")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_62
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_62 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_62";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
|
|
|
|
end SLICE_62;
|
|
|
|
architecture Structure of SLICE_62 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0044
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40050
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_0_sqmuxa_1_0_a3: lut40049
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRWE_RNO: lut40050
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRWE: vmuxregsre0044
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40051
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40051 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
|
|
|
|
end lut40051;
|
|
|
|
architecture Structure of lut40051 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x1000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40052
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40052 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
|
|
|
|
end lut40052;
|
|
|
|
architecture Structure of lut40052 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xDCEC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_63
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_63 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_63";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
|
|
|
|
end SLICE_63;
|
|
|
|
architecture Structure of SLICE_63 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40051
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRowColSel_0_0_a3_0: lut40051
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRowColSel_0_0: lut40052
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRowColSel: vmuxregsre0007
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40053
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40053 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
|
|
|
|
end lut40053;
|
|
|
|
architecture Structure of lut40053 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0001")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40054
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40054 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
|
|
|
|
end lut40054;
|
|
|
|
architecture Structure of lut40054 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xDCFE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_64
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_64 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_64";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
|
|
|
|
end SLICE_64;
|
|
|
|
architecture Structure of SLICE_64 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0044
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40053
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40054
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nUFMCS15_0_a2: lut40053
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nUFMCS_s_0_N_5_i: lut40054
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nUFMCS: vmuxregsre0044
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40055
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40055 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
|
|
|
|
end lut40055;
|
|
|
|
architecture Structure of lut40055 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0010")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40056
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40056 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
|
|
|
|
end lut40056;
|
|
|
|
architecture Structure of lut40056 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x1000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity nRWE_RNO_1_SLICE_65
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nRWE_RNO_1_SLICE_65 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRWE_RNO_1_SLICE_65";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M0: in Std_logic;
|
|
OFX0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRWE_RNO_1_SLICE_65 : ENTITY IS TRUE;
|
|
|
|
end nRWE_RNO_1_SLICE_65;
|
|
|
|
architecture Structure of nRWE_RNO_1_SLICE_65 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal OFX0_out : std_logic := 'X';
|
|
|
|
signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1: Std_logic;
|
|
signal nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0: Std_logic;
|
|
component selmux2
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40055
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40056
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_RNO_1_SLICE_65_K1: lut40055
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd,
|
|
Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1);
|
|
nRWE_RNO_1_GATE: lut40056
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd,
|
|
Z=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0);
|
|
nRWE_RNO_1_SLICE_65_K0K1MUX: selmux2
|
|
port map (D0=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_GATE_H0,
|
|
D1=>nRWE_RNO_1_SLICE_65_nRWE_RNO_1_SLICE_65_K1_H1, SD=>M0_ipd,
|
|
Z=>OFX0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M0_ipd, OFX0_out)
|
|
VARIABLE OFX0_zd : std_logic := 'X';
|
|
VARIABLE OFX0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
OFX0_zd := OFX0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_OFX0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_OFX0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_OFX0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_OFX0,
|
|
PathCondition => TRUE),
|
|
4 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_OFX0,
|
|
PathCondition => TRUE),
|
|
5 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_OFX0,
|
|
PathCondition => TRUE),
|
|
6 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_OFX0,
|
|
PathCondition => TRUE),
|
|
7 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_OFX0,
|
|
PathCondition => TRUE),
|
|
8 => (InputChangeTime => M0_ipd'last_event,
|
|
PathDelay => tpd_M0_OFX0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => OFX0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40057
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40057 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
|
|
|
|
end lut40057;
|
|
|
|
architecture Structure of lut40057 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0B0B")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_66
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_66 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_66";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
|
|
|
|
end SLICE_66;
|
|
|
|
architecture Structure of SLICE_66 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40057
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nUFMCS_s_0_N_5_i_N_2L1: lut40057
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
UFMCLK_r_i_a2_2_2: lut40049
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_1: vmuxregsre0007
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_0: vmuxregsre0007
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40058
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40058 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
|
|
|
|
end lut40058;
|
|
|
|
architecture Structure of lut40058 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0020")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0059
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0059 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0059 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0059;
|
|
|
|
architecture Structure of vmuxregsre0059 is
|
|
component FL1P3JY
|
|
generic (GSR: String);
|
|
port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic;
|
|
CK: in Std_logic; SD: in Std_logic; PD: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST01: FL1P3JY
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity SLICE_67
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_67 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_67";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
|
|
|
|
end SLICE_67;
|
|
|
|
architecture Structure of SLICE_67 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40058
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0059
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdUFMCLK_1_sqmuxa_0_a2: lut40058
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
XOR8MEG18_0_a2: lut40005
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_5: vmuxregsre0059
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_4: vmuxregsre0007
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out,
|
|
Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40060
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40060 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
|
|
|
|
end lut40060;
|
|
|
|
architecture Structure of lut40060 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xEAAA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_68
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_68 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_68";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
|
|
|
|
end SLICE_68;
|
|
|
|
architecture Structure of SLICE_68 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40053
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40060
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_14_i_a2_0_1: lut40053
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_FS_14_i_0: lut40060
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40061
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40061 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
|
|
|
|
end lut40061;
|
|
|
|
architecture Structure of lut40061 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0100")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_69
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_69 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_69";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
|
|
|
|
end SLICE_69;
|
|
|
|
architecture Structure of SLICE_69 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40060
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40061
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_13_i_a2_1: lut40061
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_FS_13_i_0: lut40060
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40062
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40062 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
|
|
|
|
end lut40062;
|
|
|
|
architecture Structure of lut40062 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x8888")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_70
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_70 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_70";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
|
|
|
|
end SLICE_70;
|
|
|
|
architecture Structure of SLICE_70 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40062
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
C1WR_0_a2_0: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
C1WR_0_a2: lut40062
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Bank_1: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Bank_0: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_71
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_71 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_71";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
|
|
|
|
end SLICE_71;
|
|
|
|
architecture Structure of SLICE_71 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
C1WR_0_a2_0_4: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
C1WR_0_a2_0_10: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
Bank_3: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Bank_2: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40063
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40063 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
|
|
|
|
end lut40063;
|
|
|
|
architecture Structure of lut40063 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFEFE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40064
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40064 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
|
|
|
|
end lut40064;
|
|
|
|
architecture Structure of lut40064 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xAAC0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_72
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_72 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_72";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
|
|
|
|
end SLICE_72;
|
|
|
|
architecture Structure of SLICE_72 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40063
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40064
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_ens2_i_o2_0: lut40063
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
UFMCLK_r_i_m2: lut40064
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_3: vmuxregsre0007
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_2: vmuxregsre0007
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40065
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40065 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
|
|
|
|
end lut40065;
|
|
|
|
architecture Structure of lut40065 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFFF7")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_73
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_73 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_73";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
|
|
|
|
end SLICE_73;
|
|
|
|
architecture Structure of SLICE_73 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40065
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
IS_0_sqmuxa_0_o2_0: lut40065
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
IS_0_sqmuxa_0_o2: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdUFMCS: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
CmdUFMCLK: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_74
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_74 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_74";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
|
|
|
|
end SLICE_74;
|
|
|
|
architecture Structure of SLICE_74 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40062
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
InitReady3_0_a2_3: lut40062
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
InitReady3_0_a2: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdUFMSDI: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40066
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40066 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
|
|
|
|
end lut40066;
|
|
|
|
architecture Structure of lut40066 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFDFD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_75
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_75 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_75";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
|
|
|
|
end SLICE_75;
|
|
|
|
architecture Structure of SLICE_75 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal M0_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40041
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40066
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Cmdn8MEGEN_4_u_i_o2_0: lut40066
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdLEDEN_4_u_i_a2_0: lut40041
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
CASr2: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CASr: vmuxregsre
|
|
port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
M0_INVERTERIN: inverter
|
|
port map (I=>M0_dly, Z=>M0_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40067
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40067 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
|
|
|
|
end lut40067;
|
|
|
|
architecture Structure of lut40067 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0002")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_76
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_76 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_76";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
|
|
|
|
end SLICE_76;
|
|
|
|
architecture Structure of SLICE_76 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40024
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40067
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable16_0_a2_4: lut40024
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdEnable16_0_a2_4_0: lut40067
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
Bank_5: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Bank_4: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40068
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40068 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
|
|
|
|
end lut40068;
|
|
|
|
architecture Structure of lut40068 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x4444")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_77
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_77 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_77";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
|
|
|
|
end SLICE_77;
|
|
|
|
architecture Structure of SLICE_77 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40068
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable16_0_a2_1: lut40068
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdEnable16_0_a2_5: lut40049
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
Bank_7: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
Bank_6: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40069
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40069 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
|
|
|
|
end lut40069;
|
|
|
|
architecture Structure of lut40069 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x7777")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_78
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_78 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_78";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
|
|
|
|
end SLICE_78;
|
|
|
|
architecture Structure of SLICE_78 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal M1_NOTIN: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal M0_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40058
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40069
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable17_0_o2: lut40069
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdEnable17_0_a2_4: lut40058
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CBR_fast: vmuxregsre
|
|
port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
M1_INVERTERIN: inverter
|
|
port map (I=>M1_dly, Z=>M1_NOTIN);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
CBR: vmuxregsre
|
|
port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
M0_INVERTERIN: inverter
|
|
port map (I=>M0_dly, Z=>M0_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40070
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40070 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
|
|
|
|
end lut40070;
|
|
|
|
architecture Structure of lut40070 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x2020")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_79
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_79 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_79";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
|
|
|
|
end SLICE_79;
|
|
|
|
architecture Structure of SLICE_79 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40070
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_RNO_2: lut40070
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRWE_RNO_0: lut40038
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
WRD_1: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_0: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40071
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40071 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
|
|
|
|
end lut40071;
|
|
|
|
architecture Structure of lut40071 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x4101")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_80
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_80 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_80";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
|
|
|
|
end SLICE_80;
|
|
|
|
architecture Structure of SLICE_80 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40024
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0059
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40071
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_RNO_1: lut40024
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRCAS_RNO_0: lut40071
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RowA_9: vmuxregsre0059
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_8: vmuxregsre0007
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40072
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40072 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
|
|
|
|
end lut40072;
|
|
|
|
architecture Structure of lut40072 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xFFFE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_81
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_81 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_81";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
|
|
|
|
end SLICE_81;
|
|
|
|
architecture Structure of SLICE_81 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal M1_NOTIN: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal M0_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40072
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_ens2_i_o2_0_3: lut40072
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
InitReady3_0_a2_5: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
FWEr_fast: vmuxregsre
|
|
port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
M1_INVERTERIN: inverter
|
|
port map (I=>M1_dly, Z=>M1_NOTIN);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
FWEr: vmuxregsre
|
|
port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
M0_INVERTERIN: inverter
|
|
port map (I=>M0_dly, Z=>M0_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40073
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40073 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
|
|
|
|
end lut40073;
|
|
|
|
architecture Structure of lut40073 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x3222")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40074
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40074 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
|
|
|
|
end lut40074;
|
|
|
|
architecture Structure of lut40074 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0222")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_82
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_82 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_82";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
|
|
|
|
end SLICE_82;
|
|
|
|
architecture Structure of SLICE_82 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40073
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40074
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdLEDEN_4_u_i_a2: lut40073
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
CmdSubmitted_1_sqmuxa_0_a2: lut40074
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CASr3: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40075
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40075 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
|
|
|
|
end lut40075;
|
|
|
|
architecture Structure of lut40075 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x7F7F")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_83
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_83 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_83";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
|
|
|
|
end SLICE_83;
|
|
|
|
architecture Structure of SLICE_83 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40063
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40075
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_nRCAS_6_sqmuxa_i_o2: lut40063
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Ready_0_sqmuxa_0_o2: lut40075
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
RBA_1: vmuxregsre0007
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RBA_0: vmuxregsre0007
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_84
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_84 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_84";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
|
|
|
|
end SLICE_84;
|
|
|
|
architecture Structure of SLICE_84 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40028
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40061
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_ens2_i_a2_4_2: lut40028
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_FS_13_i_a2_6: lut40061
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40076
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40076 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
|
|
|
|
end lut40076;
|
|
|
|
architecture Structure of lut40076 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0040")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_85
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_85 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_85";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
|
|
|
|
end SLICE_85;
|
|
|
|
architecture Structure of SLICE_85 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40053
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40076
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable17_0_a2_3: lut40076
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_Din_4: lut40053
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
WRD_3: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
WRD_2: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_86
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_86 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_86";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
|
|
|
|
end SLICE_86;
|
|
|
|
architecture Structure of SLICE_86 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40069
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQML: lut40069
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_9: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40077
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40077 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
|
|
|
|
end lut40077;
|
|
|
|
architecture Structure of lut40077 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x3232")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_87
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_87 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_87";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
|
|
|
|
end SLICE_87;
|
|
|
|
architecture Structure of SLICE_87 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40077
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_RNO_0: lut40077
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_FS_13_i_a2_8: lut40049
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40078
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40078 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
|
|
|
|
end lut40078;
|
|
|
|
architecture Structure of lut40078 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x0808")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_88
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_88 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_88";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
|
|
|
|
end SLICE_88;
|
|
|
|
architecture Structure of SLICE_88 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0007
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40078
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
C1WR_0_a2_0_3: lut40078
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nCCAS_pad_RNI01SJ: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RowA_7: vmuxregsre0007
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
RowA_6: vmuxregsre0007
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly,
|
|
M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_negedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_negedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_negedge,
|
|
HoldLow => thold_LSR_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40079
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40079 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
|
|
|
|
end lut40079;
|
|
|
|
architecture Structure of lut40079 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xBBBB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_89
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_89 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_89";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
|
|
|
|
end SLICE_89;
|
|
|
|
architecture Structure of SLICE_89 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40079
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQMH: lut40079
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_8: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40080
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40080 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
|
|
|
|
end lut40080;
|
|
|
|
architecture Structure of lut40080 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0xA8A8")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_90
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_90 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_90";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
|
|
|
|
end SLICE_90;
|
|
|
|
architecture Structure of SLICE_90 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40080
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_CMDWR: lut40080
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_0: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_91
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_91 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_91";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
|
|
|
|
end SLICE_91;
|
|
|
|
architecture Structure of SLICE_91 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_7: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_1: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_92
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_92 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_92";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
|
|
|
|
end SLICE_92;
|
|
|
|
architecture Structure of SLICE_92 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_6: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_2: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_93
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_93 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_93";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
|
|
|
|
end SLICE_93;
|
|
|
|
architecture Structure of SLICE_93 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_5: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_3: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40081
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity lut40081 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
|
|
|
|
end lut40081;
|
|
|
|
architecture Structure of lut40081 is
|
|
component ROM16X1
|
|
generic (initval: String);
|
|
port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic;
|
|
AD3: in Std_logic; DO0: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: ROM16X1
|
|
generic map (initval => "0x1111")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_94
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity SLICE_94 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_94";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
|
|
|
|
end SLICE_94;
|
|
|
|
architecture Structure of SLICE_94 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal M0_NOTIN: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0059
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40062
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40081
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
IS_0_sqmuxa_0_o2_0_RNIS63D: lut40081
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RCKEEN_8_u_0_a2_1_s: lut40062
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RA10: vmuxregsre0059
|
|
port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
M0_INVERTERIN: inverter
|
|
port map (I=>M0_dly, Z=>M0_NOTIN);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf is
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE;
|
|
|
|
end mjiobuf;
|
|
|
|
architecture Structure of mjiobuf is
|
|
component IB
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
component OBW
|
|
port (I: in Std_logic; T: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST1: IB
|
|
port map (I=>PADI, O=>Z);
|
|
INST2: OBW
|
|
port map (I=>I, T=>T, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity RD_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_0_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD0 : VitalDelayType := 0 ns;
|
|
tpw_RD0_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD0_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD0: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
|
|
|
|
end RD_0_B;
|
|
|
|
architecture Structure of RD_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD0_ipd : std_logic := 'X';
|
|
signal RD0_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_0: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out,
|
|
PADI=>RD0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD0_zd : std_logic := 'X';
|
|
VARIABLE RD0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD0_RD0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD0_ipd,
|
|
TestSignalName => "RD0",
|
|
Period => tperiod_RD0,
|
|
PulseWidthHigh => tpw_RD0_posedge,
|
|
PulseWidthLow => tpw_RD0_negedge,
|
|
PeriodData => periodcheckinfo_RD0,
|
|
Violation => tviol_RD0_RD0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD0_zd := RD0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD0_ipd'last_event,
|
|
PathDelay => tpd_RD0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf0082
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf0082 is
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf0082 : ENTITY IS TRUE;
|
|
|
|
end mjiobuf0082;
|
|
|
|
architecture Structure of mjiobuf0082 is
|
|
component OB
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST5: OB
|
|
port map (I=>I, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity Dout_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
|
|
|
|
end Dout_0_B;
|
|
|
|
architecture Structure of Dout_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout0_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_0: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
|
|
VARIABLE Dout0_zd : std_logic := 'X';
|
|
VARIABLE Dout0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout0_zd := Dout0_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf0083
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf0083 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf0083 : ENTITY IS TRUE;
|
|
|
|
end mjiobuf0083;
|
|
|
|
architecture Structure of mjiobuf0083 is
|
|
component IBPD
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST1: IBPD
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity PHI2B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity PHI2B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "PHI2B";
|
|
|
|
tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_PHI2S : VitalDelayType := 0 ns;
|
|
tpw_PHI2S_posedge : VitalDelayType := 0 ns;
|
|
tpw_PHI2S_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; PHI2S: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
|
|
|
|
end PHI2B;
|
|
|
|
architecture Structure of PHI2B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PHI2S_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0083
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2_pad: mjiobuf0083
|
|
port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_PHI2S_PHI2S : x01 := '0';
|
|
VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => PHI2S_ipd,
|
|
TestSignalName => "PHI2S",
|
|
Period => tperiod_PHI2S,
|
|
PulseWidthHigh => tpw_PHI2S_posedge,
|
|
PulseWidthLow => tpw_PHI2S_negedge,
|
|
PeriodData => periodcheckinfo_PHI2S,
|
|
Violation => tviol_PHI2S_PHI2S,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event,
|
|
PathDelay => tpd_PHI2S_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf0084
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf0084 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf0084 : ENTITY IS TRUE;
|
|
|
|
end mjiobuf0084;
|
|
|
|
architecture Structure of mjiobuf0084 is
|
|
component IB
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST1: IB
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity UFMSDOB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity UFMSDOB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "UFMSDOB";
|
|
|
|
tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_UFMSDOS : VitalDelayType := 0 ns;
|
|
tpw_UFMSDOS_posedge : VitalDelayType := 0 ns;
|
|
tpw_UFMSDOS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE;
|
|
|
|
end UFMSDOB;
|
|
|
|
architecture Structure of UFMSDOB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal UFMSDOS_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDO_pad: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0';
|
|
VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => UFMSDOS_ipd,
|
|
TestSignalName => "UFMSDOS",
|
|
Period => tperiod_UFMSDOS,
|
|
PulseWidthHigh => tpw_UFMSDOS_posedge,
|
|
PulseWidthLow => tpw_UFMSDOS_negedge,
|
|
PeriodData => periodcheckinfo_UFMSDOS,
|
|
Violation => tviol_UFMSDOS_UFMSDOS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event,
|
|
PathDelay => tpd_UFMSDOS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf0085
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf0085 is
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf0085 : ENTITY IS TRUE;
|
|
|
|
end mjiobuf0085;
|
|
|
|
architecture Structure of mjiobuf0085 is
|
|
component OB
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST5: OB
|
|
port map (I=>I, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity UFMSDIB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity UFMSDIB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "UFMSDIB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
|
|
tpd_PADDO_UFMSDIS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE;
|
|
|
|
end UFMSDIB;
|
|
|
|
architecture Structure of UFMSDIB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal UFMSDIS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMSDI_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>UFMSDIS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out)
|
|
VARIABLE UFMSDIS_zd : std_logic := 'X';
|
|
VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
UFMSDIS_zd := UFMSDIS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_UFMSDIS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => UFMSDIS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity UFMCLKB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity UFMCLKB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "UFMCLKB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
|
|
tpd_PADDO_UFMCLKS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE;
|
|
|
|
end UFMCLKB;
|
|
|
|
architecture Structure of UFMCLKB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal UFMCLKS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
UFMCLK_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>UFMCLKS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out)
|
|
VARIABLE UFMCLKS_zd : std_logic := 'X';
|
|
VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
UFMCLKS_zd := UFMCLKS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_UFMCLKS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => UFMCLKS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nUFMCSB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nUFMCSB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nUFMCSB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
|
|
tpd_PADDO_nUFMCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE;
|
|
|
|
end nUFMCSB;
|
|
|
|
architecture Structure of nUFMCSB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nUFMCSS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nUFMCS_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>nUFMCSS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out)
|
|
VARIABLE nUFMCSS_zd : std_logic := 'X';
|
|
VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nUFMCSS_zd := nUFMCSS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nUFMCSS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nUFMCSS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RDQMLB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RDQMLB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RDQMLB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RDQMLS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RDQMLS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
|
|
|
|
end RDQMLB;
|
|
|
|
architecture Structure of RDQMLB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RDQMLS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQML_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
|
|
VARIABLE RDQMLS_zd : std_logic := 'X';
|
|
VARIABLE RDQMLS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RDQMLS_zd := RDQMLS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RDQMLS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RDQMLS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RDQMHB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RDQMHB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RDQMHB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RDQMHS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RDQMHS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
|
|
|
|
end RDQMHB;
|
|
|
|
architecture Structure of RDQMHB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RDQMHS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQMH_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
|
|
VARIABLE RDQMHS_zd : std_logic := 'X';
|
|
VARIABLE RDQMHS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RDQMHS_zd := RDQMHS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RDQMHS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RDQMHS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCASB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nRCASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCASB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRCASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; nRCASS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
|
|
|
|
end nRCASB;
|
|
|
|
architecture Structure of nRCASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRCASS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>nRCASS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out)
|
|
VARIABLE nRCASS_zd : std_logic := 'X';
|
|
VARIABLE nRCASS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRCASS_zd := nRCASS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRCASS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRCASS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRRASB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nRRASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRRASB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRRASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; nRRASS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
|
|
|
|
end nRRASB;
|
|
|
|
architecture Structure of nRRASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRRASS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>nRRASS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out)
|
|
VARIABLE nRRASS_zd : std_logic := 'X';
|
|
VARIABLE nRRASS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRRASS_zd := nRRASS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRRASS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRRASS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRWEB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nRWEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRWEB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRWES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; nRWES: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
|
|
|
|
end nRWEB;
|
|
|
|
architecture Structure of nRWEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRWES_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>nRWES_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRWES_out)
|
|
VARIABLE nRWES_zd : std_logic := 'X';
|
|
VARIABLE nRWES_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRWES_zd := nRWES_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRWES,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRWES_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RCKEB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RCKEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RCKEB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RCKES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RCKES: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
|
|
|
|
end RCKEB;
|
|
|
|
architecture Structure of RCKEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RCKES_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RCKE_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RCKES_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
|
|
VARIABLE RCKES_zd : std_logic := 'X';
|
|
VARIABLE RCKES_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RCKES_zd := RCKES_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RCKES,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RCKES_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RCLKB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RCLKB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RCLKB";
|
|
|
|
tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RCLKS : VitalDelayType := 0 ns;
|
|
tpw_RCLKS_posedge : VitalDelayType := 0 ns;
|
|
tpw_RCLKS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; RCLKS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
|
|
|
|
end RCLKB;
|
|
|
|
architecture Structure of RCLKB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal RCLKS_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
RCLK_pad: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RCLKS_RCLKS : x01 := '0';
|
|
VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RCLKS_ipd,
|
|
TestSignalName => "RCLKS",
|
|
Period => tperiod_RCLKS,
|
|
PulseWidthHigh => tpw_RCLKS_posedge,
|
|
PulseWidthLow => tpw_RCLKS_negedge,
|
|
PeriodData => periodcheckinfo_RCLKS,
|
|
Violation => tviol_RCLKS_RCLKS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event,
|
|
PathDelay => tpd_RCLKS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCSB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nRCSB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCSB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_nRCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; nRCSS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
|
|
|
|
end nRCSB;
|
|
|
|
architecture Structure of nRCSB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal nRCSS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_pad: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>nRCSS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out)
|
|
VARIABLE nRCSS_zd : std_logic := 'X';
|
|
VARIABLE nRCSS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRCSS_zd := nRCSS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_nRCSS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRCSS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_7_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_7_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD7 : VitalDelayType := 0 ns;
|
|
tpw_RD7_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD7_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD7: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
|
|
|
|
end RD_7_B;
|
|
|
|
architecture Structure of RD_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD7_ipd : std_logic := 'X';
|
|
signal RD7_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_7: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out,
|
|
PADI=>RD7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD7_zd : std_logic := 'X';
|
|
VARIABLE RD7_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD7_RD7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD7_ipd,
|
|
TestSignalName => "RD7",
|
|
Period => tperiod_RD7,
|
|
PulseWidthHigh => tpw_RD7_posedge,
|
|
PulseWidthLow => tpw_RD7_negedge,
|
|
PeriodData => periodcheckinfo_RD7,
|
|
Violation => tviol_RD7_RD7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD7_zd := RD7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD7_ipd'last_event,
|
|
PathDelay => tpd_RD7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD7,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_6_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_6_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD6 : VitalDelayType := 0 ns;
|
|
tpw_RD6_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD6_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD6: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
|
|
|
|
end RD_6_B;
|
|
|
|
architecture Structure of RD_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD6_ipd : std_logic := 'X';
|
|
signal RD6_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_6: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out,
|
|
PADI=>RD6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD6_zd : std_logic := 'X';
|
|
VARIABLE RD6_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD6_RD6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD6_ipd,
|
|
TestSignalName => "RD6",
|
|
Period => tperiod_RD6,
|
|
PulseWidthHigh => tpw_RD6_posedge,
|
|
PulseWidthLow => tpw_RD6_negedge,
|
|
PeriodData => periodcheckinfo_RD6,
|
|
Violation => tviol_RD6_RD6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD6_zd := RD6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD6_ipd'last_event,
|
|
PathDelay => tpd_RD6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD6,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_5_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_5_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD5 : VitalDelayType := 0 ns;
|
|
tpw_RD5_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD5_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD5: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
|
|
|
|
end RD_5_B;
|
|
|
|
architecture Structure of RD_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD5_ipd : std_logic := 'X';
|
|
signal RD5_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_5: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out,
|
|
PADI=>RD5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD5_zd : std_logic := 'X';
|
|
VARIABLE RD5_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD5_RD5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD5_ipd,
|
|
TestSignalName => "RD5",
|
|
Period => tperiod_RD5,
|
|
PulseWidthHigh => tpw_RD5_posedge,
|
|
PulseWidthLow => tpw_RD5_negedge,
|
|
PeriodData => periodcheckinfo_RD5,
|
|
Violation => tviol_RD5_RD5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD5_zd := RD5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD5_ipd'last_event,
|
|
PathDelay => tpd_RD5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD5,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_4_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_4_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD4 : VitalDelayType := 0 ns;
|
|
tpw_RD4_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD4_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD4: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
|
|
|
|
end RD_4_B;
|
|
|
|
architecture Structure of RD_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD4_ipd : std_logic := 'X';
|
|
signal RD4_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_4: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out,
|
|
PADI=>RD4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD4_zd : std_logic := 'X';
|
|
VARIABLE RD4_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD4_RD4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD4_ipd,
|
|
TestSignalName => "RD4",
|
|
Period => tperiod_RD4,
|
|
PulseWidthHigh => tpw_RD4_posedge,
|
|
PulseWidthLow => tpw_RD4_negedge,
|
|
PeriodData => periodcheckinfo_RD4,
|
|
Violation => tviol_RD4_RD4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD4_zd := RD4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD4_ipd'last_event,
|
|
PathDelay => tpd_RD4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD4,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_3_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_3_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD3 : VitalDelayType := 0 ns;
|
|
tpw_RD3_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD3_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD3: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
|
|
|
|
end RD_3_B;
|
|
|
|
architecture Structure of RD_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD3_ipd : std_logic := 'X';
|
|
signal RD3_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_3: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out,
|
|
PADI=>RD3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD3_zd : std_logic := 'X';
|
|
VARIABLE RD3_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD3_RD3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD3_ipd,
|
|
TestSignalName => "RD3",
|
|
Period => tperiod_RD3,
|
|
PulseWidthHigh => tpw_RD3_posedge,
|
|
PulseWidthLow => tpw_RD3_negedge,
|
|
PeriodData => periodcheckinfo_RD3,
|
|
Violation => tviol_RD3_RD3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD3_zd := RD3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD3_ipd'last_event,
|
|
PathDelay => tpd_RD3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD3,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_2_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_2_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD2 : VitalDelayType := 0 ns;
|
|
tpw_RD2_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD2_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD2: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
|
|
|
|
end RD_2_B;
|
|
|
|
architecture Structure of RD_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD2_ipd : std_logic := 'X';
|
|
signal RD2_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_2: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out,
|
|
PADI=>RD2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD2_zd : std_logic := 'X';
|
|
VARIABLE RD2_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD2_RD2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD2_ipd,
|
|
TestSignalName => "RD2",
|
|
Period => tperiod_RD2,
|
|
PulseWidthHigh => tpw_RD2_posedge,
|
|
PulseWidthLow => tpw_RD2_negedge,
|
|
PeriodData => periodcheckinfo_RD2,
|
|
Violation => tviol_RD2_RD2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD2_zd := RD2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD2_ipd'last_event,
|
|
PathDelay => tpd_RD2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD2,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RD_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_1_B";
|
|
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD1 : VitalDelayType := 0 ns;
|
|
tpw_RD1_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD1_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD1: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
|
|
|
|
end RD_1_B;
|
|
|
|
architecture Structure of RD_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RD1_ipd : std_logic := 'X';
|
|
signal RD1_out : std_logic := 'Z';
|
|
|
|
component mjiobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_1: mjiobuf
|
|
port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out,
|
|
PADI=>RD1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD1_zd : std_logic := 'X';
|
|
VARIABLE RD1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD1_RD1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD1_ipd,
|
|
TestSignalName => "RD1",
|
|
Period => tperiod_RD1,
|
|
PulseWidthHigh => tpw_RD1_posedge,
|
|
PulseWidthLow => tpw_RD1_negedge,
|
|
PeriodData => periodcheckinfo_RD1,
|
|
Violation => tviol_RD1_RD1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD1_zd := RD1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD1_ipd'last_event,
|
|
PathDelay => tpd_RD1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RD1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_11_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_11_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_11_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA11 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RA11: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
|
|
|
|
end RA_11_B;
|
|
|
|
architecture Structure of RA_11_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA11_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_11: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA11_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA11_out)
|
|
VARIABLE RA11_zd : std_logic := 'X';
|
|
VARIABLE RA11_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA11_zd := RA11_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA11,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA11_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_10_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_10_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_10_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA10 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RA10: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
|
|
|
|
end RA_10_B;
|
|
|
|
architecture Structure of RA_10_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA10_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_10: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA10_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA10_out)
|
|
VARIABLE RA10_zd : std_logic := 'X';
|
|
VARIABLE RA10_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA10_zd := RA10_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA10,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA10_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_9_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_9_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_9_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA9 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA9: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
|
|
|
|
end RA_9_B;
|
|
|
|
architecture Structure of RA_9_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA9_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_9: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA9_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
|
|
VARIABLE RA9_zd : std_logic := 'X';
|
|
VARIABLE RA9_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA9_zd := RA9_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA9,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA9_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_8_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_8_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_8_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA8 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA8: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
|
|
|
|
end RA_8_B;
|
|
|
|
architecture Structure of RA_8_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA8_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_8: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA8_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
|
|
VARIABLE RA8_zd : std_logic := 'X';
|
|
VARIABLE RA8_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA8_zd := RA8_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA8,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA8_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_7_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_7_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA7: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
|
|
|
|
end RA_7_B;
|
|
|
|
architecture Structure of RA_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA7_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_7: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA7_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
|
|
VARIABLE RA7_zd : std_logic := 'X';
|
|
VARIABLE RA7_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA7_zd := RA7_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_6_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_6_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA6: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
|
|
|
|
end RA_6_B;
|
|
|
|
architecture Structure of RA_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA6_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_6: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA6_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
|
|
VARIABLE RA6_zd : std_logic := 'X';
|
|
VARIABLE RA6_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA6_zd := RA6_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_5_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_5_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA5: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
|
|
|
|
end RA_5_B;
|
|
|
|
architecture Structure of RA_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA5_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_5: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA5_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
|
|
VARIABLE RA5_zd : std_logic := 'X';
|
|
VARIABLE RA5_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA5_zd := RA5_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_4_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_4_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA4: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
|
|
|
|
end RA_4_B;
|
|
|
|
architecture Structure of RA_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA4_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_4: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA4_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
|
|
VARIABLE RA4_zd : std_logic := 'X';
|
|
VARIABLE RA4_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA4_zd := RA4_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_3_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_3_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA3: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
|
|
|
|
end RA_3_B;
|
|
|
|
architecture Structure of RA_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA3_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_3: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA3_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
|
|
VARIABLE RA3_zd : std_logic := 'X';
|
|
VARIABLE RA3_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA3_zd := RA3_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_2_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_2_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA2: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
|
|
|
|
end RA_2_B;
|
|
|
|
architecture Structure of RA_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA2_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_2: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA2_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
|
|
VARIABLE RA2_zd : std_logic := 'X';
|
|
VARIABLE RA2_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA2_zd := RA2_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
|
|
|
|
end RA_1_B;
|
|
|
|
architecture Structure of RA_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA1_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_1: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA1_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
|
|
VARIABLE RA1_zd : std_logic := 'X';
|
|
VARIABLE RA1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA1_zd := RA1_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RA_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
|
|
|
|
end RA_0_B;
|
|
|
|
architecture Structure of RA_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA0_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_0: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RA0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
|
|
VARIABLE RA0_zd : std_logic := 'X';
|
|
VARIABLE RA0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA0_zd := RA0_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RBA_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RBA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RBA1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
|
|
|
|
end RBA_1_B;
|
|
|
|
architecture Structure of RBA_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RBA1_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_pad_1: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RBA1_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RBA1_out)
|
|
VARIABLE RBA1_zd : std_logic := 'X';
|
|
VARIABLE RBA1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RBA1_zd := RBA1_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RBA1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RBA1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RBA_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RBA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; RBA0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
|
|
|
|
end RBA_0_B;
|
|
|
|
architecture Structure of RBA_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RBA0_out : std_logic := 'X';
|
|
|
|
component mjiobuf0085
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_pad_0: mjiobuf0085
|
|
port map (I=>PADDO_ipd, PAD=>RBA0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RBA0_out)
|
|
VARIABLE RBA0_zd : std_logic := 'X';
|
|
VARIABLE RBA0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RBA0_zd := RBA0_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RBA0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RBA0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf0086
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf0086 is
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf0086 : ENTITY IS TRUE;
|
|
|
|
end mjiobuf0086;
|
|
|
|
architecture Structure of mjiobuf0086 is
|
|
component OB
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST5: OB
|
|
port map (I=>I, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity LEDB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity LEDB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "LEDB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_LEDS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; LEDS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
|
|
|
|
end LEDB;
|
|
|
|
architecture Structure of LEDB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal LEDS_out : std_logic := 'X';
|
|
|
|
component mjiobuf0086
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
LED_pad: mjiobuf0086
|
|
port map (I=>PADDO_ipd, PAD=>LEDS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
|
|
VARIABLE LEDS_zd : std_logic := 'X';
|
|
VARIABLE LEDS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
LEDS_zd := LEDS_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_LEDS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => LEDS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nFWEB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nFWEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nFWEB";
|
|
|
|
tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nFWES : VitalDelayType := 0 ns;
|
|
tpw_nFWES_posedge : VitalDelayType := 0 ns;
|
|
tpw_nFWES_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nFWES: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
|
|
|
|
end nFWEB;
|
|
|
|
architecture Structure of nFWEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nFWES_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nFWE_pad: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>nFWES_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nFWES_nFWES : x01 := '0';
|
|
VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nFWES_ipd,
|
|
TestSignalName => "nFWES",
|
|
Period => tperiod_nFWES,
|
|
PulseWidthHigh => tpw_nFWES_posedge,
|
|
PulseWidthLow => tpw_nFWES_negedge,
|
|
PeriodData => periodcheckinfo_nFWES,
|
|
Violation => tviol_nFWES_nFWES,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nFWES_ipd'last_event,
|
|
PathDelay => tpd_nFWES_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mjiobuf0087
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity mjiobuf0087 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mjiobuf0087 : ENTITY IS TRUE;
|
|
|
|
end mjiobuf0087;
|
|
|
|
architecture Structure of mjiobuf0087 is
|
|
component IBPU
|
|
port (I: in Std_logic; O: out Std_logic);
|
|
end component;
|
|
begin
|
|
INST1: IBPU
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity nCRASB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nCRASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nCRASB";
|
|
|
|
tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nCRASS : VitalDelayType := 0 ns;
|
|
tpw_nCRASS_posedge : VitalDelayType := 0 ns;
|
|
tpw_nCRASS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nCRASS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
|
|
|
|
end nCRASB;
|
|
|
|
architecture Structure of nCRASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nCRASS_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0087
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nCRAS_pad: mjiobuf0087
|
|
port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nCRASS_nCRASS : x01 := '0';
|
|
VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nCRASS_ipd,
|
|
TestSignalName => "nCRASS",
|
|
Period => tperiod_nCRASS,
|
|
PulseWidthHigh => tpw_nCRASS_posedge,
|
|
PulseWidthLow => tpw_nCRASS_negedge,
|
|
PeriodData => periodcheckinfo_nCRASS,
|
|
Violation => tviol_nCRASS_nCRASS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event,
|
|
PathDelay => tpd_nCRASS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nCCASB
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity nCCASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nCCASB";
|
|
|
|
tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nCCASS : VitalDelayType := 0 ns;
|
|
tpw_nCCASS_posedge : VitalDelayType := 0 ns;
|
|
tpw_nCCASS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nCCASS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
|
|
|
|
end nCCASB;
|
|
|
|
architecture Structure of nCCASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nCCASS_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0087
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nCCAS_pad: mjiobuf0087
|
|
port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nCCASS_nCCASS : x01 := '0';
|
|
VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nCCASS_ipd,
|
|
TestSignalName => "nCCASS",
|
|
Period => tperiod_nCCASS,
|
|
PulseWidthHigh => tpw_nCCASS_posedge,
|
|
PulseWidthLow => tpw_nCCASS_negedge,
|
|
PeriodData => periodcheckinfo_nCCASS,
|
|
Violation => tviol_nCCASS_nCCASS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event,
|
|
PathDelay => tpd_nCCASS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_7_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_7_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout7: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
|
|
|
|
end Dout_7_B;
|
|
|
|
architecture Structure of Dout_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout7_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_7: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout7_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
|
|
VARIABLE Dout7_zd : std_logic := 'X';
|
|
VARIABLE Dout7_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout7_zd := Dout7_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_6_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_6_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout6: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
|
|
|
|
end Dout_6_B;
|
|
|
|
architecture Structure of Dout_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout6_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_6: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout6_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
|
|
VARIABLE Dout6_zd : std_logic := 'X';
|
|
VARIABLE Dout6_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout6_zd := Dout6_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_5_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_5_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout5: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
|
|
|
|
end Dout_5_B;
|
|
|
|
architecture Structure of Dout_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout5_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_5: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout5_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
|
|
VARIABLE Dout5_zd : std_logic := 'X';
|
|
VARIABLE Dout5_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout5_zd := Dout5_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_4_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_4_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout4: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
|
|
|
|
end Dout_4_B;
|
|
|
|
architecture Structure of Dout_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout4_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_4: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout4_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
|
|
VARIABLE Dout4_zd : std_logic := 'X';
|
|
VARIABLE Dout4_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout4_zd := Dout4_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_3_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_3_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout3: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
|
|
|
|
end Dout_3_B;
|
|
|
|
architecture Structure of Dout_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout3_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_3: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout3_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
|
|
VARIABLE Dout3_zd : std_logic := 'X';
|
|
VARIABLE Dout3_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout3_zd := Dout3_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_2_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_2_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout2: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
|
|
|
|
end Dout_2_B;
|
|
|
|
architecture Structure of Dout_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout2_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_2: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout2_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
|
|
VARIABLE Dout2_zd : std_logic := 'X';
|
|
VARIABLE Dout2_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout2_zd := Dout2_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Dout_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)
|
|
);
|
|
|
|
port (PADDO: in Std_logic; Dout1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
|
|
|
|
end Dout_1_B;
|
|
|
|
architecture Structure of Dout_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout1_out : std_logic := 'X';
|
|
|
|
component mjiobuf0082
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_1: mjiobuf0082
|
|
port map (I=>PADDO_ipd, PAD=>Dout1_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
|
|
VARIABLE Dout1_zd : std_logic := 'X';
|
|
VARIABLE Dout1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout1_zd := Dout1_out;
|
|
|
|
VitalPathDelay01Z (
|
|
OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_7_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_7_B";
|
|
|
|
tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din7 : VitalDelayType := 0 ns;
|
|
tpw_Din7_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din7_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din7: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
|
|
|
|
end Din_7_B;
|
|
|
|
architecture Structure of Din_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din7_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_7: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din7_Din7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din7_ipd,
|
|
TestSignalName => "Din7",
|
|
Period => tperiod_Din7,
|
|
PulseWidthHigh => tpw_Din7_posedge,
|
|
PulseWidthLow => tpw_Din7_negedge,
|
|
PeriodData => periodcheckinfo_Din7,
|
|
Violation => tviol_Din7_Din7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din7_ipd'last_event,
|
|
PathDelay => tpd_Din7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_6_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_6_B";
|
|
|
|
tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din6 : VitalDelayType := 0 ns;
|
|
tpw_Din6_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din6_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din6: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
|
|
|
|
end Din_6_B;
|
|
|
|
architecture Structure of Din_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din6_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_6: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din6_Din6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din6_ipd,
|
|
TestSignalName => "Din6",
|
|
Period => tperiod_Din6,
|
|
PulseWidthHigh => tpw_Din6_posedge,
|
|
PulseWidthLow => tpw_Din6_negedge,
|
|
PeriodData => periodcheckinfo_Din6,
|
|
Violation => tviol_Din6_Din6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din6_ipd'last_event,
|
|
PathDelay => tpd_Din6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_5_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_5_B";
|
|
|
|
tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din5 : VitalDelayType := 0 ns;
|
|
tpw_Din5_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din5_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din5: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
|
|
|
|
end Din_5_B;
|
|
|
|
architecture Structure of Din_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din5_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_5: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din5_Din5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din5_ipd,
|
|
TestSignalName => "Din5",
|
|
Period => tperiod_Din5,
|
|
PulseWidthHigh => tpw_Din5_posedge,
|
|
PulseWidthLow => tpw_Din5_negedge,
|
|
PeriodData => periodcheckinfo_Din5,
|
|
Violation => tviol_Din5_Din5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din5_ipd'last_event,
|
|
PathDelay => tpd_Din5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_4_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_4_B";
|
|
|
|
tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din4 : VitalDelayType := 0 ns;
|
|
tpw_Din4_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din4_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din4: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
|
|
|
|
end Din_4_B;
|
|
|
|
architecture Structure of Din_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din4_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_4: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din4_Din4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din4_ipd,
|
|
TestSignalName => "Din4",
|
|
Period => tperiod_Din4,
|
|
PulseWidthHigh => tpw_Din4_posedge,
|
|
PulseWidthLow => tpw_Din4_negedge,
|
|
PeriodData => periodcheckinfo_Din4,
|
|
Violation => tviol_Din4_Din4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din4_ipd'last_event,
|
|
PathDelay => tpd_Din4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_3_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_3_B";
|
|
|
|
tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din3 : VitalDelayType := 0 ns;
|
|
tpw_Din3_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din3_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din3: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
|
|
|
|
end Din_3_B;
|
|
|
|
architecture Structure of Din_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din3_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_3: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din3_Din3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din3_ipd,
|
|
TestSignalName => "Din3",
|
|
Period => tperiod_Din3,
|
|
PulseWidthHigh => tpw_Din3_posedge,
|
|
PulseWidthLow => tpw_Din3_negedge,
|
|
PeriodData => periodcheckinfo_Din3,
|
|
Violation => tviol_Din3_Din3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din3_ipd'last_event,
|
|
PathDelay => tpd_Din3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_2_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_2_B";
|
|
|
|
tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din2 : VitalDelayType := 0 ns;
|
|
tpw_Din2_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din2_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din2: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
|
|
|
|
end Din_2_B;
|
|
|
|
architecture Structure of Din_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din2_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_2: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din2_Din2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din2_ipd,
|
|
TestSignalName => "Din2",
|
|
Period => tperiod_Din2,
|
|
PulseWidthHigh => tpw_Din2_posedge,
|
|
PulseWidthLow => tpw_Din2_negedge,
|
|
PeriodData => periodcheckinfo_Din2,
|
|
Violation => tviol_Din2_Din2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din2_ipd'last_event,
|
|
PathDelay => tpd_Din2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_1_B";
|
|
|
|
tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din1 : VitalDelayType := 0 ns;
|
|
tpw_Din1_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
|
|
|
|
end Din_1_B;
|
|
|
|
architecture Structure of Din_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din1_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_1: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din1_Din1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din1_ipd,
|
|
TestSignalName => "Din1",
|
|
Period => tperiod_Din1,
|
|
PulseWidthHigh => tpw_Din1_posedge,
|
|
PulseWidthLow => tpw_Din1_negedge,
|
|
PeriodData => periodcheckinfo_Din1,
|
|
Violation => tviol_Din1_Din1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din1_ipd'last_event,
|
|
PathDelay => tpd_Din1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity Din_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_0_B";
|
|
|
|
tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din0 : VitalDelayType := 0 ns;
|
|
tpw_Din0_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
|
|
|
|
end Din_0_B;
|
|
|
|
architecture Structure of Din_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din0_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_0: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>Din0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din0_Din0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din0_ipd,
|
|
TestSignalName => "Din0",
|
|
Period => tperiod_Din0,
|
|
PulseWidthHigh => tpw_Din0_posedge,
|
|
PulseWidthLow => tpw_Din0_negedge,
|
|
PeriodData => periodcheckinfo_Din0,
|
|
Violation => tviol_Din0_Din0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din0_ipd'last_event,
|
|
PathDelay => tpd_Din0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity CROW_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity CROW_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "CROW_1_B";
|
|
|
|
tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CROW1 : VitalDelayType := 0 ns;
|
|
tpw_CROW1_posedge : VitalDelayType := 0 ns;
|
|
tpw_CROW1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; CROW1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
|
|
|
|
end CROW_1_B;
|
|
|
|
architecture Structure of CROW_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal CROW1_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
CROW_pad_1: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>CROW1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_CROW1_CROW1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CROW1_ipd,
|
|
TestSignalName => "CROW1",
|
|
Period => tperiod_CROW1,
|
|
PulseWidthHigh => tpw_CROW1_posedge,
|
|
PulseWidthLow => tpw_CROW1_negedge,
|
|
PeriodData => periodcheckinfo_CROW1,
|
|
Violation => tviol_CROW1_CROW1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => CROW1_ipd'last_event,
|
|
PathDelay => tpd_CROW1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity CROW_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity CROW_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "CROW_0_B";
|
|
|
|
tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CROW0 : VitalDelayType := 0 ns;
|
|
tpw_CROW0_posedge : VitalDelayType := 0 ns;
|
|
tpw_CROW0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; CROW0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
|
|
|
|
end CROW_0_B;
|
|
|
|
architecture Structure of CROW_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal CROW0_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
CROW_pad_0: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>CROW0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_CROW0_CROW0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CROW0_ipd,
|
|
TestSignalName => "CROW0",
|
|
Period => tperiod_CROW0,
|
|
PulseWidthHigh => tpw_CROW0_posedge,
|
|
PulseWidthLow => tpw_CROW0_negedge,
|
|
PeriodData => periodcheckinfo_CROW0,
|
|
Violation => tviol_CROW0_CROW0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => CROW0_ipd'last_event,
|
|
PathDelay => tpd_CROW0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_9_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_9_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_9_B";
|
|
|
|
tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin9 : VitalDelayType := 0 ns;
|
|
tpw_MAin9_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin9_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin9: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
|
|
|
|
end MAin_9_B;
|
|
|
|
architecture Structure of MAin_9_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin9_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_9: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin9_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin9_MAin9 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin9_ipd,
|
|
TestSignalName => "MAin9",
|
|
Period => tperiod_MAin9,
|
|
PulseWidthHigh => tpw_MAin9_posedge,
|
|
PulseWidthLow => tpw_MAin9_negedge,
|
|
PeriodData => periodcheckinfo_MAin9,
|
|
Violation => tviol_MAin9_MAin9,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin9_ipd'last_event,
|
|
PathDelay => tpd_MAin9_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_8_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_8_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_8_B";
|
|
|
|
tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin8 : VitalDelayType := 0 ns;
|
|
tpw_MAin8_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin8_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin8: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
|
|
|
|
end MAin_8_B;
|
|
|
|
architecture Structure of MAin_8_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin8_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_8: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin8_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin8_MAin8 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin8_ipd,
|
|
TestSignalName => "MAin8",
|
|
Period => tperiod_MAin8,
|
|
PulseWidthHigh => tpw_MAin8_posedge,
|
|
PulseWidthLow => tpw_MAin8_negedge,
|
|
PeriodData => periodcheckinfo_MAin8,
|
|
Violation => tviol_MAin8_MAin8,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin8_ipd'last_event,
|
|
PathDelay => tpd_MAin8_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_7_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_7_B";
|
|
|
|
tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin7 : VitalDelayType := 0 ns;
|
|
tpw_MAin7_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin7_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin7: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
|
|
|
|
end MAin_7_B;
|
|
|
|
architecture Structure of MAin_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin7_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_7: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin7_MAin7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin7_ipd,
|
|
TestSignalName => "MAin7",
|
|
Period => tperiod_MAin7,
|
|
PulseWidthHigh => tpw_MAin7_posedge,
|
|
PulseWidthLow => tpw_MAin7_negedge,
|
|
PeriodData => periodcheckinfo_MAin7,
|
|
Violation => tviol_MAin7_MAin7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin7_ipd'last_event,
|
|
PathDelay => tpd_MAin7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_6_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_6_B";
|
|
|
|
tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin6 : VitalDelayType := 0 ns;
|
|
tpw_MAin6_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin6_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin6: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
|
|
|
|
end MAin_6_B;
|
|
|
|
architecture Structure of MAin_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin6_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_6: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin6_MAin6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin6_ipd,
|
|
TestSignalName => "MAin6",
|
|
Period => tperiod_MAin6,
|
|
PulseWidthHigh => tpw_MAin6_posedge,
|
|
PulseWidthLow => tpw_MAin6_negedge,
|
|
PeriodData => periodcheckinfo_MAin6,
|
|
Violation => tviol_MAin6_MAin6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin6_ipd'last_event,
|
|
PathDelay => tpd_MAin6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_5_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_5_B";
|
|
|
|
tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin5 : VitalDelayType := 0 ns;
|
|
tpw_MAin5_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin5_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin5: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
|
|
|
|
end MAin_5_B;
|
|
|
|
architecture Structure of MAin_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin5_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_5: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin5_MAin5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin5_ipd,
|
|
TestSignalName => "MAin5",
|
|
Period => tperiod_MAin5,
|
|
PulseWidthHigh => tpw_MAin5_posedge,
|
|
PulseWidthLow => tpw_MAin5_negedge,
|
|
PeriodData => periodcheckinfo_MAin5,
|
|
Violation => tviol_MAin5_MAin5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin5_ipd'last_event,
|
|
PathDelay => tpd_MAin5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_4_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_4_B";
|
|
|
|
tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin4 : VitalDelayType := 0 ns;
|
|
tpw_MAin4_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin4_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin4: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
|
|
|
|
end MAin_4_B;
|
|
|
|
architecture Structure of MAin_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin4_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_4: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin4_MAin4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin4_ipd,
|
|
TestSignalName => "MAin4",
|
|
Period => tperiod_MAin4,
|
|
PulseWidthHigh => tpw_MAin4_posedge,
|
|
PulseWidthLow => tpw_MAin4_negedge,
|
|
PeriodData => periodcheckinfo_MAin4,
|
|
Violation => tviol_MAin4_MAin4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin4_ipd'last_event,
|
|
PathDelay => tpd_MAin4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_3_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_3_B";
|
|
|
|
tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin3 : VitalDelayType := 0 ns;
|
|
tpw_MAin3_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin3_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin3: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
|
|
|
|
end MAin_3_B;
|
|
|
|
architecture Structure of MAin_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin3_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_3: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin3_MAin3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin3_ipd,
|
|
TestSignalName => "MAin3",
|
|
Period => tperiod_MAin3,
|
|
PulseWidthHigh => tpw_MAin3_posedge,
|
|
PulseWidthLow => tpw_MAin3_negedge,
|
|
PeriodData => periodcheckinfo_MAin3,
|
|
Violation => tviol_MAin3_MAin3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin3_ipd'last_event,
|
|
PathDelay => tpd_MAin3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_2_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_2_B";
|
|
|
|
tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin2 : VitalDelayType := 0 ns;
|
|
tpw_MAin2_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin2_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin2: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
|
|
|
|
end MAin_2_B;
|
|
|
|
architecture Structure of MAin_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin2_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_2: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin2_MAin2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin2_ipd,
|
|
TestSignalName => "MAin2",
|
|
Period => tperiod_MAin2,
|
|
PulseWidthHigh => tpw_MAin2_posedge,
|
|
PulseWidthLow => tpw_MAin2_negedge,
|
|
PeriodData => periodcheckinfo_MAin2,
|
|
Violation => tviol_MAin2_MAin2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin2_ipd'last_event,
|
|
PathDelay => tpd_MAin2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_1_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_1_B";
|
|
|
|
tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin1 : VitalDelayType := 0 ns;
|
|
tpw_MAin1_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
|
|
|
|
end MAin_1_B;
|
|
|
|
architecture Structure of MAin_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin1_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_1: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin1_MAin1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin1_ipd,
|
|
TestSignalName => "MAin1",
|
|
Period => tperiod_MAin1,
|
|
PulseWidthHigh => tpw_MAin1_posedge,
|
|
PulseWidthLow => tpw_MAin1_negedge,
|
|
PeriodData => periodcheckinfo_MAin1,
|
|
Violation => tviol_MAin1_MAin1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin1_ipd'last_event,
|
|
PathDelay => tpd_MAin1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_0_B
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity MAin_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_0_B";
|
|
|
|
tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin0 : VitalDelayType := 0 ns;
|
|
tpw_MAin0_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
|
|
|
|
end MAin_0_B;
|
|
|
|
architecture Structure of MAin_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin0_ipd : std_logic := 'X';
|
|
|
|
component mjiobuf0084
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_0: mjiobuf0084
|
|
port map (Z=>PADDI_out, PAD=>MAin0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin0_MAin0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin0_ipd,
|
|
TestSignalName => "MAin0",
|
|
Period => tperiod_MAin0,
|
|
PulseWidthHigh => tpw_MAin0_posedge,
|
|
PulseWidthLow => tpw_MAin0_negedge,
|
|
PeriodData => periodcheckinfo_MAin0,
|
|
Violation => tviol_MAin0_MAin0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin0_ipd'last_event,
|
|
PathDelay => tpd_MAin0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RAM2GS
|
|
library IEEE, vital2000, MACHXO;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO.COMPONENTS.ALL;
|
|
|
|
entity RAM2GS is
|
|
port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0);
|
|
CROW: in Std_logic_vector (1 downto 0);
|
|
Din: in Std_logic_vector (7 downto 0);
|
|
Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic;
|
|
nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic;
|
|
RBA: out Std_logic_vector (1 downto 0);
|
|
RA: out Std_logic_vector (11 downto 0);
|
|
RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic;
|
|
RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic;
|
|
nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic;
|
|
RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic;
|
|
UFMSDI: out Std_logic; UFMSDO: in Std_logic);
|
|
|
|
|
|
|
|
end RAM2GS;
|
|
|
|
architecture Structure of RAM2GS is
|
|
signal FS_1: Std_logic;
|
|
signal FS_0: Std_logic;
|
|
signal RCLK_c: Std_logic;
|
|
signal FS_cry_1: Std_logic;
|
|
signal FS_17: Std_logic;
|
|
signal FS_16: Std_logic;
|
|
signal FS_cry_15: Std_logic;
|
|
signal FS_15: Std_logic;
|
|
signal FS_14: Std_logic;
|
|
signal FS_cry_13: Std_logic;
|
|
signal FS_13: Std_logic;
|
|
signal FS_12: Std_logic;
|
|
signal FS_cry_11: Std_logic;
|
|
signal FS_11: Std_logic;
|
|
signal FS_10: Std_logic;
|
|
signal FS_cry_9: Std_logic;
|
|
signal FS_9: Std_logic;
|
|
signal FS_8: Std_logic;
|
|
signal FS_cry_7: Std_logic;
|
|
signal FS_7: Std_logic;
|
|
signal FS_6: Std_logic;
|
|
signal FS_cry_5: Std_logic;
|
|
signal FS_5: Std_logic;
|
|
signal FS_4: Std_logic;
|
|
signal FS_cry_3: Std_logic;
|
|
signal FS_3: Std_logic;
|
|
signal FS_2: Std_logic;
|
|
signal N_147: Std_logic;
|
|
signal MAin_c_0: Std_logic;
|
|
signal CmdEnable17_0_a2_4: Std_logic;
|
|
signal CmdEnable17_0_a2_3: Std_logic;
|
|
signal CmdEnable16: Std_logic;
|
|
signal CmdEnable17: Std_logic;
|
|
signal C1WR_0_a2: Std_logic;
|
|
signal ADSubmitted: Std_logic;
|
|
signal ADSubmitted_r: Std_logic;
|
|
signal PHI2_c: Std_logic;
|
|
signal CmdEnable16_0_a2_5: Std_logic;
|
|
signal CmdEnable16_0_a2_4: Std_logic;
|
|
signal MAin_c_1: Std_logic;
|
|
signal C1Submitted: Std_logic;
|
|
signal C1Submitted_RNO: Std_logic;
|
|
signal S_1: Std_logic;
|
|
signal RASr2: Std_logic;
|
|
signal IS_3: Std_logic;
|
|
signal CO0: Std_logic;
|
|
signal N_177_i: Std_logic;
|
|
signal Ready_0_sqmuxa_0_a3_2: Std_logic;
|
|
signal CmdEnable: Std_logic;
|
|
signal un1_CMDWR: Std_logic;
|
|
signal CmdEnable_s: Std_logic;
|
|
signal N_128: Std_logic;
|
|
signal Din_c_5: Std_logic;
|
|
signal Din_c_3: Std_logic;
|
|
signal N_152: Std_logic;
|
|
signal N_133: Std_logic;
|
|
signal N_132: Std_logic;
|
|
signal LEDEN: Std_logic;
|
|
signal N_21_i: Std_logic;
|
|
signal XOR8MEG18: Std_logic;
|
|
signal CmdLEDEN: Std_logic;
|
|
signal PHI2r3: Std_logic;
|
|
signal PHI2r2: Std_logic;
|
|
signal InitReady: Std_logic;
|
|
signal CmdSubmitted: Std_logic;
|
|
signal CmdSubmitted_1_sqmuxa: Std_logic;
|
|
signal N_460_0: Std_logic;
|
|
signal N_136: Std_logic;
|
|
signal N_43: Std_logic;
|
|
signal Cmdn8MEGEN: Std_logic;
|
|
signal CmdEnable16_4: Std_logic;
|
|
signal n8MEGEN: Std_logic;
|
|
signal Cmdn8MEGEN_4_u_i_0: Std_logic;
|
|
signal N_19_i: Std_logic;
|
|
signal nRRAS_5_u_i_0: Std_logic;
|
|
signal N_160: Std_logic;
|
|
signal N_155: Std_logic;
|
|
signal IS_0: Std_logic;
|
|
signal Ready: Std_logic;
|
|
signal N_64_i_i: Std_logic;
|
|
signal N_24: Std_logic;
|
|
signal IS_2: Std_logic;
|
|
signal IS_1: Std_logic;
|
|
signal N_60_i_i: Std_logic;
|
|
signal N_56_i: Std_logic;
|
|
signal N_159_i: Std_logic;
|
|
signal N_159: Std_logic;
|
|
signal N_61_i_i: Std_logic;
|
|
signal RA10s_i: Std_logic;
|
|
signal UFMSDI_ens2_i_a2_4_2: Std_logic;
|
|
signal N_126: Std_logic;
|
|
signal N_51: Std_logic;
|
|
signal InitReady3: Std_logic;
|
|
signal N_461_0: Std_logic;
|
|
signal UFMSDI_ens2_i_a0: Std_logic;
|
|
signal nCRAS_c: Std_logic;
|
|
signal CBR: Std_logic;
|
|
signal UFMSDO_c: Std_logic;
|
|
signal N_70: Std_logic;
|
|
signal N_33: Std_logic;
|
|
signal LED_c: Std_logic;
|
|
signal un1_Din_4: Std_logic;
|
|
signal XOR8MEG: Std_logic;
|
|
signal Din_c_6: Std_logic;
|
|
signal RA11_2: Std_logic;
|
|
signal Ready_fast: Std_logic;
|
|
signal RA_c_11: Std_logic;
|
|
signal N_171: Std_logic;
|
|
signal FWEr_fast: Std_logic;
|
|
signal CASr2: Std_logic;
|
|
signal RCKEEN_8_u_1: Std_logic;
|
|
signal RCKEEN_8_u_0_0: Std_logic;
|
|
signal RCKEEN_8: Std_logic;
|
|
signal PHI2r: Std_logic;
|
|
signal RCKEEN: Std_logic;
|
|
signal RASr3: Std_logic;
|
|
signal RASr: Std_logic;
|
|
signal RCKE_2: Std_logic;
|
|
signal RCKE_c: Std_logic;
|
|
signal m18_0_a3_3: Std_logic;
|
|
signal S_0_i_o2_1: Std_logic;
|
|
signal N_165: Std_logic;
|
|
signal N_462_0: Std_logic;
|
|
signal Ready_0_sqmuxa: Std_logic;
|
|
signal N_463_0: Std_logic;
|
|
signal nRRAS_0_sqmuxa: Std_logic;
|
|
signal N_129: Std_logic;
|
|
signal UFMCLK_r_i_a2_2_2: Std_logic;
|
|
signal CmdUFMCLK: Std_logic;
|
|
signal UFMCLK_r_i_m4_xx_mm_1: Std_logic;
|
|
signal UFMCLK_c: Std_logic;
|
|
signal nUFMCS15: Std_logic;
|
|
signal N_139_i: Std_logic;
|
|
signal UFMCLK_RNO: Std_logic;
|
|
signal UFMSDI_r_xx_mm_1: Std_logic;
|
|
signal UFMSDI_c: Std_logic;
|
|
signal UFMSDI_RNO: Std_logic;
|
|
signal nRowColSel: Std_logic;
|
|
signal RowA_4: Std_logic;
|
|
signal MAin_c_4: Std_logic;
|
|
signal Din_c_4: Std_logic;
|
|
signal nCCAS_c: Std_logic;
|
|
signal RA_c_4: Std_logic;
|
|
signal WRD_4: Std_logic;
|
|
signal WRD_5: Std_logic;
|
|
signal Bank_7: Std_logic;
|
|
signal Bank_6: Std_logic;
|
|
signal Bank_5: Std_logic;
|
|
signal Bank_2: Std_logic;
|
|
signal Din_c_7: Std_logic;
|
|
signal WRD_6: Std_logic;
|
|
signal C1WR_0_a2_0_11: Std_logic;
|
|
signal WRD_7: Std_logic;
|
|
signal Din_c_2: Std_logic;
|
|
signal Din_c_0: Std_logic;
|
|
signal XOR8MEG_3_u_0_a3_2: Std_logic;
|
|
signal Din_c_1: Std_logic;
|
|
signal XOR8MEG_3: Std_logic;
|
|
signal N_69: Std_logic;
|
|
signal N_31: Std_logic;
|
|
signal N_151: Std_logic;
|
|
signal g0_1: Std_logic;
|
|
signal nRCAS_0_sqmuxa_1: Std_logic;
|
|
signal N_41: Std_logic;
|
|
signal N_37_i: Std_logic;
|
|
signal nRCAS_c: Std_logic;
|
|
signal CASr3: Std_logic;
|
|
signal RCKEEN_8_u_0_a2_1_out: Std_logic;
|
|
signal N_28_i_1: Std_logic;
|
|
signal N_28_i: Std_logic;
|
|
signal nRCS_c: Std_logic;
|
|
signal N_24_i: Std_logic;
|
|
signal nRRAS_c: Std_logic;
|
|
signal CBR_fast: Std_logic;
|
|
signal m18_0_a2_1: Std_logic;
|
|
signal G_17_1: Std_logic;
|
|
signal FWEr: Std_logic;
|
|
signal N_39_i: Std_logic;
|
|
signal nRWE_c: Std_logic;
|
|
signal N_179: Std_logic;
|
|
signal nRowColSel_0_0: Std_logic;
|
|
signal nUFMCS_s_0_N_5_i_N_2L1: Std_logic;
|
|
signal nUFMCS_c: Std_logic;
|
|
signal nUFMCS_s_0_N_5_i: Std_logic;
|
|
signal CmdUFMCS: Std_logic;
|
|
signal N_95_5: Std_logic;
|
|
signal N_95_3: Std_logic;
|
|
signal RowA_0: Std_logic;
|
|
signal RowA_1: Std_logic;
|
|
signal MAin_c_5: Std_logic;
|
|
signal CmdUFMCLK_1_sqmuxa: Std_logic;
|
|
signal RowA_5: Std_logic;
|
|
signal un1_FS_14_i_a2_0_1: Std_logic;
|
|
signal N_137_8: Std_logic;
|
|
signal N_137_6: Std_logic;
|
|
signal un1_FS_13_i_a2_1: Std_logic;
|
|
signal C1WR_0_a2_0_10: Std_logic;
|
|
signal Bank_1: Std_logic;
|
|
signal Bank_0: Std_logic;
|
|
signal MAin_c_7: Std_logic;
|
|
signal MAin_c_6: Std_logic;
|
|
signal C1WR_0_a2_0_4: Std_logic;
|
|
signal C1WR_0_a2_0_3: Std_logic;
|
|
signal Bank_4: Std_logic;
|
|
signal Bank_3: Std_logic;
|
|
signal UFMSDI_ens2_i_o2_0_3: Std_logic;
|
|
signal MAin_c_3: Std_logic;
|
|
signal MAin_c_2: Std_logic;
|
|
signal RowA_2: Std_logic;
|
|
signal RowA_3: Std_logic;
|
|
signal CmdUFMSDI: Std_logic;
|
|
signal CASr: Std_logic;
|
|
signal CmdEnable16_1: Std_logic;
|
|
signal m6_0_a2_2: Std_logic;
|
|
signal WRD_0: Std_logic;
|
|
signal WRD_1: Std_logic;
|
|
signal g4_0_0_0: Std_logic;
|
|
signal MAin_c_9: Std_logic;
|
|
signal MAin_c_8: Std_logic;
|
|
signal RowA_8: Std_logic;
|
|
signal RowA_9: Std_logic;
|
|
signal nFWE_c: Std_logic;
|
|
signal CROW_c_1: Std_logic;
|
|
signal CROW_c_0: Std_logic;
|
|
signal RBA_c_0: Std_logic;
|
|
signal RBA_c_1: Std_logic;
|
|
signal WRD_2: Std_logic;
|
|
signal WRD_3: Std_logic;
|
|
signal RA_c_9: Std_logic;
|
|
signal RDQML_c: Std_logic;
|
|
signal RD_1_i: Std_logic;
|
|
signal RowA_6: Std_logic;
|
|
signal RowA_7: Std_logic;
|
|
signal RA_c_8: Std_logic;
|
|
signal RDQMH_c: Std_logic;
|
|
signal RA_c_0: Std_logic;
|
|
signal RA_c_1: Std_logic;
|
|
signal RA_c_7: Std_logic;
|
|
signal RA_c_2: Std_logic;
|
|
signal RA_c_6: Std_logic;
|
|
signal RA_c_3: Std_logic;
|
|
signal RA_c_5: Std_logic;
|
|
signal RA_c_10: Std_logic;
|
|
signal RD_in_0: Std_logic;
|
|
signal RD_in_7: Std_logic;
|
|
signal RD_in_6: Std_logic;
|
|
signal RD_in_5: Std_logic;
|
|
signal RD_in_4: Std_logic;
|
|
signal RD_in_3: Std_logic;
|
|
signal RD_in_2: Std_logic;
|
|
signal RD_in_1: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal GNDI_TSALL: Std_logic;
|
|
component VHI
|
|
port (Z: out Std_logic);
|
|
end component;
|
|
component VLO
|
|
port (Z: out Std_logic);
|
|
end component;
|
|
component PUR
|
|
port (PUR: in Std_logic);
|
|
end component;
|
|
component GSR
|
|
port (GSR: in Std_logic);
|
|
end component;
|
|
component TSALL
|
|
port (TSALL: in Std_logic);
|
|
end component;
|
|
component SLICE_0
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_1
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_2
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_3
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_4
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_5
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_6
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_7
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_8
|
|
port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic;
|
|
FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_9
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_14
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_19
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_20
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
OFX0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_21
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_22
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_26
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_29
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_30
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_31
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_32
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_33
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_39
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_41
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_42
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_43
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_44
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_50
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_51
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_52
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_55
|
|
port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_56
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_57
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_58
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_59
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_60
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_61
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_62
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_63
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_64
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component nRWE_RNO_1_SLICE_65
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M0: in Std_logic;
|
|
OFX0: out Std_logic);
|
|
end component;
|
|
component SLICE_66
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_67
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_68
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_69
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_70
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_71
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_72
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_73
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_74
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_75
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_76
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_77
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_78
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_79
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_80
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_81
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_82
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_83
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_84
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_85
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_86
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_87
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_88
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_89
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_90
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_91
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_92
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_93
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_94
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component RD_0_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD0: inout Std_logic);
|
|
end component;
|
|
component Dout_0_B
|
|
port (PADDO: in Std_logic; Dout0: out Std_logic);
|
|
end component;
|
|
component PHI2B
|
|
port (PADDI: out Std_logic; PHI2S: in Std_logic);
|
|
end component;
|
|
component UFMSDOB
|
|
port (PADDI: out Std_logic; UFMSDOS: in Std_logic);
|
|
end component;
|
|
component UFMSDIB
|
|
port (PADDO: in Std_logic; UFMSDIS: out Std_logic);
|
|
end component;
|
|
component UFMCLKB
|
|
port (PADDO: in Std_logic; UFMCLKS: out Std_logic);
|
|
end component;
|
|
component nUFMCSB
|
|
port (PADDO: in Std_logic; nUFMCSS: out Std_logic);
|
|
end component;
|
|
component RDQMLB
|
|
port (PADDO: in Std_logic; RDQMLS: out Std_logic);
|
|
end component;
|
|
component RDQMHB
|
|
port (PADDO: in Std_logic; RDQMHS: out Std_logic);
|
|
end component;
|
|
component nRCASB
|
|
port (PADDO: in Std_logic; nRCASS: out Std_logic);
|
|
end component;
|
|
component nRRASB
|
|
port (PADDO: in Std_logic; nRRASS: out Std_logic);
|
|
end component;
|
|
component nRWEB
|
|
port (PADDO: in Std_logic; nRWES: out Std_logic);
|
|
end component;
|
|
component RCKEB
|
|
port (PADDO: in Std_logic; RCKES: out Std_logic);
|
|
end component;
|
|
component RCLKB
|
|
port (PADDI: out Std_logic; RCLKS: in Std_logic);
|
|
end component;
|
|
component nRCSB
|
|
port (PADDO: in Std_logic; nRCSS: out Std_logic);
|
|
end component;
|
|
component RD_7_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD7: inout Std_logic);
|
|
end component;
|
|
component RD_6_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD6: inout Std_logic);
|
|
end component;
|
|
component RD_5_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD5: inout Std_logic);
|
|
end component;
|
|
component RD_4_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD4: inout Std_logic);
|
|
end component;
|
|
component RD_3_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD3: inout Std_logic);
|
|
end component;
|
|
component RD_2_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD2: inout Std_logic);
|
|
end component;
|
|
component RD_1_B
|
|
port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic;
|
|
RD1: inout Std_logic);
|
|
end component;
|
|
component RA_11_B
|
|
port (PADDO: in Std_logic; RA11: out Std_logic);
|
|
end component;
|
|
component RA_10_B
|
|
port (PADDO: in Std_logic; RA10: out Std_logic);
|
|
end component;
|
|
component RA_9_B
|
|
port (PADDO: in Std_logic; RA9: out Std_logic);
|
|
end component;
|
|
component RA_8_B
|
|
port (PADDO: in Std_logic; RA8: out Std_logic);
|
|
end component;
|
|
component RA_7_B
|
|
port (PADDO: in Std_logic; RA7: out Std_logic);
|
|
end component;
|
|
component RA_6_B
|
|
port (PADDO: in Std_logic; RA6: out Std_logic);
|
|
end component;
|
|
component RA_5_B
|
|
port (PADDO: in Std_logic; RA5: out Std_logic);
|
|
end component;
|
|
component RA_4_B
|
|
port (PADDO: in Std_logic; RA4: out Std_logic);
|
|
end component;
|
|
component RA_3_B
|
|
port (PADDO: in Std_logic; RA3: out Std_logic);
|
|
end component;
|
|
component RA_2_B
|
|
port (PADDO: in Std_logic; RA2: out Std_logic);
|
|
end component;
|
|
component RA_1_B
|
|
port (PADDO: in Std_logic; RA1: out Std_logic);
|
|
end component;
|
|
component RA_0_B
|
|
port (PADDO: in Std_logic; RA0: out Std_logic);
|
|
end component;
|
|
component RBA_1_B
|
|
port (PADDO: in Std_logic; RBA1: out Std_logic);
|
|
end component;
|
|
component RBA_0_B
|
|
port (PADDO: in Std_logic; RBA0: out Std_logic);
|
|
end component;
|
|
component LEDB
|
|
port (PADDO: in Std_logic; LEDS: out Std_logic);
|
|
end component;
|
|
component nFWEB
|
|
port (PADDI: out Std_logic; nFWES: in Std_logic);
|
|
end component;
|
|
component nCRASB
|
|
port (PADDI: out Std_logic; nCRASS: in Std_logic);
|
|
end component;
|
|
component nCCASB
|
|
port (PADDI: out Std_logic; nCCASS: in Std_logic);
|
|
end component;
|
|
component Dout_7_B
|
|
port (PADDO: in Std_logic; Dout7: out Std_logic);
|
|
end component;
|
|
component Dout_6_B
|
|
port (PADDO: in Std_logic; Dout6: out Std_logic);
|
|
end component;
|
|
component Dout_5_B
|
|
port (PADDO: in Std_logic; Dout5: out Std_logic);
|
|
end component;
|
|
component Dout_4_B
|
|
port (PADDO: in Std_logic; Dout4: out Std_logic);
|
|
end component;
|
|
component Dout_3_B
|
|
port (PADDO: in Std_logic; Dout3: out Std_logic);
|
|
end component;
|
|
component Dout_2_B
|
|
port (PADDO: in Std_logic; Dout2: out Std_logic);
|
|
end component;
|
|
component Dout_1_B
|
|
port (PADDO: in Std_logic; Dout1: out Std_logic);
|
|
end component;
|
|
component Din_7_B
|
|
port (PADDI: out Std_logic; Din7: in Std_logic);
|
|
end component;
|
|
component Din_6_B
|
|
port (PADDI: out Std_logic; Din6: in Std_logic);
|
|
end component;
|
|
component Din_5_B
|
|
port (PADDI: out Std_logic; Din5: in Std_logic);
|
|
end component;
|
|
component Din_4_B
|
|
port (PADDI: out Std_logic; Din4: in Std_logic);
|
|
end component;
|
|
component Din_3_B
|
|
port (PADDI: out Std_logic; Din3: in Std_logic);
|
|
end component;
|
|
component Din_2_B
|
|
port (PADDI: out Std_logic; Din2: in Std_logic);
|
|
end component;
|
|
component Din_1_B
|
|
port (PADDI: out Std_logic; Din1: in Std_logic);
|
|
end component;
|
|
component Din_0_B
|
|
port (PADDI: out Std_logic; Din0: in Std_logic);
|
|
end component;
|
|
component CROW_1_B
|
|
port (PADDI: out Std_logic; CROW1: in Std_logic);
|
|
end component;
|
|
component CROW_0_B
|
|
port (PADDI: out Std_logic; CROW0: in Std_logic);
|
|
end component;
|
|
component MAin_9_B
|
|
port (PADDI: out Std_logic; MAin9: in Std_logic);
|
|
end component;
|
|
component MAin_8_B
|
|
port (PADDI: out Std_logic; MAin8: in Std_logic);
|
|
end component;
|
|
component MAin_7_B
|
|
port (PADDI: out Std_logic; MAin7: in Std_logic);
|
|
end component;
|
|
component MAin_6_B
|
|
port (PADDI: out Std_logic; MAin6: in Std_logic);
|
|
end component;
|
|
component MAin_5_B
|
|
port (PADDI: out Std_logic; MAin5: in Std_logic);
|
|
end component;
|
|
component MAin_4_B
|
|
port (PADDI: out Std_logic; MAin4: in Std_logic);
|
|
end component;
|
|
component MAin_3_B
|
|
port (PADDI: out Std_logic; MAin3: in Std_logic);
|
|
end component;
|
|
component MAin_2_B
|
|
port (PADDI: out Std_logic; MAin2: in Std_logic);
|
|
end component;
|
|
component MAin_1_B
|
|
port (PADDI: out Std_logic; MAin1: in Std_logic);
|
|
end component;
|
|
component MAin_0_B
|
|
port (PADDI: out Std_logic; MAin0: in Std_logic);
|
|
end component;
|
|
begin
|
|
SLICE_0I: SLICE_0
|
|
port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1,
|
|
FCO=>FS_cry_1);
|
|
SLICE_1I: SLICE_1
|
|
port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>FS_cry_15, Q0=>FS_16,
|
|
Q1=>FS_17);
|
|
SLICE_2I: SLICE_2
|
|
port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>FS_cry_13, Q0=>FS_14,
|
|
Q1=>FS_15, FCO=>FS_cry_15);
|
|
SLICE_3I: SLICE_3
|
|
port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>FS_cry_11, Q0=>FS_12,
|
|
Q1=>FS_13, FCO=>FS_cry_13);
|
|
SLICE_4I: SLICE_4
|
|
port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>FS_cry_9, Q0=>FS_10,
|
|
Q1=>FS_11, FCO=>FS_cry_11);
|
|
SLICE_5I: SLICE_5
|
|
port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>FS_cry_7, Q0=>FS_8,
|
|
Q1=>FS_9, FCO=>FS_cry_9);
|
|
SLICE_6I: SLICE_6
|
|
port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>FS_cry_5, Q0=>FS_6,
|
|
Q1=>FS_7, FCO=>FS_cry_7);
|
|
SLICE_7I: SLICE_7
|
|
port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>FS_cry_3, Q0=>FS_4,
|
|
Q1=>FS_5, FCO=>FS_cry_5);
|
|
SLICE_8I: SLICE_8
|
|
port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>FS_cry_1, Q0=>FS_2,
|
|
Q1=>FS_3, FCO=>FS_cry_3);
|
|
SLICE_9I: SLICE_9
|
|
port map (D1=>N_147, C1=>MAin_c_0, B1=>CmdEnable17_0_a2_4,
|
|
A1=>CmdEnable17_0_a2_3, D0=>CmdEnable16, C0=>CmdEnable17,
|
|
B0=>C1WR_0_a2, A0=>ADSubmitted, DI0=>ADSubmitted_r,
|
|
CLK=>PHI2_c, F0=>ADSubmitted_r, Q0=>ADSubmitted,
|
|
F1=>CmdEnable17);
|
|
SLICE_14I: SLICE_14
|
|
port map (C1=>N_147, B1=>CmdEnable16_0_a2_5, A1=>CmdEnable16_0_a2_4,
|
|
D0=>MAin_c_1, C0=>N_147, B0=>C1Submitted, A0=>CmdEnable16,
|
|
DI0=>C1Submitted_RNO, CLK=>PHI2_c, F0=>C1Submitted_RNO,
|
|
Q0=>C1Submitted, F1=>CmdEnable16);
|
|
SLICE_19I: SLICE_19
|
|
port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0,
|
|
DI0=>N_177_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_177_i, Q0=>CO0,
|
|
F1=>Ready_0_sqmuxa_0_a3_2);
|
|
SLICE_20I: SLICE_20
|
|
port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR,
|
|
B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s,
|
|
M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
|
|
SLICE_21I: SLICE_21
|
|
port map (C1=>N_128, B1=>Din_c_5, A1=>Din_c_3, D0=>N_152, C0=>N_133,
|
|
B0=>N_132, A0=>LEDEN, DI0=>N_21_i, CE=>XOR8MEG18, CLK=>PHI2_c,
|
|
F0=>N_21_i, Q0=>CmdLEDEN, F1=>N_152);
|
|
SLICE_22I: SLICE_22
|
|
port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted,
|
|
B0=>CmdSubmitted, A0=>CmdSubmitted_1_sqmuxa, DI0=>N_460_0,
|
|
CLK=>PHI2_c, F0=>N_460_0, Q0=>CmdSubmitted, F1=>N_136);
|
|
SLICE_26I: SLICE_26
|
|
port map (D1=>N_128, C1=>N_43, B1=>Cmdn8MEGEN, A1=>CmdEnable16_4,
|
|
C0=>n8MEGEN, B0=>N_152, A0=>Cmdn8MEGEN_4_u_i_0, DI0=>N_19_i,
|
|
CE=>XOR8MEG18, CLK=>PHI2_c, F0=>N_19_i, Q0=>Cmdn8MEGEN,
|
|
F1=>Cmdn8MEGEN_4_u_i_0);
|
|
SLICE_29I: SLICE_29
|
|
port map (D1=>nRRAS_5_u_i_0, C1=>N_160, B1=>N_155, A1=>IS_0, C0=>N_155,
|
|
B0=>Ready, A0=>IS_0, DI0=>N_64_i_i, CLK=>RCLK_c, F0=>N_64_i_i,
|
|
Q0=>IS_0, F1=>N_24);
|
|
SLICE_30I: SLICE_30
|
|
port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0,
|
|
DI1=>N_60_i_i, DI0=>N_56_i, CE=>N_159_i, CLK=>RCLK_c,
|
|
F0=>N_56_i, Q0=>IS_1, F1=>N_60_i_i, Q1=>IS_2);
|
|
SLICE_31I: SLICE_31
|
|
port map (D1=>N_159, C1=>IS_3, B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1,
|
|
B0=>IS_2, A0=>IS_3, DI0=>N_61_i_i, CE=>N_159_i, CLK=>RCLK_c,
|
|
F0=>N_61_i_i, Q0=>IS_3, F1=>RA10s_i);
|
|
SLICE_32I: SLICE_32
|
|
port map (D1=>UFMSDI_ens2_i_a2_4_2, C1=>N_126, B1=>N_51, A1=>InitReady,
|
|
B0=>InitReady, A0=>InitReady3, DI0=>N_461_0, CLK=>RCLK_c,
|
|
F0=>N_461_0, Q0=>InitReady, F1=>UFMSDI_ens2_i_a0);
|
|
SLICE_33I: SLICE_33
|
|
port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, C0=>UFMSDO_c, B0=>InitReady,
|
|
A0=>CmdLEDEN, DI0=>N_70, CE=>N_33, CLK=>RCLK_c, F0=>N_70,
|
|
Q0=>LEDEN, F1=>LED_c);
|
|
SLICE_39I: SLICE_39
|
|
port map (B1=>un1_Din_4, A1=>XOR8MEG, C0=>n8MEGEN, B0=>XOR8MEG,
|
|
A0=>Din_c_6, DI0=>RA11_2, LSR=>Ready_fast, CLK=>PHI2_c,
|
|
F0=>RA11_2, Q0=>RA_c_11, F1=>N_171);
|
|
SLICE_41I: SLICE_41
|
|
port map (D1=>S_1, C1=>FWEr_fast, B1=>CO0, A1=>CASr2, D0=>Ready,
|
|
C0=>RCKEEN_8_u_1, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8,
|
|
M1=>PHI2r, CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN,
|
|
F1=>RCKEEN_8_u_1, Q1=>PHI2r2);
|
|
SLICE_42I: SLICE_42
|
|
port map (D1=>RASr2, C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>RCKEEN, C0=>RASr3,
|
|
B0=>RASr2, A0=>RASr, DI0=>RCKE_2, M1=>PHI2_c, CLK=>RCLK_c,
|
|
F0=>RCKE_2, Q0=>RCKE_c, F1=>m18_0_a3_3, Q1=>PHI2r);
|
|
SLICE_43I: SLICE_43
|
|
port map (D1=>S_0_i_o2_1, C1=>InitReady, B1=>RASr2, A1=>Ready,
|
|
D0=>InitReady, C0=>N_165, B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready,
|
|
DI0=>N_462_0, M1=>PHI2r2, CLK=>RCLK_c, F0=>N_462_0, Q0=>Ready,
|
|
F1=>RCKEEN_8_u_0_0, Q1=>PHI2r3);
|
|
SLICE_44I: SLICE_44
|
|
port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_165, A1=>InitReady,
|
|
B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_463_0, M1=>nCRAS_c,
|
|
CLK=>RCLK_c, F0=>N_463_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa,
|
|
Q1=>RASr);
|
|
SLICE_50I: SLICE_50
|
|
port map (C1=>CO0, B1=>S_1, A1=>Ready, B0=>S_1, A0=>CO0, DI0=>S_0_i_o2_1,
|
|
LSR=>RASr2, CLK=>RCLK_c, F0=>S_0_i_o2_1, Q0=>S_1,
|
|
F1=>nRRAS_0_sqmuxa);
|
|
SLICE_51I: SLICE_51
|
|
port map (D1=>N_129, C1=>UFMCLK_r_i_a2_2_2, B1=>CmdUFMCLK, A1=>InitReady,
|
|
D0=>UFMCLK_r_i_m4_xx_mm_1, C0=>UFMCLK_c, B0=>nUFMCS15,
|
|
A0=>N_139_i, DI0=>UFMCLK_RNO, M1=>RASr, CLK=>RCLK_c,
|
|
F0=>UFMCLK_RNO, Q0=>UFMCLK_c, F1=>UFMCLK_r_i_m4_xx_mm_1,
|
|
Q1=>RASr2);
|
|
SLICE_52I: SLICE_52
|
|
port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdSubmitted,
|
|
D0=>UFMSDI_r_xx_mm_1, C0=>UFMSDI_c, B0=>nUFMCS15, A0=>N_139_i,
|
|
DI0=>UFMSDI_RNO, M1=>RASr2, CLK=>RCLK_c, F0=>UFMSDI_RNO,
|
|
Q0=>UFMSDI_c, F1=>N_139_i, Q1=>RASr3);
|
|
SLICE_55I: SLICE_55
|
|
port map (C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4, M1=>Din_c_5,
|
|
M0=>Din_c_4, CLK=>nCCAS_c, F0=>RA_c_4, Q0=>WRD_4, Q1=>WRD_5);
|
|
SLICE_56I: SLICE_56
|
|
port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, C0=>FS_9,
|
|
B0=>FS_7, A0=>FS_5, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c,
|
|
F0=>N_126, Q0=>WRD_6, F1=>C1WR_0_a2_0_11, Q1=>WRD_7);
|
|
SLICE_57I: SLICE_57
|
|
port map (D1=>un1_Din_4, C1=>Din_c_3, B1=>Din_c_2, A1=>Din_c_0,
|
|
D0=>XOR8MEG_3_u_0_a3_2, C0=>N_171, B0=>LEDEN, A0=>Din_c_1,
|
|
DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3,
|
|
Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_a3_2);
|
|
SLICE_58I: SLICE_58
|
|
port map (C1=>N_51, B1=>InitReady, A1=>FS_8, C0=>UFMSDO_c, B0=>InitReady,
|
|
A0=>Cmdn8MEGEN, DI0=>N_69, CE=>N_31, CLK=>RCLK_c, F0=>N_69,
|
|
Q0=>n8MEGEN, F1=>N_151);
|
|
SLICE_59I: SLICE_59
|
|
port map (D1=>S_1, C1=>Ready, B1=>N_160, A1=>N_155, D0=>g0_1, C0=>S_1,
|
|
B0=>nRCAS_0_sqmuxa_1, A0=>N_41, DI0=>N_37_i, CLK=>RCLK_c,
|
|
F0=>N_37_i, Q0=>nRCAS_c, F1=>N_41);
|
|
SLICE_60I: SLICE_60
|
|
port map (D1=>CASr2, C1=>CASr3, B1=>CO0, A1=>FWEr_fast,
|
|
D0=>RCKEEN_8_u_0_a2_1_out, C0=>N_28_i_1, B0=>N_24, A0=>CBR,
|
|
DI0=>N_28_i, CLK=>RCLK_c, F0=>N_28_i, Q0=>nRCS_c, F1=>N_28_i_1);
|
|
SLICE_61I: SLICE_61
|
|
port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>S_0_i_o2_1, D0=>IS_0,
|
|
C0=>N_155, B0=>N_160, A0=>nRRAS_5_u_i_0, DI0=>N_24_i,
|
|
CLK=>RCLK_c, F0=>N_24_i, Q0=>nRRAS_c, F1=>nRRAS_5_u_i_0);
|
|
SLICE_62I: SLICE_62
|
|
port map (D1=>Ready, C1=>RASr2, B1=>S_0_i_o2_1, A1=>CBR_fast,
|
|
D0=>m18_0_a2_1, C0=>nRCAS_0_sqmuxa_1, B0=>G_17_1, A0=>FWEr,
|
|
DI0=>N_39_i, CLK=>RCLK_c, F0=>N_39_i, Q0=>nRWE_c,
|
|
F1=>nRCAS_0_sqmuxa_1);
|
|
SLICE_63I: SLICE_63
|
|
port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready,
|
|
B0=>N_179, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa,
|
|
CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_179);
|
|
SLICE_64I: SLICE_64
|
|
port map (D1=>N_51, C1=>InitReady, B1=>FS_11, A1=>FS_10,
|
|
D0=>nUFMCS_s_0_N_5_i_N_2L1, C0=>nUFMCS_c, B0=>nUFMCS15,
|
|
A0=>N_139_i, DI0=>nUFMCS_s_0_N_5_i, CLK=>RCLK_c,
|
|
F0=>nUFMCS_s_0_N_5_i, Q0=>nUFMCS_c, F1=>nUFMCS15);
|
|
nRWE_RNO_1_SLICE_65I: nRWE_RNO_1_SLICE_65
|
|
port map (D1=>RASr2, C1=>RCKE_c, B1=>CO0, A1=>S_1, D0=>InitReady,
|
|
C0=>m18_0_a3_3, B0=>CO0, A0=>S_1, M0=>Ready, OFX0=>m18_0_a2_1);
|
|
SLICE_66I: SLICE_66
|
|
port map (C1=>UFMCLK_r_i_a2_2_2, B1=>InitReady, A1=>CmdUFMCS, D0=>N_95_5,
|
|
C0=>N_95_3, B0=>InitReady, A0=>FS_16, M1=>MAin_c_1,
|
|
M0=>MAin_c_0, LSR=>Ready_fast, CLK=>nCRAS_c,
|
|
F0=>UFMCLK_r_i_a2_2_2, Q0=>RowA_0, F1=>nUFMCS_s_0_N_5_i_N_2L1,
|
|
Q1=>RowA_1);
|
|
SLICE_67I: SLICE_67
|
|
port map (D1=>Din_c_3, C1=>Din_c_5, B1=>N_128, A1=>XOR8MEG18, D0=>N_147,
|
|
C0=>MAin_c_1, B0=>MAin_c_0, A0=>CmdEnable, M1=>MAin_c_5,
|
|
M0=>MAin_c_4, LSR=>Ready_fast, CLK=>nCRAS_c, F0=>XOR8MEG18,
|
|
Q0=>RowA_4, F1=>CmdUFMCLK_1_sqmuxa, Q1=>RowA_5);
|
|
SLICE_68I: SLICE_68
|
|
port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_14_i_a2_0_1,
|
|
C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_31,
|
|
F1=>un1_FS_14_i_a2_0_1);
|
|
SLICE_69I: SLICE_69
|
|
port map (D1=>FS_5, C1=>FS_3, B1=>FS_2, A1=>FS_0, D0=>un1_FS_13_i_a2_1,
|
|
C0=>N_137_8, B0=>N_137_6, A0=>N_136, F0=>N_33,
|
|
F1=>un1_FS_13_i_a2_1);
|
|
SLICE_70I: SLICE_70
|
|
port map (D1=>C1WR_0_a2_0_11, C1=>C1WR_0_a2_0_10, B1=>Bank_1, A1=>Bank_0,
|
|
B0=>N_147, A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c,
|
|
F0=>C1WR_0_a2, Q0=>Bank_0, F1=>N_147, Q1=>Bank_1);
|
|
SLICE_71I: SLICE_71
|
|
port map (D1=>MAin_c_7, C1=>MAin_c_6, B1=>MAin_c_5, A1=>MAin_c_4,
|
|
D0=>C1WR_0_a2_0_4, C0=>C1WR_0_a2_0_3, B0=>Bank_4, A0=>Bank_3,
|
|
M1=>Din_c_3, M0=>Din_c_2, CLK=>PHI2_c, F0=>C1WR_0_a2_0_10,
|
|
Q0=>Bank_2, F1=>C1WR_0_a2_0_4, Q1=>Bank_3);
|
|
SLICE_72I: SLICE_72
|
|
port map (C1=>UFMSDI_ens2_i_o2_0_3, B1=>FS_16, A1=>FS_12, D0=>N_51,
|
|
C0=>FS_11, B0=>FS_4, A0=>FS_1, M1=>MAin_c_3, M0=>MAin_c_2,
|
|
LSR=>Ready_fast, CLK=>nCRAS_c, F0=>N_129, Q0=>RowA_2, F1=>N_51,
|
|
Q1=>RowA_3);
|
|
SLICE_73I: SLICE_73
|
|
port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, B0=>Ready,
|
|
A0=>N_155, M1=>Din_c_2, M0=>Din_c_1, CE=>CmdUFMCLK_1_sqmuxa,
|
|
CLK=>PHI2_c, F0=>N_159, Q0=>CmdUFMCLK, F1=>N_155, Q1=>CmdUFMCS);
|
|
SLICE_74I: SLICE_74
|
|
port map (B1=>FS_14, A1=>FS_11, D0=>N_95_5, C0=>N_95_3, B0=>FS_16,
|
|
A0=>FS_10, M0=>Din_c_0, CE=>CmdUFMCLK_1_sqmuxa, CLK=>PHI2_c,
|
|
F0=>InitReady3, Q0=>CmdUFMSDI, F1=>N_95_3);
|
|
SLICE_75I: SLICE_75
|
|
port map (C1=>Din_c_7, B1=>Din_c_6, A1=>Din_c_4, C0=>N_128, B0=>Din_c_5,
|
|
A0=>Din_c_1, M1=>CASr, M0=>nCCAS_c, CLK=>RCLK_c, F0=>N_133,
|
|
Q0=>CASr, F1=>N_128, Q1=>CASr2);
|
|
SLICE_76I: SLICE_76
|
|
port map (B1=>Din_c_5, A1=>Din_c_0, D0=>MAin_c_0, C0=>Din_c_3,
|
|
B0=>Din_c_1, A0=>CmdEnable16_4, M1=>Din_c_5, M0=>Din_c_4,
|
|
CLK=>PHI2_c, F0=>CmdEnable16_0_a2_4, Q0=>Bank_4,
|
|
F1=>CmdEnable16_4, Q1=>Bank_5);
|
|
SLICE_77I: SLICE_77
|
|
port map (B1=>Din_c_7, A1=>Din_c_4, D0=>MAin_c_1, C0=>Din_c_6,
|
|
B0=>Din_c_2, A0=>CmdEnable16_1, M1=>Din_c_7, M0=>Din_c_6,
|
|
CLK=>PHI2_c, F0=>CmdEnable16_0_a2_5, Q0=>Bank_6,
|
|
F1=>CmdEnable16_1, Q1=>Bank_7);
|
|
SLICE_78I: SLICE_78
|
|
port map (B1=>Din_c_5, A1=>Din_c_3, D0=>N_43, C0=>MAin_c_1, B0=>Din_c_6,
|
|
A0=>Din_c_2, M1=>nCCAS_c, M0=>nCCAS_c, CLK=>nCRAS_c,
|
|
F0=>CmdEnable17_0_a2_4, Q0=>CBR, F1=>N_43, Q1=>CBR_fast);
|
|
SLICE_79I: SLICE_79
|
|
port map (C1=>Ready, B1=>CASr3, A1=>CASr2, D0=>m6_0_a2_2, C0=>S_1,
|
|
B0=>CO0, A0=>CBR, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c,
|
|
F0=>G_17_1, Q0=>WRD_0, F1=>m6_0_a2_2, Q1=>WRD_1);
|
|
SLICE_80I: SLICE_80
|
|
port map (B1=>CASr3, A1=>CASr2, D0=>g4_0_0_0, C0=>FWEr, B0=>CO0,
|
|
A0=>CBR_fast, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready_fast,
|
|
CLK=>nCRAS_c, F0=>g0_1, Q0=>RowA_8, F1=>g4_0_0_0, Q1=>RowA_9);
|
|
SLICE_81I: SLICE_81
|
|
port map (D1=>FS_17, C1=>FS_15, B1=>FS_14, A1=>FS_13, D0=>FS_17,
|
|
C0=>FS_15, B0=>FS_13, A0=>FS_12, M1=>nFWE_c, M0=>nFWE_c,
|
|
CLK=>nCRAS_c, F0=>N_95_5, Q0=>FWEr, F1=>UFMSDI_ens2_i_o2_0_3,
|
|
Q1=>FWEr_fast);
|
|
SLICE_82I: SLICE_82
|
|
port map (D1=>Din_c_3, C1=>Din_c_5, B1=>CmdLEDEN, A1=>N_128, D0=>Din_c_3,
|
|
C0=>Din_c_5, B0=>N_128, A0=>XOR8MEG18, M0=>CASr2, CLK=>RCLK_c,
|
|
F0=>CmdSubmitted_1_sqmuxa, Q0=>CASr3, F1=>N_132);
|
|
SLICE_83I: SLICE_83
|
|
port map (C1=>IS_3, B1=>IS_2, A1=>IS_1, C0=>IS_2, B0=>IS_1, A0=>IS_0,
|
|
M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready_fast, CLK=>nCRAS_c,
|
|
F0=>N_165, Q0=>RBA_c_0, F1=>N_160, Q1=>RBA_c_1);
|
|
SLICE_84I: SLICE_84
|
|
port map (D1=>FS_11, C1=>FS_10, B1=>FS_8, A1=>FS_6, D0=>FS_10, C0=>FS_7,
|
|
B0=>FS_6, A0=>FS_1, F0=>N_137_6, F1=>UFMSDI_ens2_i_a2_4_2);
|
|
SLICE_85I: SLICE_85
|
|
port map (D1=>Din_c_4, C1=>Din_c_7, B1=>Din_c_0, A1=>Din_c_1,
|
|
D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4,
|
|
M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>un1_Din_4,
|
|
Q0=>WRD_2, F1=>CmdEnable17_0_a2_3, Q1=>WRD_3);
|
|
SLICE_86I: SLICE_86
|
|
port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9,
|
|
A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQML_c);
|
|
SLICE_87I: SLICE_87
|
|
port map (C1=>N_151, B1=>UFMSDI_ens2_i_a0, A1=>CmdUFMSDI, D0=>N_151,
|
|
C0=>FS_11, B0=>FS_9, A0=>FS_4, F0=>N_137_8,
|
|
F1=>UFMSDI_r_xx_mm_1);
|
|
SLICE_88I: SLICE_88
|
|
port map (C1=>nFWE_c, B1=>MAin_c_3, A1=>MAin_c_2, B0=>nFWE_c,
|
|
A0=>nCCAS_c, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready_fast,
|
|
CLK=>nCRAS_c, F0=>RD_1_i, Q0=>RowA_6, F1=>C1WR_0_a2_0_3,
|
|
Q1=>RowA_7);
|
|
SLICE_89I: SLICE_89
|
|
port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_8,
|
|
A0=>MAin_c_8, F0=>RA_c_8, F1=>RDQMH_c);
|
|
SLICE_90I: SLICE_90
|
|
port map (C1=>MAin_c_1, B1=>MAin_c_0, A1=>N_147, C0=>nRowColSel,
|
|
B0=>RowA_0, A0=>MAin_c_0, F0=>RA_c_0, F1=>un1_CMDWR);
|
|
SLICE_91I: SLICE_91
|
|
port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, C0=>nRowColSel,
|
|
B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_7);
|
|
SLICE_92I: SLICE_92
|
|
port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel,
|
|
B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
|
|
SLICE_93I: SLICE_93
|
|
port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel,
|
|
B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
|
|
SLICE_94I: SLICE_94
|
|
port map (B1=>N_155, A1=>Ready, B0=>S_1, A0=>Ready, M0=>IS_0,
|
|
LSR=>RA10s_i, CLK=>RCLK_c, F0=>RCKEEN_8_u_0_a2_1_out,
|
|
Q0=>RA_c_10, F1=>N_159_i);
|
|
RD_0_I: RD_0_B
|
|
port map (PADDI=>RD_in_0, PADDT=>RD_1_i, PADDO=>WRD_0, RD0=>RD(0));
|
|
Dout_0_I: Dout_0_B
|
|
port map (PADDO=>RD_in_0, Dout0=>Dout(0));
|
|
PHI2I: PHI2B
|
|
port map (PADDI=>PHI2_c, PHI2S=>PHI2);
|
|
UFMSDOI: UFMSDOB
|
|
port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO);
|
|
UFMSDII: UFMSDIB
|
|
port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI);
|
|
UFMCLKI: UFMCLKB
|
|
port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK);
|
|
nUFMCSI: nUFMCSB
|
|
port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS);
|
|
RDQMLI: RDQMLB
|
|
port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
|
|
RDQMHI: RDQMHB
|
|
port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
|
|
nRCASI: nRCASB
|
|
port map (PADDO=>nRCAS_c, nRCASS=>nRCAS);
|
|
nRRASI: nRRASB
|
|
port map (PADDO=>nRRAS_c, nRRASS=>nRRAS);
|
|
nRWEI: nRWEB
|
|
port map (PADDO=>nRWE_c, nRWES=>nRWE);
|
|
RCKEI: RCKEB
|
|
port map (PADDO=>RCKE_c, RCKES=>RCKE);
|
|
RCLKI: RCLKB
|
|
port map (PADDI=>RCLK_c, RCLKS=>RCLK);
|
|
nRCSI: nRCSB
|
|
port map (PADDO=>nRCS_c, nRCSS=>nRCS);
|
|
RD_7_I: RD_7_B
|
|
port map (PADDI=>RD_in_7, PADDT=>RD_1_i, PADDO=>WRD_7, RD7=>RD(7));
|
|
RD_6_I: RD_6_B
|
|
port map (PADDI=>RD_in_6, PADDT=>RD_1_i, PADDO=>WRD_6, RD6=>RD(6));
|
|
RD_5_I: RD_5_B
|
|
port map (PADDI=>RD_in_5, PADDT=>RD_1_i, PADDO=>WRD_5, RD5=>RD(5));
|
|
RD_4_I: RD_4_B
|
|
port map (PADDI=>RD_in_4, PADDT=>RD_1_i, PADDO=>WRD_4, RD4=>RD(4));
|
|
RD_3_I: RD_3_B
|
|
port map (PADDI=>RD_in_3, PADDT=>RD_1_i, PADDO=>WRD_3, RD3=>RD(3));
|
|
RD_2_I: RD_2_B
|
|
port map (PADDI=>RD_in_2, PADDT=>RD_1_i, PADDO=>WRD_2, RD2=>RD(2));
|
|
RD_1_I0: RD_1_B
|
|
port map (PADDI=>RD_in_1, PADDT=>RD_1_i, PADDO=>WRD_1, RD1=>RD(1));
|
|
RA_11_I: RA_11_B
|
|
port map (PADDO=>RA_c_11, RA11=>RA(11));
|
|
RA_10_I: RA_10_B
|
|
port map (PADDO=>RA_c_10, RA10=>RA(10));
|
|
RA_9_I: RA_9_B
|
|
port map (PADDO=>RA_c_9, RA9=>RA(9));
|
|
RA_8_I: RA_8_B
|
|
port map (PADDO=>RA_c_8, RA8=>RA(8));
|
|
RA_7_I: RA_7_B
|
|
port map (PADDO=>RA_c_7, RA7=>RA(7));
|
|
RA_6_I: RA_6_B
|
|
port map (PADDO=>RA_c_6, RA6=>RA(6));
|
|
RA_5_I: RA_5_B
|
|
port map (PADDO=>RA_c_5, RA5=>RA(5));
|
|
RA_4_I: RA_4_B
|
|
port map (PADDO=>RA_c_4, RA4=>RA(4));
|
|
RA_3_I: RA_3_B
|
|
port map (PADDO=>RA_c_3, RA3=>RA(3));
|
|
RA_2_I: RA_2_B
|
|
port map (PADDO=>RA_c_2, RA2=>RA(2));
|
|
RA_1_I: RA_1_B
|
|
port map (PADDO=>RA_c_1, RA1=>RA(1));
|
|
RA_0_I: RA_0_B
|
|
port map (PADDO=>RA_c_0, RA0=>RA(0));
|
|
RBA_1_I: RBA_1_B
|
|
port map (PADDO=>RBA_c_1, RBA1=>RBA(1));
|
|
RBA_0_I: RBA_0_B
|
|
port map (PADDO=>RBA_c_0, RBA0=>RBA(0));
|
|
LEDI: LEDB
|
|
port map (PADDO=>LED_c, LEDS=>LED);
|
|
nFWEI: nFWEB
|
|
port map (PADDI=>nFWE_c, nFWES=>nFWE);
|
|
nCRASI: nCRASB
|
|
port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
|
|
nCCASI: nCCASB
|
|
port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
|
|
Dout_7_I: Dout_7_B
|
|
port map (PADDO=>RD_in_7, Dout7=>Dout(7));
|
|
Dout_6_I: Dout_6_B
|
|
port map (PADDO=>RD_in_6, Dout6=>Dout(6));
|
|
Dout_5_I: Dout_5_B
|
|
port map (PADDO=>RD_in_5, Dout5=>Dout(5));
|
|
Dout_4_I: Dout_4_B
|
|
port map (PADDO=>RD_in_4, Dout4=>Dout(4));
|
|
Dout_3_I: Dout_3_B
|
|
port map (PADDO=>RD_in_3, Dout3=>Dout(3));
|
|
Dout_2_I: Dout_2_B
|
|
port map (PADDO=>RD_in_2, Dout2=>Dout(2));
|
|
Dout_1_I: Dout_1_B
|
|
port map (PADDO=>RD_in_1, Dout1=>Dout(1));
|
|
Din_7_I: Din_7_B
|
|
port map (PADDI=>Din_c_7, Din7=>Din(7));
|
|
Din_6_I: Din_6_B
|
|
port map (PADDI=>Din_c_6, Din6=>Din(6));
|
|
Din_5_I: Din_5_B
|
|
port map (PADDI=>Din_c_5, Din5=>Din(5));
|
|
Din_4_I: Din_4_B
|
|
port map (PADDI=>Din_c_4, Din4=>Din(4));
|
|
Din_3_I: Din_3_B
|
|
port map (PADDI=>Din_c_3, Din3=>Din(3));
|
|
Din_2_I: Din_2_B
|
|
port map (PADDI=>Din_c_2, Din2=>Din(2));
|
|
Din_1_I: Din_1_B
|
|
port map (PADDI=>Din_c_1, Din1=>Din(1));
|
|
Din_0_I: Din_0_B
|
|
port map (PADDI=>Din_c_0, Din0=>Din(0));
|
|
CROW_1_I: CROW_1_B
|
|
port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
|
|
CROW_0_I: CROW_0_B
|
|
port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
|
|
MAin_9_I: MAin_9_B
|
|
port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
|
|
MAin_8_I: MAin_8_B
|
|
port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
|
|
MAin_7_I: MAin_7_B
|
|
port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
|
|
MAin_6_I: MAin_6_B
|
|
port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
|
|
MAin_5_I: MAin_5_B
|
|
port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
|
|
MAin_4_I: MAin_4_B
|
|
port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
|
|
MAin_3_I: MAin_3_B
|
|
port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
|
|
MAin_2_I: MAin_2_B
|
|
port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
|
|
MAin_1_I: MAin_1_B
|
|
port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
|
|
MAin_0_I: MAin_0_B
|
|
port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
|
|
VHI_INST: VHI
|
|
port map (Z=>VCCI);
|
|
PUR_INST: PUR
|
|
port map (PUR=>VCCI);
|
|
GSR_INST: GSR
|
|
port map (GSR=>VCCI);
|
|
VLO_INST: VLO
|
|
port map (Z=>GNDI_TSALL);
|
|
TSALL_INST: TSALL
|
|
port map (TSALL=>GNDI_TSALL);
|
|
end Structure;
|
|
|
|
|
|
|
|
library IEEE, vital2000, MACHXO;
|
|
configuration Structure_CON of RAM2GS is
|
|
for Structure
|
|
end for;
|
|
end Structure_CON;
|
|
|
|
|