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RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html
Zane Kaminski 8cbf2f47ad RC?
2023-08-16 05:11:25 -04:00

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<HTML>
<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Wed Aug 16 04:50:48 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,3
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
Report: 56.029MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
Report: 128.419MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
129 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.490ns (weighted slack = 326.980ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[2] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 8.750ns (27.6% logic, 72.4% route), 6 logic levels.
Constraint Details:
8.750ns physical path delay SLICE_71 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.490ns
Physical Path Details:
Data path SLICE_71 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c)
ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2]
CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147
CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67
ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18
CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82
ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22
ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c)
--------
8.750 (27.6% logic, 72.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_71:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.526ns (weighted slack = 327.052ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[5] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 8.714ns (27.7% logic, 72.3% route), 6 logic levels.
Constraint Details:
8.714ns physical path delay SLICE_76 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.526ns
Physical Path Details:
Data path SLICE_76 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c)
ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5]
CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147
CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67
ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18
CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82
ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22
ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c)
--------
8.714 (27.7% logic, 72.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.560ns (weighted slack = 327.120ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[7] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 8.680ns (27.8% logic, 72.2% route), 6 logic levels.
Constraint Details:
8.680ns physical path delay SLICE_77 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.560ns
Physical Path Details:
Data path SLICE_77 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q1 SLICE_77 (from PHI2_c)
ROUTE 1 1.513 R6C3A.Q1 to R4C5A.D1 Bank[7]
CTOF_DEL --- 0.371 R4C5A.D1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147
CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67
ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18
CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82
ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22
ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c)
--------
8.680 (27.8% logic, 72.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.688ns (weighted slack = 327.376ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[2] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.552ns (26.9% logic, 73.1% route), 5 logic levels.
Constraint Details:
8.552ns physical path delay SLICE_71 to SLICE_20 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.688ns
Physical Path Details:
Data path SLICE_71 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c)
ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2]
CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147
CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90
ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR
CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
8.552 (26.9% logic, 73.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_71:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.724ns (weighted slack = 327.448ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[5] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.516ns (27.1% logic, 72.9% route), 5 logic levels.
Constraint Details:
8.516ns physical path delay SLICE_76 to SLICE_20 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.724ns
Physical Path Details:
Data path SLICE_76 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c)
ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5]
CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147
CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90
ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR
CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
8.516 (27.1% logic, 72.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.725ns (weighted slack = 327.450ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[6] (from PHI2_c +)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 8.515ns (28.4% logic, 71.6% route), 6 logic levels.
Constraint Details:
8.515ns physical path delay SLICE_77 to SLICE_22 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.725ns
Physical Path Details:
Data path SLICE_77 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q0 SLICE_77 (from PHI2_c)
ROUTE 1 1.348 R6C3A.Q0 to R4C5A.C1 Bank[6]
CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147
CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67
ROUTE 5 1.215 R5C3A.F0 to R6C4D.D0 XOR8MEG18
CTOF_DEL --- 0.371 R6C4D.D0 to R6C4D.F0 SLICE_82
ROUTE 1 0.819 R6C4D.F0 to R6C4A.C0 CmdSubmitted_1_sqmuxa
CTOF_DEL --- 0.371 R6C4A.C0 to R6C4A.F0 SLICE_22
ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c)
--------
8.515 (28.4% logic, 71.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C4A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.758ns (weighted slack = 327.516ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[7] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.482ns (27.2% logic, 72.8% route), 5 logic levels.
Constraint Details:
8.482ns physical path delay SLICE_77 to SLICE_20 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.758ns
Physical Path Details:
Data path SLICE_77 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q1 SLICE_77 (from PHI2_c)
ROUTE 1 1.513 R6C3A.Q1 to R4C5A.D1 Bank[7]
CTOF_DEL --- 0.371 R4C5A.D1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147
CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90
ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR
CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
8.482 (27.2% logic, 72.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.923ns (weighted slack = 327.846ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[6] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.317ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
8.317ns physical path delay SLICE_77 to SLICE_20 meets
172.414ns delay constraint less
0.000ns skew and
0.174ns DIN_SET requirement (totaling 172.240ns) by 163.923ns
Physical Path Details:
Data path SLICE_77 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3A.CLK to R6C3A.Q0 SLICE_77 (from PHI2_c)
ROUTE 1 1.348 R6C3A.Q0 to R4C5A.C1 Bank[6]
CTOF_DEL --- 0.371 R4C5A.C1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.578 R5C2C.F1 to R2C2B.B1 N_147
CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 SLICE_90
ROUTE 1 1.444 R2C2B.F1 to R5C3D.C0 un1_CMDWR
CTOOFX_DEL --- 0.631 R5C3D.C0 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
8.317 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3A.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R5C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.952ns (weighted slack = 327.904ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[2] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.197ns (24.9% logic, 75.1% route), 5 logic levels.
Constraint Details:
8.197ns physical path delay SLICE_71 to SLICE_74 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 163.952ns
Physical Path Details:
Data path SLICE_71 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C2C.CLK to R6C2C.Q0 SLICE_71 (from PHI2_c)
ROUTE 1 1.583 R6C2C.Q0 to R4C5A.A1 Bank[2]
CTOF_DEL --- 0.371 R4C5A.A1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147
CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67
ROUTE 5 0.682 R5C3A.F0 to R5C3A.A1 XOR8MEG18
CTOF_DEL --- 0.371 R5C3A.A1 to R5C3A.F1 SLICE_67
ROUTE 2 1.170 R5C3A.F1 to R7C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.197 (24.9% logic, 75.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_71:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C2C.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R7C4B.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.988ns (weighted slack = 327.976ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank[5] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.161ns (25.0% logic, 75.0% route), 5 logic levels.
Constraint Details:
8.161ns physical path delay SLICE_76 to SLICE_74 meets
172.414ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 172.149ns) by 163.988ns
Physical Path Details:
Data path SLICE_76 to SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R6C3D.CLK to R6C3D.Q1 SLICE_76 (from PHI2_c)
ROUTE 1 1.547 R6C3D.Q1 to R4C5A.B1 Bank[5]
CTOF_DEL --- 0.371 R4C5A.B1 to R4C5A.F1 SLICE_56
ROUTE 1 1.643 R4C5A.F1 to R5C2C.B1 C1WR_0_a2_0_11
CTOF_DEL --- 0.371 R5C2C.B1 to R5C2C.F1 SLICE_70
ROUTE 6 1.075 R5C2C.F1 to R5C3A.A0 N_147
CTOF_DEL --- 0.371 R5C3A.A0 to R5C3A.F0 SLICE_67
ROUTE 5 0.682 R5C3A.F0 to R5C3A.A1 XOR8MEG18
CTOF_DEL --- 0.371 R5C3A.A1 to R5C3A.F1 SLICE_67
ROUTE 2 1.170 R5C3A.F1 to R7C4B.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.161 (25.0% logic, 75.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R6C3D.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 15 3.919 39.PADDI to R7C4B.CLK PHI2_c
--------
3.919 (0.0% logic, 100.0% route), 0 logic levels.
Report: 56.029MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 342.328ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 400.000MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 342.328ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 400.000MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
388 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.213ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 7.543ns (32.0% logic, 68.0% route), 6 logic levels.
Constraint Details:
7.543ns physical path delay SLICE_2 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.213ns
Physical Path Details:
Data path SLICE_2 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 1.571 R8C3D.Q1 to R7C4A.B1 FS[15]
CTOF_DEL --- 0.371 R7C4A.B1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8
CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69
ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c)
--------
7.543 (32.0% logic, 68.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.305ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 7.451ns (32.4% logic, 67.6% route), 6 logic levels.
Constraint Details:
7.451ns physical path delay SLICE_2 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.305ns
Physical Path Details:
Data path SLICE_2 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 1.571 R8C3D.Q1 to R7C4A.B1 FS[15]
CTOF_DEL --- 0.371 R7C4A.B1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8
CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68
ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c)
--------
7.451 (32.4% logic, 67.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.378ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 7.378ns (32.7% logic, 67.3% route), 6 logic levels.
Constraint Details:
7.378ns physical path delay SLICE_1 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.378ns
Physical Path Details:
Data path SLICE_1 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c)
ROUTE 3 1.406 R8C4A.Q1 to R7C4A.A1 FS[17]
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8
CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69
ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c)
--------
7.378 (32.7% logic, 67.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C4A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.404ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 7.352ns (32.8% logic, 67.2% route), 6 logic levels.
Constraint Details:
7.352ns physical path delay SLICE_2 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.404ns
Physical Path Details:
Data path SLICE_2 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c)
ROUTE 3 1.380 R8C3D.Q0 to R7C4A.C1 FS[14]
CTOF_DEL --- 0.371 R7C4A.C1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8
CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69
ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c)
--------
7.352 (32.8% logic, 67.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.470ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 7.286ns (33.1% logic, 66.9% route), 6 logic levels.
Constraint Details:
7.286ns physical path delay SLICE_1 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.470ns
Physical Path Details:
Data path SLICE_1 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c)
ROUTE 3 1.406 R8C4A.Q1 to R7C4A.A1 FS[17]
CTOF_DEL --- 0.371 R7C4A.A1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8
CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68
ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c)
--------
7.286 (33.1% logic, 66.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C4A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.496ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 7.260ns (33.3% logic, 66.7% route), 6 logic levels.
Constraint Details:
7.260ns physical path delay SLICE_2 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.496ns
Physical Path Details:
Data path SLICE_2 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C3D.CLK to R8C3D.Q0 SLICE_2 (from RCLK_c)
ROUTE 3 1.380 R8C3D.Q0 to R7C4A.C1 FS[14]
CTOF_DEL --- 0.371 R7C4A.C1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8
CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68
ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c)
--------
7.260 (33.3% logic, 66.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C3D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.592ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[0] (from RCLK_c +)
Destination: FF Data in Ready_fast (to RCLK_c +)
Delay: 7.227ns (23.1% logic, 76.9% route), 4 logic levels.
Constraint Details:
7.227ns physical path delay SLICE_29 to SLICE_44 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 8.592ns
Physical Path Details:
Data path SLICE_29 to SLICE_44:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C5D.CLK to R2C5D.Q0 SLICE_29 (from RCLK_c)
ROUTE 9 3.095 R2C5D.Q0 to R6C5A.B0 IS[0]
CTOF_DEL --- 0.371 R6C5A.B0 to R6C5A.F0 SLICE_83
ROUTE 2 1.962 R6C5A.F0 to R4C4D.A1 N_165
CTOF_DEL --- 0.371 R4C4D.A1 to R4C4D.F1 SLICE_44
ROUTE 1 0.497 R4C4D.F1 to R4C4D.C0 Ready_0_sqmuxa
CTOF_DEL --- 0.371 R4C4D.C0 to R4C4D.F0 SLICE_44
ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 N_463_0 (to RCLK_c)
--------
7.227 (23.1% logic, 76.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R2C5D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_44:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R4C4D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.599ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 7.157ns (33.7% logic, 66.3% route), 6 logic levels.
Constraint Details:
7.157ns physical path delay SLICE_3 to SLICE_33 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.599ns
Physical Path Details:
Data path SLICE_3 to SLICE_33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 1.185 R8C3C.Q1 to R7C4A.D1 FS[13]
CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2D.D0 N_137_8
CTOF_DEL --- 0.371 R7C2D.D0 to R7C2D.F0 SLICE_69
ROUTE 1 1.165 R7C2D.F0 to R7C5A.CE N_33 (to RCLK_c)
--------
7.157 (33.7% logic, 66.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C5A.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.660ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[7] (from RCLK_c +)
Destination: FF Data in UFMSDI (to RCLK_c +)
Delay: 7.159ns (28.6% logic, 71.4% route), 5 logic levels.
Constraint Details:
7.159ns physical path delay SLICE_6 to SLICE_52 meets
16.000ns delay constraint less
0.000ns skew and
0.181ns DIN_SET requirement (totaling 15.819ns) by 8.660ns
Physical Path Details:
Data path SLICE_6 to SLICE_52:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C2D.CLK to R8C2D.Q1 SLICE_6 (from RCLK_c)
ROUTE 3 2.186 R8C2D.Q1 to R4C5A.B0 FS[7]
CTOF_DEL --- 0.371 R4C5A.B0 to R4C5A.F0 SLICE_56
ROUTE 1 1.609 R4C5A.F0 to R7C3A.D1 N_126
CTOF_DEL --- 0.371 R7C3A.D1 to R7C3A.F1 SLICE_32
ROUTE 1 0.626 R7C3A.F1 to R7C3D.D1 UFMSDI_ens2_i_a0
CTOF_DEL --- 0.371 R7C3D.D1 to R7C3D.F1 SLICE_87
ROUTE 1 0.694 R7C3D.F1 to R7C5B.D0 UFMSDI_r_xx_mm_1
CTOF_DEL --- 0.371 R7C5B.D0 to R7C5B.F0 SLICE_52
ROUTE 1 0.000 R7C5B.F0 to R7C5B.DI0 UFMSDI_RNO (to RCLK_c)
--------
7.159 (28.6% logic, 71.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C2D.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_52:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C5B.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.691ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 7.065ns (34.2% logic, 65.8% route), 6 logic levels.
Constraint Details:
7.065ns physical path delay SLICE_3 to SLICE_58 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.691ns
Physical Path Details:
Data path SLICE_3 to SLICE_58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 1.185 R8C3C.Q1 to R7C4A.D1 FS[13]
CTOF_DEL --- 0.371 R7C4A.D1 to R7C4A.F1 SLICE_81
ROUTE 1 0.700 R7C4A.F1 to R7C3B.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.371 R7C3B.D1 to R7C3B.F1 SLICE_72
ROUTE 4 0.350 R7C3B.F1 to R7C3C.D1 N_51
CTOF_DEL --- 0.371 R7C3C.D1 to R7C3C.F1 SLICE_58
ROUTE 2 0.642 R7C3C.F1 to R7C3D.D0 N_151
CTOF_DEL --- 0.371 R7C3D.D0 to R7C3D.F0 SLICE_87
ROUTE 2 0.700 R7C3D.F0 to R7C2B.D0 N_137_8
CTOF_DEL --- 0.371 R7C2B.D0 to R7C2B.F0 SLICE_68
ROUTE 1 1.073 R7C2B.F0 to R7C3C.CE N_31 (to RCLK_c)
--------
7.065 (34.2% logic, 65.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R8C3C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
ROUTE 32 1.353 86.PADDI to R7C3C.CLK RCLK_c
--------
1.353 (0.0% logic, 100.0% route), 0 logic levels.
Report: 128.419MHz is the maximum frequency for this preference.
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 56.029 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 128.419 MHz| 6
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 10
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 8
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 32
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Wed Aug 16 04:50:48 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
Design file: ram2gs_lcmxo256c_impl1.ncd
Preference file: ram2gs_lcmxo256c_impl1.prf
Device,speed: LCMXO256C,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
129 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.358ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.339ns (62.2% logic, 37.8% route), 2 logic levels.
Constraint Details:
0.339ns physical path delay SLICE_9 to SLICE_9 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.358ns
Physical Path Details:
Data path SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3B.CLK to R5C3B.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.128 R5C3B.Q0 to R5C3B.D0 ADSubmitted
CTOF_DEL --- 0.074 R5C3B.D0 to R5C3B.F0 SLICE_9
ROUTE 1 0.000 R5C3B.F0 to R5C3B.DI0 ADSubmitted_r (to PHI2_c)
--------
0.339 (62.2% logic, 37.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.364ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdSubmitted (from PHI2_c -)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 0.345ns (61.2% logic, 38.8% route), 2 logic levels.
Constraint Details:
0.345ns physical path delay SLICE_22 to SLICE_22 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.364ns
Physical Path Details:
Data path SLICE_22 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C4A.CLK to R6C4A.Q0 SLICE_22 (from PHI2_c)
ROUTE 3 0.134 R6C4A.Q0 to R6C4A.A0 CmdSubmitted
CTOF_DEL --- 0.074 R6C4A.A0 to R6C4A.F0 SLICE_22
ROUTE 1 0.000 R6C4A.F0 to R6C4A.DI0 N_460_0 (to PHI2_c)
--------
0.345 (61.2% logic, 38.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C4A.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C4A.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.415ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.396ns (66.2% logic, 33.8% route), 2 logic levels.
Constraint Details:
0.396ns physical path delay SLICE_20 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.415ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.134 R5C3D.Q0 to R5C3D.A0 CmdEnable
CTOOFX_DEL --- 0.125 R5C3D.A0 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
0.396 (66.2% logic, 33.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.436ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 0.417ns (50.6% logic, 49.4% route), 2 logic levels.
Constraint Details:
0.417ns physical path delay SLICE_14 to SLICE_14 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.436ns
Physical Path Details:
Data path SLICE_14 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_14 (from PHI2_c)
ROUTE 2 0.206 R5C3C.Q0 to R5C3C.B0 C1Submitted
CTOF_DEL --- 0.074 R5C3C.B0 to R5C3C.F0 SLICE_14
ROUTE 1 0.000 R5C3C.F0 to R5C3C.DI0 C1Submitted_RNO (to PHI2_c)
--------
0.417 (50.6% logic, 49.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.477ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.458ns (56.3% logic, 43.7% route), 2 logic levels.
Constraint Details:
0.458ns physical path delay SLICE_20 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.477ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.200 R5C3D.Q0 to R5C3D.A1 CmdEnable
CTOOFX_DEL --- 0.121 R5C3D.A1 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
0.458 (56.3% logic, 43.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.483ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.464ns (55.6% logic, 44.4% route), 2 logic levels.
Constraint Details:
0.464ns physical path delay SLICE_9 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.483ns
Physical Path Details:
Data path SLICE_9 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3B.CLK to R5C3B.Q0 SLICE_9 (from PHI2_c)
ROUTE 2 0.206 R5C3B.Q0 to R5C3D.B1 ADSubmitted
CTOOFX_DEL --- 0.121 R5C3D.B1 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
0.464 (55.6% logic, 44.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3B.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.487ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.468ns (56.0% logic, 44.0% route), 2 logic levels.
Constraint Details:
0.468ns physical path delay SLICE_14 to SLICE_20 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.487ns
Physical Path Details:
Data path SLICE_14 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3C.CLK to R5C3C.Q0 SLICE_14 (from PHI2_c)
ROUTE 2 0.206 R5C3C.Q0 to R5C3D.B0 C1Submitted
CTOOFX_DEL --- 0.125 R5C3D.B0 to R5C3D.OFX0 SLICE_20
ROUTE 1 0.000 R5C3D.OFX0 to R5C3D.DI0 CmdEnable_s (to PHI2_c)
--------
0.468 (56.0% logic, 44.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3C.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.595ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 0.572ns (36.9% logic, 63.1% route), 2 logic levels.
Constraint Details:
0.572ns physical path delay SLICE_20 to SLICE_26 meets
-0.023ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.023ns) by 0.595ns
Physical Path Details:
Data path SLICE_20 to SLICE_26:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R5C3D.CLK to R5C3D.Q0 SLICE_20 (from PHI2_c)
ROUTE 3 0.134 R5C3D.Q0 to R5C3A.D0 CmdEnable
CTOF_DEL --- 0.074 R5C3A.D0 to R5C3A.F0 SLICE_67
ROUTE 5 0.227 R5C3A.F0 to R6C3B.CE XOR8MEG18 (to PHI2_c)
--------
0.572 (36.9% logic, 63.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R5C3D.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_26:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.611ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Cmdn8MEGEN (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 0.592ns (48.1% logic, 51.9% route), 3 logic levels.
Constraint Details:
0.592ns physical path delay SLICE_26 to SLICE_26 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.611ns
Physical Path Details:
Data path SLICE_26 to SLICE_26:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C3B.CLK to R6C3B.Q0 SLICE_26 (from PHI2_c)
ROUTE 2 0.208 R6C3B.Q0 to R6C3B.B1 Cmdn8MEGEN
CTOF_DEL --- 0.074 R6C3B.B1 to R6C3B.F1 SLICE_26
ROUTE 1 0.099 R6C3B.F1 to R6C3B.C0 Cmdn8MEGEN_4_u_i_0
CTOF_DEL --- 0.074 R6C3B.C0 to R6C3B.F0 SLICE_26
ROUTE 1 0.000 R6C3B.F0 to R6C3B.DI0 N_19_i (to PHI2_c)
--------
0.592 (48.1% logic, 51.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_26:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_26:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C3B.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.650ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdLEDEN (from PHI2_c -)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 0.631ns (45.2% logic, 54.8% route), 3 logic levels.
Constraint Details:
0.631ns physical path delay SLICE_21 to SLICE_21 meets
-0.019ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.650ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.137 R6C4C.CLK to R6C4C.Q0 SLICE_21 (from PHI2_c)
ROUTE 2 0.208 R6C4C.Q0 to R6C4D.B1 CmdLEDEN
CTOF_DEL --- 0.074 R6C4D.B1 to R6C4D.F1 SLICE_82
ROUTE 1 0.138 R6C4D.F1 to R6C4C.B0 N_132
CTOF_DEL --- 0.074 R6C4C.B0 to R6C4C.F0 SLICE_21
ROUTE 1 0.000 R6C4C.F0 to R6C4C.DI0 N_21_i (to PHI2_c)
--------
0.631 (45.2% logic, 54.8% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 15 0.967 39.PADDI to R6C4C.CLK PHI2_c
--------
0.967 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
388 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.273ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels.
Constraint Details:
0.256ns physical path delay SLICE_75 to SLICE_75 meets
-0.017ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.017ns) by 0.273ns
Physical Path Details:
Data path SLICE_75 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R6C4B.CLK to R6C4B.Q0 SLICE_75 (from RCLK_c)
ROUTE 1 0.130 R6C4B.Q0 to R6C4B.M1 CASr (to RCLK_c)
--------
0.256 (49.2% logic, 50.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R6C4B.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R6C4B.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.277ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r2 (from RCLK_c +)
Destination: FF Data in PHI2r3 (to RCLK_c +)
Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.260ns physical path delay SLICE_41 to SLICE_43 meets
-0.017ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.017ns) by 0.277ns
Physical Path Details:
Data path SLICE_41 to SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R4C5C.CLK to R4C5C.Q1 SLICE_41 (from RCLK_c)
ROUTE 3 0.134 R4C5C.Q1 to R4C5D.M1 PHI2r2 (to RCLK_c)
--------
0.260 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_41:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R4C5C.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_43:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R4C5D.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in FS[17] (to RCLK_c +)
FF FS[16]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_1 to SLICE_1 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q1 SLICE_1 (from RCLK_c)
ROUTE 3 0.131 R8C4A.Q1 to R8C4A.A1 FS[17] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in FS_cry_0[14] (to RCLK_c +)
FF FS[15]
FF FS[14]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_2 to SLICE_2 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C3D.CLK to R8C3D.Q1 SLICE_2 (from RCLK_c)
ROUTE 3 0.131 R8C3D.Q1 to R8C3D.A1 FS[15] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3D.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3D.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in FS_cry_0[12] (to RCLK_c +)
FF FS[13]
FF FS[12]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_3 to SLICE_3 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C3C.CLK to R8C3C.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 0.131 R8C3C.Q1 to R8C3C.A1 FS[13] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3C.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3C.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from RCLK_c +)
Destination: FF Data in FS_cry_0[10] (to RCLK_c +)
FF FS[11]
FF FS[10]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_4 to SLICE_4 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C3B.CLK to R8C3B.Q1 SLICE_4 (from RCLK_c)
ROUTE 6 0.131 R8C3B.Q1 to R8C3B.A1 FS[11] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3B.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3B.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[3] (from RCLK_c +)
Destination: FF Data in FS_cry_0[2] (to RCLK_c +)
FF FS[3]
FF FS[2]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_8 to SLICE_8 meets
-0.044ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.044ns) by 0.301ns
Physical Path Details:
Data path SLICE_8 to SLICE_8:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C2B.CLK to R8C2B.Q1 SLICE_8 (from RCLK_c)
ROUTE 3 0.131 R8C2B.Q1 to R8C2B.A1 FS[3] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C2B.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C2B.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from RCLK_c +)
Destination: FF Data in FS_cry_0[0] (to RCLK_c +)
FF FS[1]
FF FS[0]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_0 to SLICE_0 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C2A.CLK to R8C2A.Q0 SLICE_0 (from RCLK_c)
ROUTE 3 0.131 R8C2A.Q0 to R8C2A.A0 FS[0] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C2A.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C2A.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[16] (from RCLK_c +)
Destination: FF Data in FS[17] (to RCLK_c +)
FF FS[16]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_1 to SLICE_1 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_1 (from RCLK_c)
ROUTE 4 0.131 R8C4A.Q0 to R8C4A.A0 FS[16] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C4A.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from RCLK_c +)
Destination: FF Data in FS_cry_0[12] (to RCLK_c +)
FF FS[13]
FF FS[12]
Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_3 to SLICE_3 meets
-0.045ns LUT_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.045ns) by 0.302ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R8C3C.CLK to R8C3C.Q0 SLICE_3 (from RCLK_c)
ROUTE 3 0.131 R8C3C.Q0 to R8C3C.A0 FS[12] (to RCLK_c)
--------
0.257 (49.0% logic, 51.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3C.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 32 0.333 86.PADDI to R8C3C.CLK RCLK_c
--------
0.333 (0.0% logic, 100.0% route), 0 logic levels.
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 10
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 8
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 32
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 517 paths, 4 nets, and 420 connections (66.35% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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