RAM2GS/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd
Zane Kaminski 8cbf2f47ad RC?
2023-08-16 05:11:25 -04:00

18 lines
364 B
Common Lisp

[ActiveSupport TRCE]
; Setup Analysis
Fmax_0 = 56.029 MHz (2.900 MHz);
Fmax_1 = 400.000 MHz (2.900 MHz);
Fmax_2 = 400.000 MHz (2.900 MHz);
Fmax_3 = 128.419 MHz (62.500 MHz);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Fmax_0 = - (-);
Fmax_1 = - (-);
Fmax_2 = - (-);
Fmax_3 = - (-);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;