mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-26 08:49:57 +00:00
103 lines
2.8 KiB
Plaintext
103 lines
2.8 KiB
Plaintext
[ START MERGED ]
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IS_i[0] IS[0]
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Ready_fast_i Ready_fast
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XOR8MEG.CN PHI2_c
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nCCAS_c_i nCCAS_c
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RASr2_i RASr2
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nCRAS_c_i nCRAS_c
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nCRAS_c_i_0 nCRAS_c
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nFWE_c_i nFWE_c
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[ END MERGED ]
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[ START CLIPPED ]
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GND
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VCC
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FS_cry[2]
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FS_cry[4]
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FS_cry[6]
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FS_cry[8]
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FS_cry[10]
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FS_cry[12]
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FS_cry[14]
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FS_cry_0_COUT1[16]
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FS_cry[16]
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FS_cry[0]
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[ END CLIPPED ]
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[ START DESIGN PREFS ]
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SCHEMATIC START ;
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# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 04:50:46 2023
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SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
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LOCATE COMP "RD[0]" SITE "64" ;
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LOCATE COMP "Dout[0]" SITE "1" ;
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LOCATE COMP "PHI2" SITE "39" ;
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LOCATE COMP "UFMSDO" SITE "55" ;
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LOCATE COMP "UFMSDI" SITE "56" ;
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LOCATE COMP "UFMCLK" SITE "58" ;
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LOCATE COMP "nUFMCS" SITE "53" ;
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LOCATE COMP "RDQML" SITE "61" ;
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LOCATE COMP "RDQMH" SITE "76" ;
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LOCATE COMP "nRCAS" SITE "78" ;
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LOCATE COMP "nRRAS" SITE "73" ;
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LOCATE COMP "nRWE" SITE "72" ;
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LOCATE COMP "RCKE" SITE "82" ;
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LOCATE COMP "RCLK" SITE "86" ;
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LOCATE COMP "nRCS" SITE "77" ;
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LOCATE COMP "RD[7]" SITE "71" ;
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LOCATE COMP "RD[6]" SITE "70" ;
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LOCATE COMP "RD[5]" SITE "69" ;
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LOCATE COMP "RD[4]" SITE "68" ;
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LOCATE COMP "RD[3]" SITE "67" ;
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LOCATE COMP "RD[2]" SITE "66" ;
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LOCATE COMP "RD[1]" SITE "65" ;
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LOCATE COMP "RA[11]" SITE "79" ;
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LOCATE COMP "RA[10]" SITE "87" ;
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LOCATE COMP "RA[9]" SITE "85" ;
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LOCATE COMP "RA[8]" SITE "96" ;
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LOCATE COMP "RA[7]" SITE "100" ;
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LOCATE COMP "RA[6]" SITE "91" ;
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LOCATE COMP "RA[5]" SITE "95" ;
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LOCATE COMP "RA[4]" SITE "99" ;
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LOCATE COMP "RA[3]" SITE "97" ;
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LOCATE COMP "RA[2]" SITE "94" ;
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LOCATE COMP "RA[1]" SITE "89" ;
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LOCATE COMP "RA[0]" SITE "98" ;
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LOCATE COMP "RBA[1]" SITE "83" ;
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LOCATE COMP "RBA[0]" SITE "63" ;
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LOCATE COMP "LED" SITE "57" ;
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LOCATE COMP "nFWE" SITE "22" ;
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LOCATE COMP "nCRAS" SITE "43" ;
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LOCATE COMP "nCCAS" SITE "27" ;
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LOCATE COMP "Dout[7]" SITE "3" ;
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LOCATE COMP "Dout[6]" SITE "2" ;
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LOCATE COMP "Dout[5]" SITE "5" ;
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LOCATE COMP "Dout[4]" SITE "4" ;
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LOCATE COMP "Dout[3]" SITE "6" ;
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LOCATE COMP "Dout[2]" SITE "8" ;
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LOCATE COMP "Dout[1]" SITE "7" ;
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LOCATE COMP "Din[7]" SITE "19" ;
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LOCATE COMP "Din[6]" SITE "20" ;
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LOCATE COMP "Din[5]" SITE "17" ;
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LOCATE COMP "Din[4]" SITE "18" ;
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LOCATE COMP "Din[3]" SITE "16" ;
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LOCATE COMP "Din[2]" SITE "14" ;
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LOCATE COMP "Din[1]" SITE "15" ;
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LOCATE COMP "Din[0]" SITE "21" ;
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LOCATE COMP "CROW[1]" SITE "34" ;
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LOCATE COMP "CROW[0]" SITE "32" ;
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LOCATE COMP "MAin[9]" SITE "51" ;
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LOCATE COMP "MAin[8]" SITE "50" ;
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LOCATE COMP "MAin[7]" SITE "44" ;
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LOCATE COMP "MAin[6]" SITE "49" ;
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LOCATE COMP "MAin[5]" SITE "45" ;
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LOCATE COMP "MAin[4]" SITE "46" ;
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LOCATE COMP "MAin[3]" SITE "47" ;
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LOCATE COMP "MAin[2]" SITE "37" ;
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LOCATE COMP "MAin[1]" SITE "38" ;
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LOCATE COMP "MAin[0]" SITE "23" ;
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FREQUENCY PORT "PHI2" 2.900000 MHz ;
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FREQUENCY PORT "nCCAS" 2.900000 MHz ;
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FREQUENCY PORT "nCRAS" 2.900000 MHz ;
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FREQUENCY PORT "RCLK" 62.500000 MHz ;
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SCHEMATIC END ;
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[ END DESIGN PREFS ]
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