9 lines
347 B
Verilog
9 lines
347 B
Verilog
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
|
/* Module Version: 1.2 */
|
|
/* Thu Sep 21 04:34:49 2023 */
|
|
|
|
/* parameterized module instance */
|
|
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
|
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
|
.wbc_ufm_irq( ));
|