36591 lines
1.3 MiB
36591 lines
1.3 MiB
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-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
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-- ldbanno -n VHDL -o LCMXO2_640HC_impl1_mapvho.vho -w -neg -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd
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-- Netlist created on Sat Aug 19 21:54:57 2023
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-- Netlist written on Sat Aug 19 21:55:00 2023
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-- Design is for device LCMXO2-640HC
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-- Design is for package TQFP100
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-- Design is for performance grade 4
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-- entity vmuxregsre
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity vmuxregsre is
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE;
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end vmuxregsre;
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architecture Structure of vmuxregsre is
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begin
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INST01: FL1P3DX
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generic map (GSR => "DISABLED")
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port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
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end Structure;
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-- entity vcc
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity vcc is
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port (PWR1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE;
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end vcc;
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architecture Structure of vcc is
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begin
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INST1: VHI
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port map (Z=>PWR1);
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end Structure;
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-- entity gnd
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity gnd is
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port (PWR0: out Std_logic);
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ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE;
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end gnd;
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architecture Structure of gnd is
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begin
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INST1: VLO
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port map (Z=>PWR0);
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end Structure;
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-- entity ccu2B0
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity ccu2B0 is
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE;
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end ccu2B0;
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architecture Structure of ccu2B0 is
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begin
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inst1: CCU2D
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generic map (INIT0 => X"000A", INIT1 => X"300A", INJECT1_0 => "NO",
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INJECT1_1 => "NO")
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port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
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C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
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end Structure;
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-- entity SLICE_0
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_0 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_0";
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI1_CLK : VitalDelayType := 0 ns;
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tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic;
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F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE;
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end SLICE_0;
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architecture Structure of SLICE_0 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A1_ipd : std_logic := 'X';
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signal DI1_ipd : std_logic := 'X';
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signal DI1_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal FCO_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal GNDI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component ccu2B0
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
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end component;
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begin
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FS_0: vmuxregsre
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port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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FS_cry_0_0: ccu2B0
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port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
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C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out,
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CO1=>FCO_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (A1_ipd, DI1_dly, CLK_dly, F1_out, Q1_out, FCO_out)
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE FCO_zd : std_logic := 'X';
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VARIABLE FCO_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_DI1_CLK : x01 := '0';
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VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => DI1_dly,
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TestSignalName => "DI1",
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TestDelay => tisd_DI1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI1_CLK_noedge_posedge,
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SetupLow => tsetup_DI1_CLK_noedge_posedge,
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HoldHigh => thold_DI1_CLK_noedge_posedge,
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HoldLow => thold_DI1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI1_CLK_TimingDatash,
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Violation => tviol_DI1_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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FCO_zd := FCO_out;
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
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Paths => (0 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_FCO,
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PathCondition => TRUE)),
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GlitchData => FCO_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity ccu20001
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity ccu20001 is
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE;
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end ccu20001;
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architecture Structure of ccu20001 is
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begin
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inst1: CCU2D
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generic map (INIT0 => X"5002", INIT1 => X"300A", INJECT1_0 => "NO",
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INJECT1_1 => "NO")
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port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
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C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
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end Structure;
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-- entity SLICE_1
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_1 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_1";
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
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FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE;
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end SLICE_1;
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architecture Structure of SLICE_1 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal A0_ipd : std_logic := 'X';
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signal DI0_ipd : std_logic := 'X';
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signal DI0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal FCI_ipd : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal GNDI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component ccu20001
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port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
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D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
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C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
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S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
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end component;
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begin
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FS_17: vmuxregsre
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port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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FS_s_0_17: ccu20001
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port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI,
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C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open,
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CO1=>open);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_DI0_CLK : x01 := '0';
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VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => DI0_dly,
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TestSignalName => "DI0",
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TestDelay => tisd_DI0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI0_CLK_noedge_posedge,
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SetupLow => tsetup_DI0_CLK_noedge_posedge,
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HoldHigh => thold_DI0_CLK_noedge_posedge,
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HoldLow => thold_DI0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI0_CLK_TimingDatash,
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Violation => tviol_DI0_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity ccu20002
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity ccu20002 is
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE;
|
|
|
|
end ccu20002;
|
|
|
|
architecture Structure of ccu20002 is
|
|
begin
|
|
inst1: CCU2D
|
|
generic map (INIT0 => X"300A", INIT1 => X"300A", INJECT1_0 => "NO",
|
|
INJECT1_1 => "NO")
|
|
port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1,
|
|
C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1);
|
|
end Structure;
|
|
|
|
-- entity SLICE_2
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_2 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_2";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE;
|
|
|
|
end SLICE_2;
|
|
|
|
architecture Structure of SLICE_2 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_16: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_15: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_15: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_3
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_3 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_3";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE;
|
|
|
|
end SLICE_3;
|
|
|
|
architecture Structure of SLICE_3 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_14: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_13: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_13: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_4
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_4 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_4";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE;
|
|
|
|
end SLICE_4;
|
|
|
|
architecture Structure of SLICE_4 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_12: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_11: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_11: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_5
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_5 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_5";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE;
|
|
|
|
end SLICE_5;
|
|
|
|
architecture Structure of SLICE_5 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_10: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_9: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_9: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_6
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_6 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_6";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE;
|
|
|
|
end SLICE_6;
|
|
|
|
architecture Structure of SLICE_6 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_8: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_7: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_7: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_7
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_7 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_7";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE;
|
|
|
|
end SLICE_7;
|
|
|
|
architecture Structure of SLICE_7 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_6: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_5: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_5: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_8
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_8 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_8";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE;
|
|
|
|
end SLICE_8;
|
|
|
|
architecture Structure of SLICE_8 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_4: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_3: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_9
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_9 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_9";
|
|
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_FCI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE;
|
|
|
|
end SLICE_9;
|
|
|
|
architecture Structure of SLICE_9 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal FCI_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
signal FCO_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component ccu20002
|
|
port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic;
|
|
D0: in Std_logic; A1: in Std_logic; B1: in Std_logic;
|
|
C1: in Std_logic; D1: in Std_logic; CI: in Std_logic;
|
|
S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FS_1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
FS_cry_0_1: ccu20002
|
|
port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI,
|
|
C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out,
|
|
CO1=>FCO_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
VitalWireDelay(FCI_ipd, FCI, tipd_FCI);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly,
|
|
FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE FCO_zd : std_logic := 'X';
|
|
VARIABLE FCO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
FCO_zd := FCO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd,
|
|
Paths => (0 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_FCO,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_FCO,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => FCI_ipd'last_event,
|
|
PathDelay => tpd_FCI_FCO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => FCO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut4
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut4 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE;
|
|
|
|
end lut4;
|
|
|
|
architecture Structure of lut4 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40003
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40003 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE;
|
|
|
|
end lut40003;
|
|
|
|
architecture Structure of lut40003 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"00F2")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity inverter
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity inverter is
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE;
|
|
|
|
end inverter;
|
|
|
|
architecture Structure of inverter is
|
|
begin
|
|
INST1: INV
|
|
port map (A=>I, Z=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_10
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_10 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_10";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE;
|
|
|
|
end SLICE_10;
|
|
|
|
architecture Structure of SLICE_10 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40003
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable17: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
ADSubmitted_r: lut40003
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
ADSubmitted: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40004
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40004 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE;
|
|
|
|
end lut40004;
|
|
|
|
architecture Structure of lut40004 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"F2F2")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_11
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_11 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_11";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_11 : ENTITY IS TRUE;
|
|
|
|
end SLICE_11;
|
|
|
|
architecture Structure of SLICE_11 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40004
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable16: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
C1Submitted_s: lut40004
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
C1Submitted: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40005
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40005 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE;
|
|
|
|
end lut40005;
|
|
|
|
architecture Structure of lut40005 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"5555")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_12
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_12 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_12";
|
|
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_12 : ENTITY IS TRUE;
|
|
|
|
end SLICE_12;
|
|
|
|
architecture Structure of SLICE_12 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nCCAS_pad_RNISUR8: lut40005
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CASr2: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CASr: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out,
|
|
Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40006
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40006 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE;
|
|
|
|
end lut40006;
|
|
|
|
architecture Structure of lut40006 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0800")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40007
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40007 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE;
|
|
|
|
end lut40007;
|
|
|
|
architecture Structure of lut40007 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"DDDD")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity vmuxregsre0008
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity vmuxregsre0008 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF vmuxregsre0008 : ENTITY IS TRUE;
|
|
|
|
end vmuxregsre0008;
|
|
|
|
architecture Structure of vmuxregsre0008 is
|
|
begin
|
|
INST01: FL1P3IY
|
|
generic map (GSR => "DISABLED")
|
|
port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity SLICE_16
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_16 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_16";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE;
|
|
|
|
end SLICE_16;
|
|
|
|
architecture Structure of SLICE_16 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40006
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40007
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0008
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Ready_0_sqmuxa_0_a3_2: lut40006
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
S_RNO_0: lut40007
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
S_0: vmuxregsre0008
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40009
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40009 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE;
|
|
|
|
end lut40009;
|
|
|
|
architecture Structure of lut40009 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"EEEE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40010
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40010 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE;
|
|
|
|
end lut40010;
|
|
|
|
architecture Structure of lut40010 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"AC8C")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity selmux2
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity selmux2 is
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE;
|
|
|
|
end selmux2;
|
|
|
|
architecture Structure of selmux2 is
|
|
begin
|
|
INST1: MUX21
|
|
port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_17
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_17 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_17";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
OFX0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_17 : ENTITY IS TRUE;
|
|
|
|
end SLICE_17;
|
|
|
|
architecture Structure of SLICE_17 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal OFX0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal SLICE_17_SLICE_17_K1_H1: Std_logic;
|
|
signal SLICE_17_CmdEnable_s_GATE_H0: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40009
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40010
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component selmux2
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
SLICE_17_K1: lut40009
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI,
|
|
Z=>SLICE_17_SLICE_17_K1_H1);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdEnable_s_GATE: lut40010
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd,
|
|
Z=>SLICE_17_CmdEnable_s_GATE_H0);
|
|
CmdEnable: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
SLICE_17_K0K1MUX: selmux2
|
|
port map (D0=>SLICE_17_CmdEnable_s_GATE_H0, D1=>SLICE_17_SLICE_17_K1_H1,
|
|
SD=>M0_ipd, Z=>OFX0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out)
|
|
VARIABLE OFX0_zd : std_logic := 'X';
|
|
VARIABLE OFX0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
OFX0_zd := OFX0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_OFX0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_OFX0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_OFX0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_OFX0,
|
|
PathCondition => TRUE),
|
|
4 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_OFX0,
|
|
PathCondition => TRUE),
|
|
5 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_OFX0,
|
|
PathCondition => TRUE),
|
|
6 => (InputChangeTime => M0_ipd'last_event,
|
|
PathDelay => tpd_M0_OFX0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => OFX0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40011
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40011 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE;
|
|
|
|
end lut40011;
|
|
|
|
architecture Structure of lut40011 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CACA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40012
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40012 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE;
|
|
|
|
end lut40012;
|
|
|
|
architecture Structure of lut40012 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"ACAC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_18
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_18 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_18";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE;
|
|
|
|
end SLICE_18;
|
|
|
|
architecture Structure of SLICE_18 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdLEDEN_4_0: lut40011
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdLEDEN_4_u: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
CmdLEDEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40013
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40013 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE;
|
|
|
|
end lut40013;
|
|
|
|
architecture Structure of lut40013 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"030A")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_20
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_20 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_20";
|
|
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE;
|
|
|
|
end SLICE_20;
|
|
|
|
architecture Structure of SLICE_20 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40013
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdUFMShift_3_u: lut40013
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdUFMShift: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly,
|
|
CLK_dly, F0_out, Q0_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_21
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_21 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_21";
|
|
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_21 : ENTITY IS TRUE;
|
|
|
|
end SLICE_21;
|
|
|
|
architecture Structure of SLICE_21 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40013
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdUFMShift_3_u_fast: lut40013
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdUFMShift_fast: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly,
|
|
CLK_dly, F0_out, Q0_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40014
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40014 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE;
|
|
|
|
end lut40014;
|
|
|
|
architecture Structure of lut40014 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4444")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40015
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40015 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE;
|
|
|
|
end lut40015;
|
|
|
|
architecture Structure of lut40015 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0C0A")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_22
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_22 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_22";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_22 : ENTITY IS TRUE;
|
|
|
|
end SLICE_22;
|
|
|
|
architecture Structure of SLICE_22 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40015
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdUFMWrite_2: lut40014
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdUFMWrite_3_u: lut40015
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdUFMWrite: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40016
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40016 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE;
|
|
|
|
end lut40016;
|
|
|
|
architecture Structure of lut40016 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0002")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40017
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40017 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE;
|
|
|
|
end lut40017;
|
|
|
|
architecture Structure of lut40017 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"A8A8")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_23
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_23 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_23";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE;
|
|
|
|
end SLICE_23;
|
|
|
|
architecture Structure of SLICE_23 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40016
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40017
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG11: lut40016
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
CmdValid_r: lut40017
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdValid: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40018
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40018 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE;
|
|
|
|
end lut40018;
|
|
|
|
architecture Structure of lut40018 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8080")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_24
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_24 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_24";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE;
|
|
|
|
end SLICE_24;
|
|
|
|
architecture Structure of SLICE_24 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40017
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG18: lut40018
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdValid_r_fast: lut40017
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
CmdValid_fast: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40019
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40019 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE;
|
|
|
|
end lut40019;
|
|
|
|
architecture Structure of lut40019 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3A3A")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40020
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40020 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE;
|
|
|
|
end lut40020;
|
|
|
|
architecture Structure of lut40020 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"E2E2")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_25
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_25 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_25";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE;
|
|
|
|
end SLICE_25;
|
|
|
|
architecture Structure of SLICE_25 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40019
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40020
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Cmdn8MEGEN_4_0: lut40019
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Cmdn8MEGEN_4_u: lut40020
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
Cmdn8MEGEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40021
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40021 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE;
|
|
|
|
end lut40021;
|
|
|
|
architecture Structure of lut40021 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"EEEE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_26
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_26 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_26";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE;
|
|
|
|
end SLICE_26;
|
|
|
|
architecture Structure of SLICE_26 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nCCAS_pad_RNI01SJ: lut40021
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nFWE_pad_RNI420B: lut40005
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
FWEr: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out,
|
|
Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40022
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40022 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE;
|
|
|
|
end lut40022;
|
|
|
|
architecture Structure of lut40022 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFF7")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40023
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40023 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE;
|
|
|
|
end lut40023;
|
|
|
|
architecture Structure of lut40023 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"A9A9")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_28
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_28 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_28";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_28 : ENTITY IS TRUE;
|
|
|
|
end SLICE_28;
|
|
|
|
architecture Structure of SLICE_28 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40022
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40023
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA10_0io_RNO: lut40022
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
IS_RNO_0: lut40023
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
IS_0: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40024
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40024 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE;
|
|
|
|
end lut40024;
|
|
|
|
architecture Structure of lut40024 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"7878")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40025
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40025 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE;
|
|
|
|
end lut40025;
|
|
|
|
architecture Structure of lut40025 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"6666")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_29
|
|
library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_29 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_29";
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI1_CLK : VitalDelayType := 0 ns;
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tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_CE_CLK : VitalDelayType := 0 ns;
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tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
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B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
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DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
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F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
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Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_29 : ENTITY IS TRUE;
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end SLICE_29;
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architecture Structure of SLICE_29 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal DI1_ipd : std_logic := 'X';
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signal DI1_dly : std_logic := 'X';
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signal DI0_ipd : std_logic := 'X';
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signal DI0_dly : std_logic := 'X';
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signal CE_ipd : std_logic := 'X';
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signal CE_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40024
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40025
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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IS_RNO_2: lut40024
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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IS_n1_0_x2: lut40025
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port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
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IS_2: vmuxregsre
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port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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IS_1: vmuxregsre
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port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
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VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
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VitalWireDelay(CE_ipd, CE, tipd_CE);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
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VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
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VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly,
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DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_DI1_CLK : x01 := '0';
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VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_DI0_CLK : x01 := '0';
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VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CE_CLK : x01 := '0';
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VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => DI1_dly,
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TestSignalName => "DI1",
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TestDelay => tisd_DI1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI1_CLK_noedge_posedge,
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SetupLow => tsetup_DI1_CLK_noedge_posedge,
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HoldHigh => thold_DI1_CLK_noedge_posedge,
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HoldLow => thold_DI1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI1_CLK_TimingDatash,
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Violation => tviol_DI1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => DI0_dly,
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TestSignalName => "DI0",
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TestDelay => tisd_DI0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_DI0_CLK_noedge_posedge,
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SetupLow => tsetup_DI0_CLK_noedge_posedge,
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HoldHigh => thold_DI0_CLK_noedge_posedge,
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HoldLow => thold_DI0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => DI0_CLK_TimingDatash,
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Violation => tviol_DI0_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => CE_dly,
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TestSignalName => "CE",
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TestDelay => tisd_CE_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_CE_CLK_noedge_posedge,
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SetupLow => tsetup_CE_CLK_noedge_posedge,
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HoldHigh => thold_CE_CLK_noedge_posedge,
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HoldLow => thold_CE_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => CE_CLK_TimingDatash,
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Violation => tviol_CE_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => C1_ipd'last_event,
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PathDelay => tpd_C1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => B1_ipd'last_event,
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PathDelay => tpd_B1_F1,
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PathCondition => TRUE),
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2 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity lut40026
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity lut40026 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE;
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end lut40026;
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architecture Structure of lut40026 is
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begin
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INST10: ROM16X1A
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generic map (initval => X"6AAA")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity SLICE_30
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_30 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_30";
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_CE_CLK : VitalDelayType := 0 ns;
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tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
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C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
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DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
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F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE;
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end SLICE_30;
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architecture Structure of SLICE_30 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal DI0_ipd : std_logic := 'X';
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signal DI0_dly : std_logic := 'X';
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signal CE_ipd : std_logic := 'X';
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signal CE_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40021
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
|
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component lut40026
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
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Z: out Std_logic);
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end component;
|
|
begin
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|
RA10_2_sqmuxa_0_o2: lut40021
|
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port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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IS_RNO_3: lut40026
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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|
IS_3: vmuxregsre
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port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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|
DRIVEVCC: vcc
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|
port map (PWR1=>VCCI);
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|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_31
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_31 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_31";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE;
|
|
|
|
end SLICE_31;
|
|
|
|
architecture Structure of SLICE_31 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
InitReady3_0_a3: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
InitReady_RNO: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
InitReady: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40027
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40027 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE;
|
|
|
|
end lut40027;
|
|
|
|
architecture Structure of lut40027 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"B8B8")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_32
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_32 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_32";
|
|
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE;
|
|
|
|
end SLICE_32;
|
|
|
|
architecture Structure of SLICE_32 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40027
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
LEDEN_6: lut40027
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
LEDEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly,
|
|
F0_out, Q0_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40028
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40028 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE;
|
|
|
|
end lut40028;
|
|
|
|
architecture Structure of lut40028 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FBFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_34
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_34 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_34";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE;
|
|
|
|
end SLICE_34;
|
|
|
|
architecture Structure of SLICE_34 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40005
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40028
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
LED_pad_RNO: lut40028
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RASr_RNO: lut40005
|
|
port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RASr2: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
RASr: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_posedge,
|
|
HoldHigh => thold_M1_CLK_noedge_posedge,
|
|
HoldLow => thold_M1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40029
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40029 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE;
|
|
|
|
end lut40029;
|
|
|
|
architecture Structure of lut40029 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1111")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_35
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_35 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_35";
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_M1_CLK : VitalDelayType := 0 ns;
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tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tisd_M0_CLK : VitalDelayType := 0 ns;
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tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
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B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
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M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
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Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE;
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end SLICE_35;
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architecture Structure of SLICE_35 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal M1_ipd : std_logic := 'X';
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signal M1_dly : std_logic := 'X';
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signal M0_ipd : std_logic := 'X';
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signal M0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal Q1_out : std_logic := 'X';
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signal GNDI: Std_logic;
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signal VCCI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40012
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40029
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1: lut40029
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port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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un9_RA_4: lut40012
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
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PHI2r2: vmuxregsre
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port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q1_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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RASr3: vmuxregsre
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port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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-- INPUT PATH DELAYs
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WireDelay : BLOCK
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BEGIN
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(M1_ipd, M1, tipd_M1);
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VitalWireDelay(M0_ipd, M0, tipd_M0);
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VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
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END BLOCK;
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-- Setup and Hold DELAYs
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SignalDelay : BLOCK
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BEGIN
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VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
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VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
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VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
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END BLOCK;
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VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly,
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M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
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VARIABLE F0_zd : std_logic := 'X';
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VARIABLE F0_GlitchData : VitalGlitchDataType;
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VARIABLE Q0_zd : std_logic := 'X';
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VARIABLE Q0_GlitchData : VitalGlitchDataType;
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VARIABLE F1_zd : std_logic := 'X';
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VARIABLE F1_GlitchData : VitalGlitchDataType;
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VARIABLE Q1_zd : std_logic := 'X';
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VARIABLE Q1_GlitchData : VitalGlitchDataType;
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VARIABLE tviol_M1_CLK : x01 := '0';
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VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_M0_CLK : x01 := '0';
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VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_CLK_CLK : x01 := '0';
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VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
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BEGIN
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IF (TimingChecksOn) THEN
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VitalSetupHoldCheck (
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TestSignal => M1_dly,
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TestSignalName => "M1",
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TestDelay => tisd_M1_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M1_CLK_noedge_posedge,
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SetupLow => tsetup_M1_CLK_noedge_posedge,
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HoldHigh => thold_M1_CLK_noedge_posedge,
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HoldLow => thold_M1_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M1_CLK_TimingDatash,
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Violation => tviol_M1_CLK,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => M0_dly,
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TestSignalName => "M0",
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TestDelay => tisd_M0_CLK,
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RefSignal => CLK_dly,
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RefSignalName => "CLK",
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RefDelay => ticd_CLK,
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SetupHigh => tsetup_M0_CLK_noedge_posedge,
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SetupLow => tsetup_M0_CLK_noedge_posedge,
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HoldHigh => thold_M0_CLK_noedge_posedge,
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HoldLow => thold_M0_CLK_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => M0_CLK_TimingDatash,
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Violation => tviol_M0_CLK,
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MsgSeverity => warning);
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VitalPeriodPulseCheck (
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TestSignal => CLK_ipd,
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TestSignalName => "CLK",
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Period => tperiod_CLK,
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PulseWidthHigh => tpw_CLK_posedge,
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PulseWidthLow => tpw_CLK_negedge,
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PeriodData => periodcheckinfo_CLK,
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Violation => tviol_CLK_CLK,
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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CheckEnabled => TRUE,
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MsgSeverity => warning);
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END IF;
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F0_zd := F0_out;
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Q0_zd := Q0_out;
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F1_zd := F1_out;
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Q1_zd := Q1_out;
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VitalPathDelay01 (
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OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
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Paths => (0 => (InputChangeTime => C0_ipd'last_event,
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PathDelay => tpd_C0_F0,
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PathCondition => TRUE),
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1 => (InputChangeTime => B0_ipd'last_event,
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PathDelay => tpd_B0_F0,
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PathCondition => TRUE),
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2 => (InputChangeTime => A0_ipd'last_event,
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PathDelay => tpd_A0_F0,
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PathCondition => TRUE)),
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GlitchData => F0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q0,
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PathCondition => TRUE)),
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GlitchData => Q0_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
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Paths => (0 => (InputChangeTime => B1_ipd'last_event,
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PathDelay => tpd_B1_F1,
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PathCondition => TRUE),
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1 => (InputChangeTime => A1_ipd'last_event,
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PathDelay => tpd_A1_F1,
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PathCondition => TRUE)),
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GlitchData => F1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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VitalPathDelay01 (
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OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
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Paths => (0 => (InputChangeTime => CLK_dly'last_event,
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PathDelay => tpd_CLK_Q1,
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PathCondition => TRUE)),
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GlitchData => Q1_GlitchData,
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Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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END PROCESS;
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end Structure;
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-- entity lut40030
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity lut40030 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE;
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end lut40030;
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architecture Structure of lut40030 is
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begin
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INST10: ROM16X1A
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generic map (initval => X"5072")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity lut40031
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity lut40031 is
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE;
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end lut40031;
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architecture Structure of lut40031 is
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begin
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INST10: ROM16X1A
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generic map (initval => X"DCCC")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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end Structure;
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-- entity SLICE_36
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library IEEE, vital2000, MACHXO2;
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use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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entity SLICE_36 is
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-- miscellaneous vital GENERICs
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GENERIC (
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TimingChecksOn : boolean := TRUE;
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XOn : boolean := FALSE;
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MsgOn : boolean := TRUE;
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InstancePath : string := "SLICE_36";
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tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
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tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
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ticd_CLK : VitalDelayType := 0 ns;
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tisd_DI0_CLK : VitalDelayType := 0 ns;
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tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
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tperiod_CLK : VitalDelayType := 0 ns;
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tpw_CLK_posedge : VitalDelayType := 0 ns;
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tpw_CLK_negedge : VitalDelayType := 0 ns);
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port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
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A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
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B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
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CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
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F1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE;
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end SLICE_36;
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architecture Structure of SLICE_36 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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signal D1_ipd : std_logic := 'X';
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal D0_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal DI0_ipd : std_logic := 'X';
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signal DI0_dly : std_logic := 'X';
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signal CLK_ipd : std_logic := 'X';
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signal CLK_dly : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal Q0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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signal VCCI: Std_logic;
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signal GNDI: Std_logic;
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component vmuxregsre
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port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
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SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
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Q: out Std_logic);
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end component;
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component vcc
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port (PWR1: out Std_logic);
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end component;
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component gnd
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port (PWR0: out Std_logic);
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end component;
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component lut40030
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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component lut40031
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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RCKEEN_8_u_RNO: lut40030
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
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RCKEEN_8_u: lut40031
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
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RCKEEN: vmuxregsre
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port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
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LSR=>GNDI, Q=>Q0_out);
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DRIVEVCC: vcc
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port map (PWR1=>VCCI);
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DRIVEGND: gnd
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port map (PWR0=>GNDI);
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|
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-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
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BEGIN
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VitalWireDelay(D1_ipd, D1, tipd_D1);
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(D0_ipd, D0, tipd_D0);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40032
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40032 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE;
|
|
|
|
end lut40032;
|
|
|
|
architecture Structure of lut40032 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40033
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40033 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE;
|
|
|
|
end lut40033;
|
|
|
|
architecture Structure of lut40033 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FE30")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_37
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_37 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_37";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE;
|
|
|
|
end SLICE_37;
|
|
|
|
architecture Structure of SLICE_37 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40032
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40033
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_Bank_1_4: lut40032
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
RCKE_2_0: lut40033
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
RCKE: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40034
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40034 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE;
|
|
|
|
end lut40034;
|
|
|
|
architecture Structure of lut40034 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"7F7F")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40035
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40035 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE;
|
|
|
|
end lut40035;
|
|
|
|
architecture Structure of lut40035 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"AEAA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_38
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_38 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_38";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_38 : ENTITY IS TRUE;
|
|
|
|
end SLICE_38;
|
|
|
|
architecture Structure of SLICE_38 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40034
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40035
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Ready_0_sqmuxa_0_o2: lut40034
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Ready_RNO: lut40035
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
Ready: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40036
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40036 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE;
|
|
|
|
end lut40036;
|
|
|
|
architecture Structure of lut40036 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0200")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_39
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_39 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_39";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_39 : ENTITY IS TRUE;
|
|
|
|
end SLICE_39;
|
|
|
|
architecture Structure of SLICE_39 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40036
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
Ready_0_sqmuxa_0_a3: lut40036
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
Ready_fast_RNO: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
Ready_fast: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40037
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40037 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE;
|
|
|
|
end lut40037;
|
|
|
|
architecture Structure of lut40037 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8888")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_40
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_40 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_40";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_40 : ENTITY IS TRUE;
|
|
|
|
end SLICE_40;
|
|
|
|
architecture Structure of SLICE_40 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RowAd_1: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RowAd_0: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RowA_1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
RowA_0: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_negedge,
|
|
HoldLow => thold_DI1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_41
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_41 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_41";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_41 : ENTITY IS TRUE;
|
|
|
|
end SLICE_41;
|
|
|
|
architecture Structure of SLICE_41 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RowAd_3: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RowAd_2: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RowA_3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
RowA_2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_negedge,
|
|
HoldLow => thold_DI1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40038
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40038 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE;
|
|
|
|
end lut40038;
|
|
|
|
architecture Structure of lut40038 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"BBBB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_42
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_42 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_42";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_42 : ENTITY IS TRUE;
|
|
|
|
end SLICE_42;
|
|
|
|
architecture Structure of SLICE_42 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RowAd_5: lut40038
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RowAd_4: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RowA_5: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
RowA_4: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_negedge,
|
|
HoldLow => thold_DI1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_43
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_43 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_43";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE;
|
|
|
|
end SLICE_43;
|
|
|
|
architecture Structure of SLICE_43 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RowAd_7: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RowAd_6: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RowA_7: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
RowA_6: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_negedge,
|
|
HoldLow => thold_DI1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_44
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_44 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_44";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE;
|
|
|
|
end SLICE_44;
|
|
|
|
architecture Structure of SLICE_44 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RowAd_9: lut40038
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RowAd_8: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
RowA_9: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
RowA_8: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly,
|
|
CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_negedge,
|
|
HoldLow => thold_DI1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40039
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40039 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE;
|
|
|
|
end lut40039;
|
|
|
|
architecture Structure of lut40039 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"5400")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_45
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_45 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_45";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE;
|
|
|
|
end SLICE_45;
|
|
|
|
architecture Structure of SLICE_45 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal LSR_NOTIN: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0008
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40039
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_5_u_i_0: lut40039
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
S_0_i_o2_1: lut40021
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
S_1: vmuxregsre0008
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_NOTIN, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
LSR_INVERTERIN: inverter
|
|
port map (I=>LSR_dly, Z=>LSR_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40040
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40040 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE;
|
|
|
|
end lut40040;
|
|
|
|
architecture Structure of lut40040 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"40C0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_46
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_46 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_46";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_46 : ENTITY IS TRUE;
|
|
|
|
end SLICE_46;
|
|
|
|
architecture Structure of SLICE_46 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40011
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40040
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG_3_u_0_bm: lut40040
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
XOR8MEG_3_u_0_GATE: lut40011
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
XOR8MEG: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_negedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_negedge,
|
|
HoldLow => thold_DI0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40041
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40041 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE;
|
|
|
|
end lut40041;
|
|
|
|
architecture Structure of lut40041 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0001")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_47
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_47 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_47";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_47 : ENTITY IS TRUE;
|
|
|
|
end SLICE_47;
|
|
|
|
architecture Structure of SLICE_47 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40027
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40041
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_rst10: lut40041
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
n8MEGEN_6: lut40027
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
n8MEGEN: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40042
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40042 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE;
|
|
|
|
end lut40042;
|
|
|
|
architecture Structure of lut40042 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40043
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40043 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE;
|
|
|
|
end lut40043;
|
|
|
|
architecture Structure of lut40043 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"DCEC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_48
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_48 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_48";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_48 : ENTITY IS TRUE;
|
|
|
|
end SLICE_48;
|
|
|
|
architecture Structure of SLICE_48 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0008
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40042
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40043
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRowColSel_0_0_a3_0: lut40042
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRowColSel_0_0: lut40043
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
nRowColSel: vmuxregsre0008
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40044
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40044 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE;
|
|
|
|
end lut40044;
|
|
|
|
architecture Structure of lut40044 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"B1A0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40045
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40045 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE;
|
|
|
|
end lut40045;
|
|
|
|
architecture Structure of lut40045 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"E4E4")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_49
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_49 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_49";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE;
|
|
|
|
end SLICE_49;
|
|
|
|
architecture Structure of SLICE_49 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40044
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40045
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_adr_5_1: lut40044
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_adr_5_0: lut40045
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_adr_1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
wb_adr_0: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out,
|
|
Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_50
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_50 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_50";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE;
|
|
|
|
end SLICE_50;
|
|
|
|
architecture Structure of SLICE_50 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_adr_5_3: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_adr_5_2: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
wb_adr_3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
wb_adr_2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly,
|
|
CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40046
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40046 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE;
|
|
|
|
end lut40046;
|
|
|
|
architecture Structure of lut40046 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"D8D8")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_51
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_51 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_51";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_51 : ENTITY IS TRUE;
|
|
|
|
end SLICE_51;
|
|
|
|
architecture Structure of SLICE_51 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40046
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_adr_5_5: lut40046
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_adr_5_4: lut40046
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
wb_adr_5: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
wb_adr_4: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_52
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_52 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_52";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_52 : ENTITY IS TRUE;
|
|
|
|
end SLICE_52;
|
|
|
|
architecture Structure of SLICE_52 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40046
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_adr_5_7: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_adr_5_6: lut40046
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
wb_adr_7: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
wb_adr_6: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI1_dly,
|
|
DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40047
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40047 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE;
|
|
|
|
end lut40047;
|
|
|
|
architecture Structure of lut40047 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0100")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40048
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40048 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE;
|
|
|
|
end lut40048;
|
|
|
|
architecture Structure of lut40048 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"ECCC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_53
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_53 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_53";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_53 : ENTITY IS TRUE;
|
|
|
|
end SLICE_53;
|
|
|
|
architecture Structure of SLICE_53 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0008
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40047
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40048
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_wb_cyc_stb_2_sqmuxa_i_a3_2: lut40047
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_wb_cyc_stb_1_sqmuxa_0: lut40048
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_cyc_stb: vmuxregsre0008
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40049
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40049 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE;
|
|
|
|
end lut40049;
|
|
|
|
architecture Structure of lut40049 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FEFA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40050
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40050 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE;
|
|
|
|
end lut40050;
|
|
|
|
architecture Structure of lut40050 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"EAC0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_54
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_54 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_54";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_54 : ENTITY IS TRUE;
|
|
|
|
end SLICE_54;
|
|
|
|
architecture Structure of SLICE_54 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40050
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_1: lut40049
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_0_iv_0_0: lut40050
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_dati_1: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_0: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out,
|
|
F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40051
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40051 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE;
|
|
|
|
end lut40051;
|
|
|
|
architecture Structure of lut40051 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFEA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40052
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40052 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE;
|
|
|
|
end lut40052;
|
|
|
|
architecture Structure of lut40052 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FEFC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_55
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_55 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_55";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_55 : ENTITY IS TRUE;
|
|
|
|
end SLICE_55;
|
|
|
|
architecture Structure of SLICE_55 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40051
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_3: lut40051
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_2: lut40052
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_dati_3: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_2: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out,
|
|
F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40053
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40053 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE;
|
|
|
|
end lut40053;
|
|
|
|
architecture Structure of lut40053 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFE4")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_56
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_56 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_56";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE;
|
|
|
|
end SLICE_56;
|
|
|
|
architecture Structure of SLICE_56 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40053
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_5: lut40052
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_4: lut40053
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_dati_5: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_4: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out,
|
|
F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40054
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40054 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE;
|
|
|
|
end lut40054;
|
|
|
|
architecture Structure of lut40054 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"ECEC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_57
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_57 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_57";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE;
|
|
|
|
end SLICE_57;
|
|
|
|
architecture Structure of SLICE_57 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI1_ipd : std_logic := 'X';
|
|
signal DI1_dly : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40049
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40054
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_7: lut40049
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_6: lut40054
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_7: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
wb_dati_6: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI1_ipd, DI1, tipd_DI1);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK);
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out,
|
|
Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI1_CLK : x01 := '0';
|
|
VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI1_dly,
|
|
TestSignalName => "DI1",
|
|
TestDelay => tisd_DI1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI1_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI1_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI1_CLK_noedge_posedge,
|
|
HoldLow => thold_DI1_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI1_CLK_TimingDatash,
|
|
Violation => tviol_DI1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40055
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40055 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE;
|
|
|
|
end lut40055;
|
|
|
|
architecture Structure of lut40055 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"7250")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_58
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_58 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_58";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE;
|
|
|
|
end SLICE_58;
|
|
|
|
architecture Structure of SLICE_58 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0008
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40055
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
FS_RNIVOOA_14: lut40018
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_reqe: lut40055
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_req: vmuxregsre0008
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40056
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40056 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE;
|
|
|
|
end lut40056;
|
|
|
|
architecture Structure of lut40056 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3B33")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40057
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40057 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE;
|
|
|
|
end lut40057;
|
|
|
|
architecture Structure of lut40057 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"7430")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_59
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_59 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_59";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE;
|
|
|
|
end SLICE_59;
|
|
|
|
architecture Structure of SLICE_59 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40056
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40057
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2r3_RNIS5A51: lut40056
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_rste: lut40057
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_rst: vmuxregsre
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, DI0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40058
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40058 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE;
|
|
|
|
end lut40058;
|
|
|
|
architecture Structure of lut40058 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"888F")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_60
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_60 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_60";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_LSR : VitalDelayType := 0 ns;
|
|
tpw_LSR_posedge : VitalDelayType := 0 ns;
|
|
tpw_LSR_negedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE;
|
|
|
|
end SLICE_60;
|
|
|
|
architecture Structure of SLICE_60 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal DI0_ipd : std_logic := 'X';
|
|
signal DI0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component vmuxregsre0008
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component lut40021
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40058
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_wb_adr_0_sqmuxa_2: lut40021
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_we_0: lut40058
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
wb_we: vmuxregsre0008
|
|
port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly,
|
|
LSR=>LSR_dly, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(DI0_ipd, DI0, tipd_DI0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI0_CLK : x01 := '0';
|
|
VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_LSR : x01 := '0';
|
|
VARIABLE periodcheckinfo_LSR : VitalPeriodDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI0_dly,
|
|
TestSignalName => "DI0",
|
|
TestDelay => tisd_DI0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI0_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI0_CLK_noedge_posedge,
|
|
HoldLow => thold_DI0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI0_CLK_TimingDatash,
|
|
Violation => tviol_DI0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_posedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_posedge,
|
|
HoldHigh => thold_CE_CLK_noedge_posedge,
|
|
HoldLow => thold_CE_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => LSR_ipd,
|
|
TestSignalName => "LSR",
|
|
Period => tperiod_LSR,
|
|
PulseWidthHigh => tpw_LSR_posedge,
|
|
PulseWidthLow => tpw_LSR_negedge,
|
|
PeriodData => periodcheckinfo_LSR,
|
|
Violation => tviol_LSR_LSR,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40059
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40059 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE;
|
|
|
|
end lut40059;
|
|
|
|
architecture Structure of lut40059 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFDF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40060
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40060 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE;
|
|
|
|
end lut40060;
|
|
|
|
architecture Structure of lut40060 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FBFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity wb_cyc_stb_RNO_SLICE_61
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity wb_cyc_stb_RNO_SLICE_61 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "wb_cyc_stb_RNO_SLICE_61";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF wb_cyc_stb_RNO_SLICE_61 : ENTITY IS TRUE;
|
|
|
|
end wb_cyc_stb_RNO_SLICE_61;
|
|
|
|
architecture Structure of wb_cyc_stb_RNO_SLICE_61 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal OFX0_out : std_logic := 'X';
|
|
|
|
signal wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component selmux2
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40059
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40060
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_cyc_stb_RNO_SLICE_61_K1: lut40059
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd,
|
|
Z=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1);
|
|
wb_cyc_stb_RNO_GATE: lut40060
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI,
|
|
Z=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_cyc_stb_RNO_SLICE_61_K0K1MUX: selmux2
|
|
port map (D0=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_GATE_H0,
|
|
D1=>wb_cyc_stb_RNO_SLICE_61_wb_cyc_stb_RNO_SLICE_61_K1_H1,
|
|
SD=>M0_ipd, Z=>OFX0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M0_ipd, OFX0_out)
|
|
VARIABLE OFX0_zd : std_logic := 'X';
|
|
VARIABLE OFX0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
OFX0_zd := OFX0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_OFX0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_OFX0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_OFX0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_OFX0,
|
|
PathCondition => TRUE),
|
|
4 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_OFX0,
|
|
PathCondition => TRUE),
|
|
5 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_OFX0,
|
|
PathCondition => TRUE),
|
|
6 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_OFX0,
|
|
PathCondition => TRUE),
|
|
7 => (InputChangeTime => M0_ipd'last_event,
|
|
PathDelay => tpd_M0_OFX0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => OFX0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40061
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40061 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE;
|
|
|
|
end lut40061;
|
|
|
|
architecture Structure of lut40061 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"B8F0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_62
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_62 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_62";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE;
|
|
|
|
end SLICE_62;
|
|
|
|
architecture Structure of SLICE_62 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40032
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40061
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdValid_fast_RNITQBM1: lut40061
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
ufmefb_EFBInst_0_RNI9PBJ: lut40032
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40062
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40062 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE;
|
|
|
|
end lut40062;
|
|
|
|
architecture Structure of lut40062 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0BFB")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_63
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_63 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_63";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE;
|
|
|
|
end SLICE_63;
|
|
|
|
architecture Structure of SLICE_63 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40022
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40062
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
IS_0_sqmuxa_0_o2_0: lut40022
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_nRCAS_6_sqmuxa_i_0: lut40062
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40063
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40063 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE;
|
|
|
|
end lut40063;
|
|
|
|
architecture Structure of lut40063 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"F1FC")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40064
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40064 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE;
|
|
|
|
end lut40064;
|
|
|
|
architecture Structure of lut40064 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"2000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_64
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_64 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_64";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE;
|
|
|
|
end SLICE_64;
|
|
|
|
architecture Structure of SLICE_64 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40063
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40064
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_0io_RNO: lut40063
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCAS_0_sqmuxa_1_0_a3: lut40064
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40065
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40065 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE;
|
|
|
|
end lut40065;
|
|
|
|
architecture Structure of lut40065 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1108")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40066
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40066 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE;
|
|
|
|
end lut40066;
|
|
|
|
architecture Structure of lut40066 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"2A2B")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_65
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_65 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_65";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE;
|
|
|
|
end SLICE_65;
|
|
|
|
architecture Structure of SLICE_65 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40065
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40066
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_40_1_0: lut40065
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_FS_40_1_0_1: lut40066
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40067
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40067 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE;
|
|
|
|
end lut40067;
|
|
|
|
architecture Structure of lut40067 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1313")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40068
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40068 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE;
|
|
|
|
end lut40068;
|
|
|
|
architecture Structure of lut40068 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1303")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_66
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_66 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_66";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE;
|
|
|
|
end SLICE_66;
|
|
|
|
architecture Structure of SLICE_66 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40067
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40068
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_0io_RNO_0: lut40067
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRCAS_0io_RNO: lut40068
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40069
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40069 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE;
|
|
|
|
end lut40069;
|
|
|
|
architecture Structure of lut40069 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0080")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40070
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40070 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE;
|
|
|
|
end lut40070;
|
|
|
|
architecture Structure of lut40070 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"EAEA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_67
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_67 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_67";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE;
|
|
|
|
end SLICE_67;
|
|
|
|
architecture Structure of SLICE_67 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40069
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40070
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_1: lut40069
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_o3_2: lut40070
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40071
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40071 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE;
|
|
|
|
end lut40071;
|
|
|
|
architecture Structure of lut40071 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"5252")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40072
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40072 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE;
|
|
|
|
end lut40072;
|
|
|
|
architecture Structure of lut40072 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0004")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_68
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_68 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_68";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE;
|
|
|
|
end SLICE_68;
|
|
|
|
architecture Structure of SLICE_68 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40071
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40072
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_0io_RNO_1: lut40071
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRWE_0io_RNO_4: lut40072
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40073
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40073 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE;
|
|
|
|
end lut40073;
|
|
|
|
architecture Structure of lut40073 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"BFBF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40074
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40074 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE;
|
|
|
|
end lut40074;
|
|
|
|
architecture Structure of lut40074 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0202")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_69
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_69 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_69";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE;
|
|
|
|
end SLICE_69;
|
|
|
|
architecture Structure of SLICE_69 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40073
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40074
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_0io_RNO_3: lut40073
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
S_RNICVV51_0: lut40074
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40075
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40075 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE;
|
|
|
|
end lut40075;
|
|
|
|
architecture Structure of lut40075 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4040")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_70
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_70 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_70";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE;
|
|
|
|
end SLICE_70;
|
|
|
|
architecture Structure of SLICE_70 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40075
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_4: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_a3_RNO_4: lut40075
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40076
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40076 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE;
|
|
|
|
end lut40076;
|
|
|
|
architecture Structure of lut40076 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0090")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_71
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_71 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_71";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_71 : ENTITY IS TRUE;
|
|
|
|
end SLICE_71;
|
|
|
|
architecture Structure of SLICE_71 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40076
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_we113_i_a2: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_RNO_7: lut40076
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40077
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40077 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE;
|
|
|
|
end lut40077;
|
|
|
|
architecture Structure of lut40077 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"B000")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_72
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_72 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_72";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE;
|
|
|
|
end SLICE_72;
|
|
|
|
architecture Structure of SLICE_72 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40016
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40077
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_2: lut40077
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
FS_RNI3V8E_9: lut40016
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_73
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_73 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_73";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CE : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_CE_CLK : VitalDelayType := 0 ns;
|
|
tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE;
|
|
|
|
end SLICE_73;
|
|
|
|
architecture Structure of SLICE_73 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CE_ipd : std_logic := 'X';
|
|
signal CE_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40006
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG14: lut40006
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
CmdUFMData_RNO: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CmdUFMData: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CE_ipd, CE, tipd_CE);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CE_CLK : x01 := '0';
|
|
VARIABLE CE_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => CE_dly,
|
|
TestSignalName => "CE",
|
|
TestDelay => tisd_CE_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_CE_CLK_noedge_negedge,
|
|
SetupLow => tsetup_CE_CLK_noedge_negedge,
|
|
HoldHigh => thold_CE_CLK_noedge_negedge,
|
|
HoldLow => thold_CE_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => CE_CLK_TimingDatash,
|
|
Violation => tviol_CE_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_74
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_74 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_74";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE;
|
|
|
|
end SLICE_74;
|
|
|
|
architecture Structure of SLICE_74 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40042
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_6: lut40042
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_1_6: lut40052
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40078
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40078 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE;
|
|
|
|
end lut40078;
|
|
|
|
architecture Structure of lut40078 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0404")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40079
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40079 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE;
|
|
|
|
end lut40079;
|
|
|
|
architecture Structure of lut40079 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"ECA0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_75
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_75 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_75";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE;
|
|
|
|
end SLICE_75;
|
|
|
|
architecture Structure of SLICE_75 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40078
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40079
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a2_0_3: lut40078
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_0_3: lut40079
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_76
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_76 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_76";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE;
|
|
|
|
end SLICE_76;
|
|
|
|
architecture Structure of SLICE_76 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40047
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_adr_cnst_sn_m2_0_a3: lut40047
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_RNO_4: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40080
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40080 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE;
|
|
|
|
end lut40080;
|
|
|
|
architecture Structure of lut40080 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FEFE")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40081
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40081 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE;
|
|
|
|
end lut40081;
|
|
|
|
architecture Structure of lut40081 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FF32")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_77
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_77 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_77";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE;
|
|
|
|
end SLICE_77;
|
|
|
|
architecture Structure of SLICE_77 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40080
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40081
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_nRCAS_6_sqmuxa_i_o2: lut40080
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
nRRAS_5_u_i: lut40081
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40082
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40082 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE;
|
|
|
|
end lut40082;
|
|
|
|
architecture Structure of lut40082 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"D3D3")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_78
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_78 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_78";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE;
|
|
|
|
end SLICE_78;
|
|
|
|
architecture Structure of SLICE_78 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40082
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_m3_7: lut40082
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_a3_7: lut40018
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_79
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_79 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_79";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE;
|
|
|
|
end SLICE_79;
|
|
|
|
architecture Structure of SLICE_79 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40079
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_2_0_1: lut40018
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_0_1: lut40079
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40083
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40083 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE;
|
|
|
|
end lut40083;
|
|
|
|
architecture Structure of lut40083 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"EEEA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_80
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_80 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_80";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE;
|
|
|
|
end SLICE_80;
|
|
|
|
architecture Structure of SLICE_80 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40042
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40083
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_1_1_4: lut40042
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_1_4: lut40083
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_81
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_81 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_81";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE;
|
|
|
|
end SLICE_81;
|
|
|
|
architecture Structure of SLICE_81 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40042
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40052
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_3_7: lut40042
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_1_7: lut40052
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40084
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40084 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE;
|
|
|
|
end lut40084;
|
|
|
|
architecture Structure of lut40084 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8060")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_82
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_82 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_82";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE;
|
|
|
|
end SLICE_82;
|
|
|
|
architecture Structure of SLICE_82 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40029
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40084
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_we95_0_0: lut40029
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_wb_we95_1: lut40084
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40085
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40085 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE;
|
|
|
|
end lut40085;
|
|
|
|
architecture Structure of lut40085 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0101")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_83
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_83 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_83";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE;
|
|
|
|
end SLICE_83;
|
|
|
|
architecture Structure of SLICE_83 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40077
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40085
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a2_7: lut40085
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_a3_1_7: lut40077
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40086
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40086 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE;
|
|
|
|
end lut40086;
|
|
|
|
architecture Structure of lut40086 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"1010")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_84
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_84 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_84";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE;
|
|
|
|
end SLICE_84;
|
|
|
|
architecture Structure of SLICE_84 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40016
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40086
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_29: lut40016
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_adr_cnst_sn_m4_32: lut40086
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40087
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40087 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE;
|
|
|
|
end lut40087;
|
|
|
|
architecture Structure of lut40087 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"9090")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40088
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40088 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE;
|
|
|
|
end lut40088;
|
|
|
|
architecture Structure of lut40088 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"F6F0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_85
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_85 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_85";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE;
|
|
|
|
end SLICE_85;
|
|
|
|
architecture Structure of SLICE_85 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40087
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40088
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_adr_cnst_0_0: lut40087
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_FS_40_1_1_1: lut40088
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40089
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40089 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE;
|
|
|
|
end lut40089;
|
|
|
|
architecture Structure of lut40089 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"FFB1")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_86
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_86 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_86";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE;
|
|
|
|
end SLICE_86;
|
|
|
|
architecture Structure of SLICE_86 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40089
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_40_1_o6: lut40089
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_FS_40_1_a6: lut40018
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40090
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40090 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE;
|
|
|
|
end lut40090;
|
|
|
|
architecture Structure of lut40090 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"7777")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40091
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40091 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE;
|
|
|
|
end lut40091;
|
|
|
|
architecture Structure of lut40091 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8040")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_87
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_87 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_87";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE;
|
|
|
|
end SLICE_87;
|
|
|
|
architecture Structure of SLICE_87 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40090
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40091
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_21_1_i: lut40090
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_we95: lut40091
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40092
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40092 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE;
|
|
|
|
end lut40092;
|
|
|
|
architecture Structure of lut40092 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"3AFA")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40093
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40093 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE;
|
|
|
|
end lut40093;
|
|
|
|
architecture Structure of lut40093 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"200F")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_88
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_88 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_88";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE;
|
|
|
|
end SLICE_88;
|
|
|
|
architecture Structure of SLICE_88 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40092
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40093
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_0io_RNO: lut40092
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRCAS_r_i_a3_1_1_tz: lut40093
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_89
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_89 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_89";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE;
|
|
|
|
end SLICE_89;
|
|
|
|
architecture Structure of SLICE_89 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40007
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40032
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_wb_cyc_stb_2_sqmuxa_i_o3: lut40007
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_wb_cyc_stb_2_sqmuxa_i_a3: lut40032
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40094
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40094 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE;
|
|
|
|
end lut40094;
|
|
|
|
architecture Structure of lut40094 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"CCC8")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_90
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_90 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_90";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE;
|
|
|
|
end SLICE_90;
|
|
|
|
architecture Structure of SLICE_90 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40094
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_CMDWR: lut40094
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
C1WR_7: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40095
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40095 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE;
|
|
|
|
end lut40095;
|
|
|
|
architecture Structure of lut40095 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"E0E0")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_91
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_91 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_91";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE;
|
|
|
|
end SLICE_91;
|
|
|
|
architecture Structure of SLICE_91 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40095
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_ADWR: lut40095
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
ADWR_7: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40096
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40096 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE;
|
|
|
|
end lut40096;
|
|
|
|
architecture Structure of lut40096 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0020")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_92
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_92 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_92";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE;
|
|
|
|
end SLICE_92;
|
|
|
|
architecture Structure of SLICE_92 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40096
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
C1WR_0: lut40018
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
C1WR_2: lut40096
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40097
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40097 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE;
|
|
|
|
end lut40097;
|
|
|
|
architecture Structure of lut40097 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"BBBF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_93
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_93 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_93";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE;
|
|
|
|
end SLICE_93;
|
|
|
|
architecture Structure of SLICE_93 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40073
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40097
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_wb_adr_0_sqmuxa_3: lut40073
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_we113_i_0: lut40097
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_94
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_94 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_94";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE;
|
|
|
|
end SLICE_94;
|
|
|
|
architecture Structure of SLICE_94 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_Bank_1_3: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_Bank_1: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_95
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_95 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_95";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE;
|
|
|
|
end SLICE_95;
|
|
|
|
architecture Structure of SLICE_95 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40032
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_PHI2r3_0: lut40014
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_wb_cyc_stb_1_sqmuxa_0_a3: lut40032
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_96
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_96 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_96";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE;
|
|
|
|
end SLICE_96;
|
|
|
|
architecture Structure of SLICE_96 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40018
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40085
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_wb_cyc_stb_2_sqmuxa_i_a3_1: lut40085
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un1_wb_cyc_stb_1_sqmuxa_0_a3_0_2: lut40018
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40098
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40098 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE;
|
|
|
|
end lut40098;
|
|
|
|
architecture Structure of lut40098 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"80FF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_97
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_97 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_97";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE;
|
|
|
|
end SLICE_97;
|
|
|
|
architecture Structure of SLICE_97 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40098
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2r3_RNIFT0I: lut40014
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdUFMShift_fast_RNIG9JD1: lut40098
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_98
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_98 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_98";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE;
|
|
|
|
end SLICE_98;
|
|
|
|
architecture Structure of SLICE_98 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40064
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40075
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_0io_RNO_2: lut40064
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
nRWE_0io_RNO_0: lut40075
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40099
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40099 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE;
|
|
|
|
end lut40099;
|
|
|
|
architecture Structure of lut40099 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8004")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_99
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_99 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_99";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE;
|
|
|
|
end SLICE_99;
|
|
|
|
architecture Structure of SLICE_99 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40099
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_0_0_0_1: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_a3_0_0_3: lut40099
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40100
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40100 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE;
|
|
|
|
end lut40100;
|
|
|
|
architecture Structure of lut40100 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4042")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40101
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40101 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE;
|
|
|
|
end lut40101;
|
|
|
|
architecture Structure of lut40101 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0810")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_100
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_100 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_100";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE;
|
|
|
|
end SLICE_100;
|
|
|
|
architecture Structure of SLICE_100 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40100
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40101
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_40_1_1_tz: lut40100
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
wb_dati_5_1_iv_0_o3_1: lut40101
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_101
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_101 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_101";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE;
|
|
|
|
end SLICE_101;
|
|
|
|
architecture Structure of SLICE_101 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40041
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40064
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable17_5: lut40064
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_Din_2: lut40041
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_102
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_102 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_102";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE;
|
|
|
|
end SLICE_102;
|
|
|
|
architecture Structure of SLICE_102 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40074
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
InitReady3_0_a3_2: lut4
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
un1_FS_11: lut40074
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40102
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40102 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE;
|
|
|
|
end lut40102;
|
|
|
|
architecture Structure of lut40102 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"8282")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_103
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_103 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_103";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE;
|
|
|
|
end SLICE_103;
|
|
|
|
architecture Structure of SLICE_103 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40102
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a3_0_0_6: lut40102
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_a3_3_0_7: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_104
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_104 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_104";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE;
|
|
|
|
end SLICE_104;
|
|
|
|
architecture Structure of SLICE_104 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
component lut40036
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40096
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
CmdEnable16_4: lut40036
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
CmdEnable17_4: lut40096
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd,
|
|
B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40103
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40103 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE;
|
|
|
|
end lut40103;
|
|
|
|
architecture Structure of lut40103 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0808")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity lut40104
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40104 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE;
|
|
|
|
end lut40104;
|
|
|
|
architecture Structure of lut40104 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"0008")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_105
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_105 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_105";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M1_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE;
|
|
|
|
end SLICE_105;
|
|
|
|
architecture Structure of SLICE_105 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M1_ipd : std_logic := 'X';
|
|
signal M1_dly : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
signal Q1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40103
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40104
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
ADWR_4: lut40103
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CMDWR_2: lut40104
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CBR_fast: vmuxregsre
|
|
port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q1_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
CBR: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M1_ipd, M1, tipd_M1);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK);
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q1_zd : std_logic := 'X';
|
|
VARIABLE Q1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M1_CLK : x01 := '0';
|
|
VARIABLE M1_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M1_dly,
|
|
TestSignalName => "M1",
|
|
TestDelay => tisd_M1_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M1_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M1_CLK_noedge_negedge,
|
|
HoldHigh => thold_M1_CLK_noedge_negedge,
|
|
HoldLow => thold_M1_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M1_CLK_TimingDatash,
|
|
Violation => tviol_M1_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
Q1_zd := Q1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_106
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_106 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_106";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE;
|
|
|
|
end SLICE_106;
|
|
|
|
architecture Structure of SLICE_106 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40047
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
XOR8MEG9_1: lut40014
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
CmdEnable16_5: lut40047
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
CASr3: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_107
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_107 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_107";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_107 : ENTITY IS TRUE;
|
|
|
|
end SLICE_107;
|
|
|
|
architecture Structure of SLICE_107 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40038
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQMH: lut40038
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_9: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40105
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40105 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40105 : ENTITY IS TRUE;
|
|
|
|
end lut40105;
|
|
|
|
architecture Structure of lut40105 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"5051")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_108
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_108 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_108";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_108 : ENTITY IS TRUE;
|
|
|
|
end SLICE_108;
|
|
|
|
architecture Structure of SLICE_108 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component lut40029
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40105
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_5_u_i_0_RNILD5I: lut40105
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
IS_0_sqmuxa_0_o2_0_RNIS63D: lut40029
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
FWEr_fast: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
M0_dly, CLK_dly, F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_negedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_negedge,
|
|
HoldHigh => thold_M0_CLK_noedge_negedge,
|
|
HoldLow => thold_M0_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_109
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_109 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_109";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_109 : ENTITY IS TRUE;
|
|
|
|
end SLICE_109;
|
|
|
|
architecture Structure of SLICE_109 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40014
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
wb_dati_5_1_iv_0_a2_4: lut40014
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_1_iv_0_a2_0_4: lut40014
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40106
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40106 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE;
|
|
|
|
end lut40106;
|
|
|
|
architecture Structure of lut40106 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"4800")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_110
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_110 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_110";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_110 : ENTITY IS TRUE;
|
|
|
|
end SLICE_110;
|
|
|
|
architecture Structure of SLICE_110 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40090
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40106
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un1_FS_22_1_i: lut40090
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
wb_dati_5_0_iv_0_a3_1_0: lut40106
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_111
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_111 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_111";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_111 : ENTITY IS TRUE;
|
|
|
|
end SLICE_111;
|
|
|
|
architecture Structure of SLICE_111 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut4
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_7: lut40012
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
ADWR_5: lut4
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_112
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_112 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_112";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_112 : ENTITY IS TRUE;
|
|
|
|
end SLICE_112;
|
|
|
|
architecture Structure of SLICE_112 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40090
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQML: lut40090
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_0: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out,
|
|
F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_113
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_113 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_113";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_113 : ENTITY IS TRUE;
|
|
|
|
end SLICE_113;
|
|
|
|
architecture Structure of SLICE_113 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_8: lut40012
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_1: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_114
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_114 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_114";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_114 : ENTITY IS TRUE;
|
|
|
|
end SLICE_114;
|
|
|
|
architecture Structure of SLICE_114 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40012
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
un9_RA_6: lut40012
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
un9_RA_2: lut40012
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_115
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
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use MACHXO2.COMPONENTS.ALL;
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|
|
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entity SLICE_115 is
|
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-- miscellaneous vital GENERICs
|
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GENERIC (
|
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TimingChecksOn : boolean := TRUE;
|
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XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
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InstancePath : string := "SLICE_115";
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|
|
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tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
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|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
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tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
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|
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port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
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C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
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F0: out Std_logic; F1: out Std_logic);
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ATTRIBUTE Vital_Level0 OF SLICE_115 : ENTITY IS TRUE;
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end SLICE_115;
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architecture Structure of SLICE_115 is
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ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
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|
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signal C1_ipd : std_logic := 'X';
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signal B1_ipd : std_logic := 'X';
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signal A1_ipd : std_logic := 'X';
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signal C0_ipd : std_logic := 'X';
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signal B0_ipd : std_logic := 'X';
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signal A0_ipd : std_logic := 'X';
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signal F0_out : std_logic := 'X';
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signal F1_out : std_logic := 'X';
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|
|
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signal GNDI: Std_logic;
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component gnd
|
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port (PWR0: out Std_logic);
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end component;
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component lut40012
|
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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end component;
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begin
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un9_RA_5: lut40012
|
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port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
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DRIVEGND: gnd
|
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port map (PWR0=>GNDI);
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un9_RA_3: lut40012
|
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port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out);
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|
|
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-- INPUT PATH DELAYs
|
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WireDelay : BLOCK
|
|
BEGIN
|
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VitalWireDelay(C1_ipd, C1, tipd_C1);
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VitalWireDelay(B1_ipd, B1, tipd_B1);
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VitalWireDelay(A1_ipd, A1, tipd_A1);
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VitalWireDelay(C0_ipd, C0, tipd_C0);
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VitalWireDelay(B0_ipd, B0, tipd_B0);
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VitalWireDelay(A0_ipd, A0, tipd_A0);
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END BLOCK;
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|
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VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
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|
VARIABLE F0_GlitchData : VitalGlitchDataType;
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|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
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|
|
|
|
|
BEGIN
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|
|
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IF (TimingChecksOn) THEN
|
|
|
|
END IF;
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|
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F0_zd := F0_out;
|
|
F1_zd := F1_out;
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|
|
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VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
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|
|
|
END PROCESS;
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|
|
|
end Structure;
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|
|
|
-- entity lut40107
|
|
library IEEE, vital2000, MACHXO2;
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|
use IEEE.STD_LOGIC_1164.all;
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|
use vital2000.vital_timing.all;
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|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40107 is
|
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
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Z: out Std_logic);
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|
|
|
ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE;
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|
|
|
end lut40107;
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|
|
|
architecture Structure of lut40107 is
|
|
begin
|
|
INST10: ROM16X1A
|
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generic map (initval => X"C048")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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|
end Structure;
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|
|
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-- entity lut40108
|
|
library IEEE, vital2000, MACHXO2;
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|
use IEEE.STD_LOGIC_1164.all;
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use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40108 is
|
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port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
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|
|
|
ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE;
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|
|
|
end lut40108;
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|
|
|
architecture Structure of lut40108 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"2222")
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port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
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|
end Structure;
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|
|
|
-- entity SLICE_116
|
|
library IEEE, vital2000, MACHXO2;
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|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_116 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_116";
|
|
|
|
tipd_D1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_116 : ENTITY IS TRUE;
|
|
|
|
end SLICE_116;
|
|
|
|
architecture Structure of SLICE_116 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal D1_ipd : std_logic := 'X';
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40107
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40108
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA11d: lut40107
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out);
|
|
XOR8MEG14_1: lut40108
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(D1_ipd, D1, tipd_D1);
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd,
|
|
F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => D1_ipd'last_event,
|
|
PathDelay => tpd_D1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity lut40109
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity lut40109 is
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE;
|
|
|
|
end lut40109;
|
|
|
|
architecture Structure of lut40109 is
|
|
begin
|
|
INST10: ROM16X1A
|
|
generic map (initval => X"70CF")
|
|
port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z);
|
|
end Structure;
|
|
|
|
-- entity SLICE_117
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_117 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_117";
|
|
|
|
tipd_C1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_D0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_C0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_117 : ENTITY IS TRUE;
|
|
|
|
end SLICE_117;
|
|
|
|
architecture Structure of SLICE_117 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal C1_ipd : std_logic := 'X';
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal D0_ipd : std_logic := 'X';
|
|
signal C0_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40086
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
component lut40109
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_0io_RNO_0: lut40086
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RCKEEN_8_u_1_0: lut40109
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(C1_ipd, C1, tipd_C1);
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(D0_ipd, D0, tipd_D0);
|
|
VitalWireDelay(C0_ipd, C0, tipd_C0);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd,
|
|
A0_ipd, F0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => D0_ipd'last_event,
|
|
PathDelay => tpd_D0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => C0_ipd'last_event,
|
|
PathDelay => tpd_C0_F0,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
3 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => C1_ipd'last_event,
|
|
PathDelay => tpd_C1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
2 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity SLICE_118
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity SLICE_118 is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "SLICE_118";
|
|
|
|
tipd_B1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_B0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_A0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_M0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_M0_CLK : VitalDelayType := 0 ns;
|
|
tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF SLICE_118 : ENTITY IS TRUE;
|
|
|
|
end SLICE_118;
|
|
|
|
architecture Structure of SLICE_118 is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal B1_ipd : std_logic := 'X';
|
|
signal A1_ipd : std_logic := 'X';
|
|
signal B0_ipd : std_logic := 'X';
|
|
signal A0_ipd : std_logic := 'X';
|
|
signal M0_ipd : std_logic := 'X';
|
|
signal M0_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal F0_out : std_logic := 'X';
|
|
signal Q0_out : std_logic := 'X';
|
|
signal F1_out : std_logic := 'X';
|
|
|
|
signal GNDI: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component vmuxregsre
|
|
port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic;
|
|
SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic;
|
|
Q: out Std_logic);
|
|
end component;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component lut40037
|
|
port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic;
|
|
Z: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBAd_0: lut40037
|
|
port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
RBAd_1: lut40037
|
|
port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out);
|
|
PHI2r3: vmuxregsre
|
|
port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly,
|
|
LSR=>GNDI, Q=>Q0_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(B1_ipd, B1, tipd_B1);
|
|
VitalWireDelay(A1_ipd, A1, tipd_A1);
|
|
VitalWireDelay(B0_ipd, B0, tipd_B0);
|
|
VitalWireDelay(A0_ipd, A0, tipd_A0);
|
|
VitalWireDelay(M0_ipd, M0, tipd_M0);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly,
|
|
F0_out, Q0_out, F1_out)
|
|
VARIABLE F0_zd : std_logic := 'X';
|
|
VARIABLE F0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE Q0_zd : std_logic := 'X';
|
|
VARIABLE Q0_GlitchData : VitalGlitchDataType;
|
|
VARIABLE F1_zd : std_logic := 'X';
|
|
VARIABLE F1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_M0_CLK : x01 := '0';
|
|
VARIABLE M0_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => M0_dly,
|
|
TestSignalName => "M0",
|
|
TestDelay => tisd_M0_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_M0_CLK_noedge_posedge,
|
|
SetupLow => tsetup_M0_CLK_noedge_posedge,
|
|
HoldHigh => thold_M0_CLK_noedge_posedge,
|
|
HoldLow => thold_M0_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => M0_CLK_TimingDatash,
|
|
Violation => tviol_M0_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
F0_zd := F0_out;
|
|
Q0_zd := Q0_out;
|
|
F1_zd := F1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd,
|
|
Paths => (0 => (InputChangeTime => B0_ipd'last_event,
|
|
PathDelay => tpd_B0_F0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A0_ipd'last_event,
|
|
PathDelay => tpd_A0_F0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_Q0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Q0_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd,
|
|
Paths => (0 => (InputChangeTime => B1_ipd'last_event,
|
|
PathDelay => tpd_B1_F1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => A1_ipd'last_event,
|
|
PathDelay => tpd_A1_F1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => F1_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf is
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf;
|
|
|
|
architecture Structure of xo2iobuf is
|
|
begin
|
|
INST1: IB
|
|
port map (I=>PADI, O=>Z);
|
|
INST2: OBW
|
|
port map (I=>I, T=>T, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity RD_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_0_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD0 : VitalDelayType := 0 ns;
|
|
tpw_RD0_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD0_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD0: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE;
|
|
|
|
end RD_0_B;
|
|
|
|
architecture Structure of RD_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD0_ipd : std_logic := 'X';
|
|
signal RD0_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_0: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out,
|
|
PADI=>RD0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD0_ipd, RD0, tipd_RD0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD0_ipd, RD0_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD0_zd : std_logic := 'X';
|
|
VARIABLE RD0_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD0_RD0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD0_ipd,
|
|
TestSignalName => "RD0",
|
|
Period => tperiod_RD0,
|
|
PulseWidthHigh => tpw_RD0_posedge,
|
|
PulseWidthLow => tpw_RD0_negedge,
|
|
PeriodData => periodcheckinfo_RD0,
|
|
Violation => tviol_RD0_RD0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD0_zd := RD0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD0_ipd'last_event,
|
|
PathDelay => tpd_RD0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD0,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mfflsre
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity mfflsre is
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE;
|
|
|
|
end mfflsre;
|
|
|
|
architecture Structure of mfflsre is
|
|
begin
|
|
INST01: FD1P3DX
|
|
generic map (GSR => "DISABLED")
|
|
port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity RD_0_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_0_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_0_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_0_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_0_MGIOL;
|
|
|
|
architecture Structure of RD_0_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_0: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0110
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0110 is
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0110 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0110;
|
|
|
|
architecture Structure of xo2iobuf0110 is
|
|
begin
|
|
INST5: OB
|
|
port map (I=>I, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity Dout_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE;
|
|
|
|
end Dout_0_B;
|
|
|
|
architecture Structure of Dout_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout0_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_0: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout0_out)
|
|
VARIABLE Dout0_zd : std_logic := 'X';
|
|
VARIABLE Dout0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout0_zd := Dout0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0111
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0111 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0111 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0111;
|
|
|
|
architecture Structure of xo2iobuf0111 is
|
|
begin
|
|
INST1: IBPD
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity PHI2B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity PHI2B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "PHI2B";
|
|
|
|
tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_PHI2S : VitalDelayType := 0 ns;
|
|
tpw_PHI2S_posedge : VitalDelayType := 0 ns;
|
|
tpw_PHI2S_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; PHI2S: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE;
|
|
|
|
end PHI2B;
|
|
|
|
architecture Structure of PHI2B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal PHI2S_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0111
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2_pad: xo2iobuf0111
|
|
port map (Z=>PADDI_out, PAD=>PHI2S_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_PHI2S_PHI2S : x01 := '0';
|
|
VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => PHI2S_ipd,
|
|
TestSignalName => "PHI2S",
|
|
Period => tperiod_PHI2S,
|
|
PulseWidthHigh => tpw_PHI2S_posedge,
|
|
PulseWidthLow => tpw_PHI2S_negedge,
|
|
PeriodData => periodcheckinfo_PHI2S,
|
|
Violation => tviol_PHI2S_PHI2S,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event,
|
|
PathDelay => tpd_PHI2S_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity smuxlregsre
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity smuxlregsre is
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE;
|
|
|
|
end smuxlregsre;
|
|
|
|
architecture Structure of smuxlregsre is
|
|
begin
|
|
INST01: IFS1P3DX
|
|
generic map (GSR => "DISABLED")
|
|
port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity PHI2_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity PHI2_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "PHI2_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF PHI2_MGIOL : ENTITY IS TRUE;
|
|
|
|
end PHI2_MGIOL;
|
|
|
|
architecture Structure of PHI2_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
PHI2r_0io: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RDQMLB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RDQMLB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RDQMLB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RDQMLS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE;
|
|
|
|
end RDQMLB;
|
|
|
|
architecture Structure of RDQMLB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RDQMLS_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQML_pad: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RDQMLS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out)
|
|
VARIABLE RDQMLS_zd : std_logic := 'X';
|
|
VARIABLE RDQMLS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RDQMLS_zd := RDQMLS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RDQMLS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RDQMLS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RDQMHB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RDQMHB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RDQMHB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RDQMHS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE;
|
|
|
|
end RDQMHB;
|
|
|
|
architecture Structure of RDQMHB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RDQMHS_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RDQMH_pad: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RDQMHS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out)
|
|
VARIABLE RDQMHS_zd : std_logic := 'X';
|
|
VARIABLE RDQMHS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RDQMHS_zd := RDQMHS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RDQMHS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RDQMHS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRCASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCASB";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; nRCASS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE;
|
|
|
|
end nRCASB;
|
|
|
|
architecture Structure of nRCASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal nRCASS_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_pad: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>nRCASS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, nRCASS_out)
|
|
VARIABLE nRCASS_zd : std_logic := 'X';
|
|
VARIABLE nRCASS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRCASS_zd := nRCASS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_nRCASS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRCASS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mfflsre0112
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity mfflsre0112 is
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mfflsre0112 : ENTITY IS TRUE;
|
|
|
|
end mfflsre0112;
|
|
|
|
architecture Structure of mfflsre0112 is
|
|
begin
|
|
INST01: FD1P3BX
|
|
generic map (GSR => "DISABLED")
|
|
port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity nRCAS_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRCAS_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCAS_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCAS_MGIOL : ENTITY IS TRUE;
|
|
|
|
end nRCAS_MGIOL;
|
|
|
|
architecture Structure of nRCAS_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component mfflsre0112
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCAS_0io: mfflsre0112
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_posedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_posedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRRASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRRASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRRASB";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; nRRASS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE;
|
|
|
|
end nRRASB;
|
|
|
|
architecture Structure of nRRASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal nRRASS_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_pad: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>nRRASS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, nRRASS_out)
|
|
VARIABLE nRRASS_zd : std_logic := 'X';
|
|
VARIABLE nRRASS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRRASS_zd := nRRASS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_nRRASS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRRASS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRRAS_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRRAS_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRRAS_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRRAS_MGIOL : ENTITY IS TRUE;
|
|
|
|
end nRRAS_MGIOL;
|
|
|
|
architecture Structure of nRRAS_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component mfflsre0112
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRRAS_0io: mfflsre0112
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_posedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_posedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRWEB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRWEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRWEB";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_nRWES : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; nRWES: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE;
|
|
|
|
end nRWEB;
|
|
|
|
architecture Structure of nRWEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal nRWES_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_pad: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>nRWES_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, nRWES_out)
|
|
VARIABLE nRWES_zd : std_logic := 'X';
|
|
VARIABLE nRWES_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRWES_zd := nRWES_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_nRWES,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRWES_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRWE_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRWE_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRWE_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRWE_MGIOL : ENTITY IS TRUE;
|
|
|
|
end nRWE_MGIOL;
|
|
|
|
architecture Structure of nRWE_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component mfflsre0112
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRWE_0io: mfflsre0112
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_posedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_posedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RCKEB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RCKEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RCKEB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RCKES: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE;
|
|
|
|
end RCKEB;
|
|
|
|
architecture Structure of RCKEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RCKES_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RCKE_pad: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RCKES_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RCKES_out)
|
|
VARIABLE RCKES_zd : std_logic := 'X';
|
|
VARIABLE RCKES_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RCKES_zd := RCKES_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RCKES,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RCKES_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0113
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0113 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0113 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0113;
|
|
|
|
architecture Structure of xo2iobuf0113 is
|
|
begin
|
|
INST1: IB
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity RCLKB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RCLKB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RCLKB";
|
|
|
|
tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RCLKS : VitalDelayType := 0 ns;
|
|
tpw_RCLKS_posedge : VitalDelayType := 0 ns;
|
|
tpw_RCLKS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; RCLKS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE;
|
|
|
|
end RCLKB;
|
|
|
|
architecture Structure of RCLKB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal RCLKS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
RCLK_pad: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>RCLKS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RCLKS_RCLKS : x01 := '0';
|
|
VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RCLKS_ipd,
|
|
TestSignalName => "RCLKS",
|
|
Period => tperiod_RCLKS,
|
|
PulseWidthHigh => tpw_RCLKS_posedge,
|
|
PulseWidthLow => tpw_RCLKS_negedge,
|
|
PeriodData => periodcheckinfo_RCLKS,
|
|
Violation => tviol_RCLKS_RCLKS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event,
|
|
PathDelay => tpd_RCLKS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCSB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRCSB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCSB";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; nRCSS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE;
|
|
|
|
end nRCSB;
|
|
|
|
architecture Structure of nRCSB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal nRCSS_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_pad: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>nRCSS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, nRCSS_out)
|
|
VARIABLE nRCSS_zd : std_logic := 'X';
|
|
VARIABLE nRCSS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
nRCSS_zd := nRCSS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_nRCSS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => nRCSS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nRCS_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nRCS_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nRCS_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nRCS_MGIOL : ENTITY IS TRUE;
|
|
|
|
end nRCS_MGIOL;
|
|
|
|
architecture Structure of nRCS_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component mfflsre0112
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
nRCS_0io: mfflsre0112
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_posedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_posedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_7_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD7 : VitalDelayType := 0 ns;
|
|
tpw_RD7_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD7_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD7: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE;
|
|
|
|
end RD_7_B;
|
|
|
|
architecture Structure of RD_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD7_ipd : std_logic := 'X';
|
|
signal RD7_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_7: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out,
|
|
PADI=>RD7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD7_ipd, RD7, tipd_RD7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD7_ipd, RD7_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD7_zd : std_logic := 'X';
|
|
VARIABLE RD7_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD7_RD7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD7_ipd,
|
|
TestSignalName => "RD7",
|
|
Period => tperiod_RD7,
|
|
PulseWidthHigh => tpw_RD7_posedge,
|
|
PulseWidthLow => tpw_RD7_negedge,
|
|
PeriodData => periodcheckinfo_RD7,
|
|
Violation => tviol_RD7_RD7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD7_zd := RD7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD7_ipd'last_event,
|
|
PathDelay => tpd_RD7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD7,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_7_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_7_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_7_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_7_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_7_MGIOL;
|
|
|
|
architecture Structure of RD_7_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_7: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_6_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD6 : VitalDelayType := 0 ns;
|
|
tpw_RD6_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD6_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD6: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE;
|
|
|
|
end RD_6_B;
|
|
|
|
architecture Structure of RD_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD6_ipd : std_logic := 'X';
|
|
signal RD6_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_6: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out,
|
|
PADI=>RD6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD6_ipd, RD6, tipd_RD6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD6_ipd, RD6_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD6_zd : std_logic := 'X';
|
|
VARIABLE RD6_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD6_RD6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD6_ipd,
|
|
TestSignalName => "RD6",
|
|
Period => tperiod_RD6,
|
|
PulseWidthHigh => tpw_RD6_posedge,
|
|
PulseWidthLow => tpw_RD6_negedge,
|
|
PeriodData => periodcheckinfo_RD6,
|
|
Violation => tviol_RD6_RD6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD6_zd := RD6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD6_ipd'last_event,
|
|
PathDelay => tpd_RD6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD6,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_6_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_6_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_6_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_6_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_6_MGIOL;
|
|
|
|
architecture Structure of RD_6_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_6: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_5_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD5 : VitalDelayType := 0 ns;
|
|
tpw_RD5_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD5_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD5: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE;
|
|
|
|
end RD_5_B;
|
|
|
|
architecture Structure of RD_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD5_ipd : std_logic := 'X';
|
|
signal RD5_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_5: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out,
|
|
PADI=>RD5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD5_ipd, RD5, tipd_RD5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD5_ipd, RD5_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD5_zd : std_logic := 'X';
|
|
VARIABLE RD5_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD5_RD5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD5_ipd,
|
|
TestSignalName => "RD5",
|
|
Period => tperiod_RD5,
|
|
PulseWidthHigh => tpw_RD5_posedge,
|
|
PulseWidthLow => tpw_RD5_negedge,
|
|
PeriodData => periodcheckinfo_RD5,
|
|
Violation => tviol_RD5_RD5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD5_zd := RD5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD5_ipd'last_event,
|
|
PathDelay => tpd_RD5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD5,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_5_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_5_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_5_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_5_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_5_MGIOL;
|
|
|
|
architecture Structure of RD_5_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_5: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_4_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD4 : VitalDelayType := 0 ns;
|
|
tpw_RD4_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD4_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD4: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE;
|
|
|
|
end RD_4_B;
|
|
|
|
architecture Structure of RD_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD4_ipd : std_logic := 'X';
|
|
signal RD4_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_4: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out,
|
|
PADI=>RD4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD4_ipd, RD4, tipd_RD4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD4_ipd, RD4_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD4_zd : std_logic := 'X';
|
|
VARIABLE RD4_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD4_RD4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD4_ipd,
|
|
TestSignalName => "RD4",
|
|
Period => tperiod_RD4,
|
|
PulseWidthHigh => tpw_RD4_posedge,
|
|
PulseWidthLow => tpw_RD4_negedge,
|
|
PeriodData => periodcheckinfo_RD4,
|
|
Violation => tviol_RD4_RD4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD4_zd := RD4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD4_ipd'last_event,
|
|
PathDelay => tpd_RD4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD4,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_4_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_4_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_4_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_4_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_4_MGIOL;
|
|
|
|
architecture Structure of RD_4_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_4: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_3_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD3 : VitalDelayType := 0 ns;
|
|
tpw_RD3_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD3_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD3: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE;
|
|
|
|
end RD_3_B;
|
|
|
|
architecture Structure of RD_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD3_ipd : std_logic := 'X';
|
|
signal RD3_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_3: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out,
|
|
PADI=>RD3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD3_ipd, RD3, tipd_RD3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD3_ipd, RD3_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD3_zd : std_logic := 'X';
|
|
VARIABLE RD3_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD3_RD3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD3_ipd,
|
|
TestSignalName => "RD3",
|
|
Period => tperiod_RD3,
|
|
PulseWidthHigh => tpw_RD3_posedge,
|
|
PulseWidthLow => tpw_RD3_negedge,
|
|
PeriodData => periodcheckinfo_RD3,
|
|
Violation => tviol_RD3_RD3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD3_zd := RD3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD3_ipd'last_event,
|
|
PathDelay => tpd_RD3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD3,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_3_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_3_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_3_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_3_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_3_MGIOL;
|
|
|
|
architecture Structure of RD_3_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_3: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_2_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD2 : VitalDelayType := 0 ns;
|
|
tpw_RD2_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD2_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD2: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE;
|
|
|
|
end RD_2_B;
|
|
|
|
architecture Structure of RD_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD2_ipd : std_logic := 'X';
|
|
signal RD2_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_2: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out,
|
|
PADI=>RD2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD2_ipd, RD2, tipd_RD2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD2_ipd, RD2_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD2_zd : std_logic := 'X';
|
|
VARIABLE RD2_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD2_RD2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD2_ipd,
|
|
TestSignalName => "RD2",
|
|
Period => tperiod_RD2,
|
|
PulseWidthHigh => tpw_RD2_posedge,
|
|
PulseWidthLow => tpw_RD2_negedge,
|
|
PeriodData => periodcheckinfo_RD2,
|
|
Violation => tviol_RD2_RD2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD2_zd := RD2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD2_ipd'last_event,
|
|
PathDelay => tpd_RD2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD2,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_2_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_2_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_2_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_2_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_2_MGIOL;
|
|
|
|
architecture Structure of RD_2_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_2: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_1_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns);
|
|
tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_RD1 : VitalDelayType := 0 ns;
|
|
tpw_RD1_posedge : VitalDelayType := 0 ns;
|
|
tpw_RD1_negedge : VitalDelayType := 0 ns;
|
|
tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns));
|
|
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD1: inout Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE;
|
|
|
|
end RD_1_B;
|
|
|
|
architecture Structure of RD_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal PADDT_ipd : std_logic := 'X';
|
|
signal RD1_ipd : std_logic := 'X';
|
|
signal RD1_out : std_logic := 'Z';
|
|
|
|
component xo2iobuf
|
|
port (I: in Std_logic; T: in Std_logic; Z: out Std_logic;
|
|
PAD: out Std_logic; PADI: in Std_logic);
|
|
end component;
|
|
begin
|
|
RD_pad_1: xo2iobuf
|
|
port map (I=>IOLDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out,
|
|
PADI=>RD1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT);
|
|
VitalWireDelay(RD1_ipd, RD1, tipd_RD1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, IOLDO_ipd, PADDT_ipd, RD1_ipd, RD1_out)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
VARIABLE RD1_zd : std_logic := 'X';
|
|
VARIABLE RD1_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_RD1_RD1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => RD1_ipd,
|
|
TestSignalName => "RD1",
|
|
Period => tperiod_RD1,
|
|
PulseWidthHigh => tpw_RD1_posedge,
|
|
PulseWidthLow => tpw_RD1_negedge,
|
|
PeriodData => periodcheckinfo_RD1,
|
|
Violation => tviol_RD1_RD1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
RD1_zd := RD1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => RD1_ipd'last_event,
|
|
PathDelay => tpd_RD1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01Z (
|
|
OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RD1,
|
|
PathCondition => TRUE),
|
|
1 => (InputChangeTime => PADDT_ipd'last_event,
|
|
PathDelay => tpd_PADDT_RD1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RD1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RD_1_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RD_1_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RD_1_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RD_1_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RD_1_MGIOL;
|
|
|
|
architecture Structure of RD_1_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
WRD_0io_1: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_11_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_11_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_11_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RA11 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; RA11: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE;
|
|
|
|
end RA_11_B;
|
|
|
|
architecture Structure of RA_11_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal RA11_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_11: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>RA11_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, RA11_out)
|
|
VARIABLE RA11_zd : std_logic := 'X';
|
|
VARIABLE RA11_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA11_zd := RA11_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RA11,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA11_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_11_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_11_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_11_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_11_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RA_11_MGIOL;
|
|
|
|
architecture Structure of RA_11_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA11_0io: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_posedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_posedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_10_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_10_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_10_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RA10 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; RA10: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE;
|
|
|
|
end RA_10_B;
|
|
|
|
architecture Structure of RA_10_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal RA10_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_10: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>RA10_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, RA10_out)
|
|
VARIABLE RA10_zd : std_logic := 'X';
|
|
VARIABLE RA10_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA10_zd := RA10_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RA10,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA10_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity mfflsre0114
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity mfflsre0114 is
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF mfflsre0114 : ENTITY IS TRUE;
|
|
|
|
end mfflsre0114;
|
|
|
|
architecture Structure of mfflsre0114 is
|
|
begin
|
|
INST01: FD1P3JX
|
|
generic map (GSR => "DISABLED")
|
|
port map (D=>D0, SP=>SP, CK=>CK, PD=>LSR, Q=>Q);
|
|
end Structure;
|
|
|
|
-- entity RA_10_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_10_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_10_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_LSR : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_LSR_CLK : VitalDelayType := 0 ns;
|
|
tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_10_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RA_10_MGIOL;
|
|
|
|
architecture Structure of RA_10_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal LSR_ipd : std_logic := 'X';
|
|
signal LSR_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component mfflsre0114
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA10_0io: mfflsre0114
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly,
|
|
Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(LSR_ipd, LSR, tipd_LSR);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, LSR_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_LSR_CLK : x01 := '0';
|
|
VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_posedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_posedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_posedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => LSR_dly,
|
|
TestSignalName => "LSR",
|
|
TestDelay => tisd_LSR_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_LSR_CLK_noedge_posedge,
|
|
SetupLow => tsetup_LSR_CLK_noedge_posedge,
|
|
HoldHigh => thold_LSR_CLK_noedge_posedge,
|
|
HoldLow => thold_LSR_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => LSR_CLK_TimingDatash,
|
|
Violation => tviol_LSR_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_9_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_9_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_9_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA9: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE;
|
|
|
|
end RA_9_B;
|
|
|
|
architecture Structure of RA_9_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA9_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_9: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA9_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA9_out)
|
|
VARIABLE RA9_zd : std_logic := 'X';
|
|
VARIABLE RA9_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA9_zd := RA9_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA9,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA9_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_8_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_8_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_8_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA8: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE;
|
|
|
|
end RA_8_B;
|
|
|
|
architecture Structure of RA_8_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA8_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_8: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA8_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA8_out)
|
|
VARIABLE RA8_zd : std_logic := 'X';
|
|
VARIABLE RA8_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA8_zd := RA8_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA8,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA8_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_7_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA7: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE;
|
|
|
|
end RA_7_B;
|
|
|
|
architecture Structure of RA_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA7_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_7: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA7_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA7_out)
|
|
VARIABLE RA7_zd : std_logic := 'X';
|
|
VARIABLE RA7_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA7_zd := RA7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_6_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA6: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE;
|
|
|
|
end RA_6_B;
|
|
|
|
architecture Structure of RA_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA6_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_6: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA6_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA6_out)
|
|
VARIABLE RA6_zd : std_logic := 'X';
|
|
VARIABLE RA6_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA6_zd := RA6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_5_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA5: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE;
|
|
|
|
end RA_5_B;
|
|
|
|
architecture Structure of RA_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA5_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_5: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA5_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA5_out)
|
|
VARIABLE RA5_zd : std_logic := 'X';
|
|
VARIABLE RA5_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA5_zd := RA5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_4_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA4: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE;
|
|
|
|
end RA_4_B;
|
|
|
|
architecture Structure of RA_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA4_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_4: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA4_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA4_out)
|
|
VARIABLE RA4_zd : std_logic := 'X';
|
|
VARIABLE RA4_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA4_zd := RA4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_3_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA3: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE;
|
|
|
|
end RA_3_B;
|
|
|
|
architecture Structure of RA_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA3_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_3: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA3_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA3_out)
|
|
VARIABLE RA3_zd : std_logic := 'X';
|
|
VARIABLE RA3_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA3_zd := RA3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_2_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA2: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE;
|
|
|
|
end RA_2_B;
|
|
|
|
architecture Structure of RA_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA2_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_2: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA2_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA2_out)
|
|
VARIABLE RA2_zd : std_logic := 'X';
|
|
VARIABLE RA2_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA2_zd := RA2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE;
|
|
|
|
end RA_1_B;
|
|
|
|
architecture Structure of RA_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA1_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_1: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA1_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA1_out)
|
|
VARIABLE RA1_zd : std_logic := 'X';
|
|
VARIABLE RA1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA1_zd := RA1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RA_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RA_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RA_0_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; RA0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE;
|
|
|
|
end RA_0_B;
|
|
|
|
architecture Structure of RA_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal RA0_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RA_pad_0: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>RA0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, RA0_out)
|
|
VARIABLE RA0_zd : std_logic := 'X';
|
|
VARIABLE RA0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RA0_zd := RA0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_RA0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RA0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RBA_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_1_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; RBA1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE;
|
|
|
|
end RBA_1_B;
|
|
|
|
architecture Structure of RBA_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal RBA1_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_pad_1: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>RBA1_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, RBA1_out)
|
|
VARIABLE RBA1_zd : std_logic := 'X';
|
|
VARIABLE RBA1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RBA1_zd := RBA1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RBA1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RBA1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_1_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RBA_1_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_1_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_1_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RBA_1_MGIOL;
|
|
|
|
architecture Structure of RBA_1_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_0io_1: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RBA_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_0_B";
|
|
|
|
tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_IOLDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (IOLDO: in Std_logic; RBA0: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE;
|
|
|
|
end RBA_0_B;
|
|
|
|
architecture Structure of RBA_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_ipd : std_logic := 'X';
|
|
signal RBA0_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_pad_0: xo2iobuf0110
|
|
port map (I=>IOLDO_ipd, PAD=>RBA0_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_ipd, RBA0_out)
|
|
VARIABLE RBA0_zd : std_logic := 'X';
|
|
VARIABLE RBA0_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
RBA0_zd := RBA0_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd,
|
|
Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event,
|
|
PathDelay => tpd_IOLDO_RBA0,
|
|
PathCondition => TRUE)),
|
|
GlitchData => RBA0_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity RBA_0_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RBA_0_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "RBA_0_MGIOL";
|
|
|
|
tipd_OPOS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns;
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_OPOS_CLK : VitalDelayType := 0 ns;
|
|
tsetup_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns;
|
|
thold_OPOS_CLK_noedge_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF RBA_0_MGIOL : ENTITY IS TRUE;
|
|
|
|
end RBA_0_MGIOL;
|
|
|
|
architecture Structure of RBA_0_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal IOLDO_out : std_logic := 'X';
|
|
signal OPOS_ipd : std_logic := 'X';
|
|
signal OPOS_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal CLK_NOTIN: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component inverter
|
|
port (I: in Std_logic; Z: out Std_logic);
|
|
end component;
|
|
component mfflsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
RBA_0io_0: mfflsre
|
|
port map (D0=>OPOS_dly, SP=>VCCI, CK=>CLK_NOTIN, LSR=>GNDI, Q=>IOLDO_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
CLK_INVERTERIN: inverter
|
|
port map (I=>CLK_dly, Z=>CLK_NOTIN);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(OPOS_ipd, OPOS, tipd_OPOS);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(OPOS_dly, OPOS_ipd, tisd_OPOS_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (IOLDO_out, OPOS_dly, CLK_dly)
|
|
VARIABLE IOLDO_zd : std_logic := 'X';
|
|
VARIABLE IOLDO_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_OPOS_CLK : x01 := '0';
|
|
VARIABLE OPOS_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => OPOS_dly,
|
|
TestSignalName => "OPOS",
|
|
TestDelay => tisd_OPOS_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_OPOS_CLK_noedge_negedge,
|
|
SetupLow => tsetup_OPOS_CLK_noedge_negedge,
|
|
HoldHigh => thold_OPOS_CLK_noedge_negedge,
|
|
HoldLow => thold_OPOS_CLK_noedge_negedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '\',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => OPOS_CLK_TimingDatash,
|
|
Violation => tviol_OPOS_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
IOLDO_zd := IOLDO_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_IOLDO,
|
|
PathCondition => TRUE)),
|
|
GlitchData => IOLDO_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0115
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0115 is
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0115 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0115;
|
|
|
|
architecture Structure of xo2iobuf0115 is
|
|
begin
|
|
INST5: OB
|
|
port map (I=>I, O=>PAD);
|
|
end Structure;
|
|
|
|
-- entity LEDB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity LEDB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "LEDB";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; LEDS: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE;
|
|
|
|
end LEDB;
|
|
|
|
architecture Structure of LEDB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal LEDS_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0115
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
LED_pad: xo2iobuf0115
|
|
port map (I=>PADDO_ipd, PAD=>LEDS_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, LEDS_out)
|
|
VARIABLE LEDS_zd : std_logic := 'X';
|
|
VARIABLE LEDS_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
LEDS_zd := LEDS_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_LEDS,
|
|
PathCondition => TRUE)),
|
|
GlitchData => LEDS_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity xo2iobuf0116
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity xo2iobuf0116 is
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF xo2iobuf0116 : ENTITY IS TRUE;
|
|
|
|
end xo2iobuf0116;
|
|
|
|
architecture Structure of xo2iobuf0116 is
|
|
begin
|
|
INST1: IBPU
|
|
port map (I=>PAD, O=>Z);
|
|
end Structure;
|
|
|
|
-- entity nFWEB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nFWEB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nFWEB";
|
|
|
|
tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nFWES : VitalDelayType := 0 ns;
|
|
tpw_nFWES_posedge : VitalDelayType := 0 ns;
|
|
tpw_nFWES_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nFWES: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE;
|
|
|
|
end nFWEB;
|
|
|
|
architecture Structure of nFWEB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nFWES_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0116
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nFWE_pad: xo2iobuf0116
|
|
port map (Z=>PADDI_out, PAD=>nFWES_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nFWES_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nFWES_nFWES : x01 := '0';
|
|
VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nFWES_ipd,
|
|
TestSignalName => "nFWES",
|
|
Period => tperiod_nFWES,
|
|
PulseWidthHigh => tpw_nFWES_posedge,
|
|
PulseWidthLow => tpw_nFWES_negedge,
|
|
PeriodData => periodcheckinfo_nFWES,
|
|
Violation => tviol_nFWES_nFWES,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nFWES_ipd'last_event,
|
|
PathDelay => tpd_nFWES_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nCRASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nCRASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nCRASB";
|
|
|
|
tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nCRASS : VitalDelayType := 0 ns;
|
|
tpw_nCRASS_posedge : VitalDelayType := 0 ns;
|
|
tpw_nCRASS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nCRASS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE;
|
|
|
|
end nCRASB;
|
|
|
|
architecture Structure of nCRASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nCRASS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0116
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nCRAS_pad: xo2iobuf0116
|
|
port map (Z=>PADDI_out, PAD=>nCRASS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nCRASS_nCRASS : x01 := '0';
|
|
VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nCRASS_ipd,
|
|
TestSignalName => "nCRASS",
|
|
Period => tperiod_nCRASS,
|
|
PulseWidthHigh => tpw_nCRASS_posedge,
|
|
PulseWidthLow => tpw_nCRASS_negedge,
|
|
PeriodData => periodcheckinfo_nCRASS,
|
|
Violation => tviol_nCRASS_nCRASS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event,
|
|
PathDelay => tpd_nCRASS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity nCCASB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity nCCASB is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "nCCASB";
|
|
|
|
tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_nCCASS : VitalDelayType := 0 ns;
|
|
tpw_nCCASS_posedge : VitalDelayType := 0 ns;
|
|
tpw_nCCASS_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; nCCASS: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE;
|
|
|
|
end nCCASB;
|
|
|
|
architecture Structure of nCCASB is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal nCCASS_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0116
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
nCCAS_pad: xo2iobuf0116
|
|
port map (Z=>PADDI_out, PAD=>nCCASS_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_nCCASS_nCCASS : x01 := '0';
|
|
VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => nCCASS_ipd,
|
|
TestSignalName => "nCCASS",
|
|
Period => tperiod_nCCASS,
|
|
PulseWidthHigh => tpw_nCCASS_posedge,
|
|
PulseWidthLow => tpw_nCCASS_negedge,
|
|
PeriodData => periodcheckinfo_nCCASS,
|
|
Violation => tviol_nCCASS_nCCASS,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event,
|
|
PathDelay => tpd_nCCASS_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_7_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout7: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE;
|
|
|
|
end Dout_7_B;
|
|
|
|
architecture Structure of Dout_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout7_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_7: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout7_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout7_out)
|
|
VARIABLE Dout7_zd : std_logic := 'X';
|
|
VARIABLE Dout7_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout7_zd := Dout7_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout7,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout7_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_6_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout6: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE;
|
|
|
|
end Dout_6_B;
|
|
|
|
architecture Structure of Dout_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout6_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_6: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout6_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout6_out)
|
|
VARIABLE Dout6_zd : std_logic := 'X';
|
|
VARIABLE Dout6_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout6_zd := Dout6_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout6,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout6_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_5_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout5: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE;
|
|
|
|
end Dout_5_B;
|
|
|
|
architecture Structure of Dout_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout5_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_5: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout5_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout5_out)
|
|
VARIABLE Dout5_zd : std_logic := 'X';
|
|
VARIABLE Dout5_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout5_zd := Dout5_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout5,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout5_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_4_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout4: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE;
|
|
|
|
end Dout_4_B;
|
|
|
|
architecture Structure of Dout_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout4_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_4: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout4_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout4_out)
|
|
VARIABLE Dout4_zd : std_logic := 'X';
|
|
VARIABLE Dout4_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout4_zd := Dout4_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout4,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout4_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_3_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout3: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE;
|
|
|
|
end Dout_3_B;
|
|
|
|
architecture Structure of Dout_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout3_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_3: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout3_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout3_out)
|
|
VARIABLE Dout3_zd : std_logic := 'X';
|
|
VARIABLE Dout3_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout3_zd := Dout3_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout3,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout3_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_2_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout2: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE;
|
|
|
|
end Dout_2_B;
|
|
|
|
architecture Structure of Dout_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout2_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_2: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout2_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout2_out)
|
|
VARIABLE Dout2_zd : std_logic := 'X';
|
|
VARIABLE Dout2_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout2_zd := Dout2_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout2,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout2_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Dout_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Dout_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Dout_1_B";
|
|
|
|
tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns));
|
|
|
|
port (PADDO: in Std_logic; Dout1: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE;
|
|
|
|
end Dout_1_B;
|
|
|
|
architecture Structure of Dout_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDO_ipd : std_logic := 'X';
|
|
signal Dout1_out : std_logic := 'X';
|
|
|
|
component xo2iobuf0110
|
|
port (I: in Std_logic; PAD: out Std_logic);
|
|
end component;
|
|
begin
|
|
Dout_pad_1: xo2iobuf0110
|
|
port map (I=>PADDO_ipd, PAD=>Dout1_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDO_ipd, Dout1_out)
|
|
VARIABLE Dout1_zd : std_logic := 'X';
|
|
VARIABLE Dout1_GlitchData : VitalGlitchDataType;
|
|
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
|
|
END IF;
|
|
|
|
Dout1_zd := Dout1_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd,
|
|
Paths => (0 => (InputChangeTime => PADDO_ipd'last_event,
|
|
PathDelay => tpd_PADDO_Dout1,
|
|
PathCondition => TRUE)),
|
|
GlitchData => Dout1_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_7_B";
|
|
|
|
tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din7 : VitalDelayType := 0 ns;
|
|
tpw_Din7_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din7_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din7: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE;
|
|
|
|
end Din_7_B;
|
|
|
|
architecture Structure of Din_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din7_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_7: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din7_ipd, Din7, tipd_Din7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din7_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din7_Din7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din7_ipd,
|
|
TestSignalName => "Din7",
|
|
Period => tperiod_Din7,
|
|
PulseWidthHigh => tpw_Din7_posedge,
|
|
PulseWidthLow => tpw_Din7_negedge,
|
|
PeriodData => periodcheckinfo_Din7,
|
|
Violation => tviol_Din7_Din7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din7_ipd'last_event,
|
|
PathDelay => tpd_Din7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_7_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_7_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_7_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_7_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_7_MGIOL;
|
|
|
|
architecture Structure of Din_7_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_7: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_6_B";
|
|
|
|
tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din6 : VitalDelayType := 0 ns;
|
|
tpw_Din6_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din6_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din6: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE;
|
|
|
|
end Din_6_B;
|
|
|
|
architecture Structure of Din_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din6_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_6: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din6_ipd, Din6, tipd_Din6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din6_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din6_Din6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din6_ipd,
|
|
TestSignalName => "Din6",
|
|
Period => tperiod_Din6,
|
|
PulseWidthHigh => tpw_Din6_posedge,
|
|
PulseWidthLow => tpw_Din6_negedge,
|
|
PeriodData => periodcheckinfo_Din6,
|
|
Violation => tviol_Din6_Din6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din6_ipd'last_event,
|
|
PathDelay => tpd_Din6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_6_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_6_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_6_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_6_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_6_MGIOL;
|
|
|
|
architecture Structure of Din_6_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_6: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_5_B";
|
|
|
|
tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din5 : VitalDelayType := 0 ns;
|
|
tpw_Din5_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din5_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din5: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE;
|
|
|
|
end Din_5_B;
|
|
|
|
architecture Structure of Din_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din5_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_5: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din5_ipd, Din5, tipd_Din5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din5_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din5_Din5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din5_ipd,
|
|
TestSignalName => "Din5",
|
|
Period => tperiod_Din5,
|
|
PulseWidthHigh => tpw_Din5_posedge,
|
|
PulseWidthLow => tpw_Din5_negedge,
|
|
PeriodData => periodcheckinfo_Din5,
|
|
Violation => tviol_Din5_Din5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din5_ipd'last_event,
|
|
PathDelay => tpd_Din5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_5_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_5_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_5_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_5_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_5_MGIOL;
|
|
|
|
architecture Structure of Din_5_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_5: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_4_B";
|
|
|
|
tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din4 : VitalDelayType := 0 ns;
|
|
tpw_Din4_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din4_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din4: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE;
|
|
|
|
end Din_4_B;
|
|
|
|
architecture Structure of Din_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din4_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_4: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din4_ipd, Din4, tipd_Din4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din4_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din4_Din4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din4_ipd,
|
|
TestSignalName => "Din4",
|
|
Period => tperiod_Din4,
|
|
PulseWidthHigh => tpw_Din4_posedge,
|
|
PulseWidthLow => tpw_Din4_negedge,
|
|
PeriodData => periodcheckinfo_Din4,
|
|
Violation => tviol_Din4_Din4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din4_ipd'last_event,
|
|
PathDelay => tpd_Din4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_4_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_4_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_4_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_4_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_4_MGIOL;
|
|
|
|
architecture Structure of Din_4_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_4: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_3_B";
|
|
|
|
tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din3 : VitalDelayType := 0 ns;
|
|
tpw_Din3_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din3_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din3: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE;
|
|
|
|
end Din_3_B;
|
|
|
|
architecture Structure of Din_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din3_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_3: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din3_ipd, Din3, tipd_Din3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din3_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din3_Din3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din3_ipd,
|
|
TestSignalName => "Din3",
|
|
Period => tperiod_Din3,
|
|
PulseWidthHigh => tpw_Din3_posedge,
|
|
PulseWidthLow => tpw_Din3_negedge,
|
|
PeriodData => periodcheckinfo_Din3,
|
|
Violation => tviol_Din3_Din3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din3_ipd'last_event,
|
|
PathDelay => tpd_Din3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_3_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_3_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_3_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_3_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_3_MGIOL;
|
|
|
|
architecture Structure of Din_3_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_3: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_2_B";
|
|
|
|
tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din2 : VitalDelayType := 0 ns;
|
|
tpw_Din2_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din2_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din2: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE;
|
|
|
|
end Din_2_B;
|
|
|
|
architecture Structure of Din_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din2_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_2: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din2_ipd, Din2, tipd_Din2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din2_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din2_Din2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din2_ipd,
|
|
TestSignalName => "Din2",
|
|
Period => tperiod_Din2,
|
|
PulseWidthHigh => tpw_Din2_posedge,
|
|
PulseWidthLow => tpw_Din2_negedge,
|
|
PeriodData => periodcheckinfo_Din2,
|
|
Violation => tviol_Din2_Din2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din2_ipd'last_event,
|
|
PathDelay => tpd_Din2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_2_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_2_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_2_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_2_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_2_MGIOL;
|
|
|
|
architecture Structure of Din_2_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_2: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_1_B";
|
|
|
|
tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din1 : VitalDelayType := 0 ns;
|
|
tpw_Din1_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE;
|
|
|
|
end Din_1_B;
|
|
|
|
architecture Structure of Din_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din1_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_1: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din1_ipd, Din1, tipd_Din1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din1_Din1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din1_ipd,
|
|
TestSignalName => "Din1",
|
|
Period => tperiod_Din1,
|
|
PulseWidthHigh => tpw_Din1_posedge,
|
|
PulseWidthLow => tpw_Din1_negedge,
|
|
PeriodData => periodcheckinfo_Din1,
|
|
Violation => tviol_Din1_Din1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din1_ipd'last_event,
|
|
PathDelay => tpd_Din1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_1_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_1_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_1_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_1_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_1_MGIOL;
|
|
|
|
architecture Structure of Din_1_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_1: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_0_B";
|
|
|
|
tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_Din0 : VitalDelayType := 0 ns;
|
|
tpw_Din0_posedge : VitalDelayType := 0 ns;
|
|
tpw_Din0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; Din0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE;
|
|
|
|
end Din_0_B;
|
|
|
|
architecture Structure of Din_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal Din0_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
Din_pad_0: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>Din0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(Din0_ipd, Din0, tipd_Din0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, Din0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_Din0_Din0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => Din0_ipd,
|
|
TestSignalName => "Din0",
|
|
Period => tperiod_Din0,
|
|
PulseWidthHigh => tpw_Din0_posedge,
|
|
PulseWidthLow => tpw_Din0_negedge,
|
|
PeriodData => periodcheckinfo_Din0,
|
|
Violation => tviol_Din0_Din0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => Din0_ipd'last_event,
|
|
PathDelay => tpd_Din0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity Din_0_MGIOL
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity Din_0_MGIOL is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "Din_0_MGIOL";
|
|
|
|
tipd_DI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CLK : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CLK_INP : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_CLK : VitalDelayType := 0 ns;
|
|
tisd_DI_CLK : VitalDelayType := 0 ns;
|
|
tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_CLK : VitalDelayType := 0 ns;
|
|
tpw_CLK_posedge : VitalDelayType := 0 ns;
|
|
tpw_CLK_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF Din_0_MGIOL : ENTITY IS TRUE;
|
|
|
|
end Din_0_MGIOL;
|
|
|
|
architecture Structure of Din_0_MGIOL is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal DI_ipd : std_logic := 'X';
|
|
signal DI_dly : std_logic := 'X';
|
|
signal CLK_ipd : std_logic := 'X';
|
|
signal CLK_dly : std_logic := 'X';
|
|
signal INP_out : std_logic := 'X';
|
|
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component smuxlregsre
|
|
port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic;
|
|
LSR: in Std_logic; Q: out Std_logic);
|
|
end component;
|
|
begin
|
|
Bank_0io_0: smuxlregsre
|
|
port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INP_out);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(DI_ipd, DI, tipd_DI);
|
|
VitalWireDelay(CLK_ipd, CLK, tipd_CLK);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK);
|
|
VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (DI_dly, CLK_dly, INP_out)
|
|
VARIABLE INP_zd : std_logic := 'X';
|
|
VARIABLE INP_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_DI_CLK : x01 := '0';
|
|
VARIABLE DI_CLK_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_CLK_CLK : x01 := '0';
|
|
VARIABLE periodcheckinfo_CLK : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalSetupHoldCheck (
|
|
TestSignal => DI_dly,
|
|
TestSignalName => "DI",
|
|
TestDelay => tisd_DI_CLK,
|
|
RefSignal => CLK_dly,
|
|
RefSignalName => "CLK",
|
|
RefDelay => ticd_CLK,
|
|
SetupHigh => tsetup_DI_CLK_noedge_posedge,
|
|
SetupLow => tsetup_DI_CLK_noedge_posedge,
|
|
HoldHigh => thold_DI_CLK_noedge_posedge,
|
|
HoldLow => thold_DI_CLK_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => DI_CLK_TimingDatash,
|
|
Violation => tviol_DI_CLK,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CLK_ipd,
|
|
TestSignalName => "CLK",
|
|
Period => tperiod_CLK,
|
|
PulseWidthHigh => tpw_CLK_posedge,
|
|
PulseWidthLow => tpw_CLK_negedge,
|
|
PeriodData => periodcheckinfo_CLK,
|
|
Violation => tviol_CLK_CLK,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
INP_zd := INP_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => INP, OutSignalName => "INP", OutTemp => INP_zd,
|
|
Paths => (0 => (InputChangeTime => CLK_dly'last_event,
|
|
PathDelay => tpd_CLK_INP,
|
|
PathCondition => TRUE)),
|
|
GlitchData => INP_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity CROW_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity CROW_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "CROW_1_B";
|
|
|
|
tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CROW1 : VitalDelayType := 0 ns;
|
|
tpw_CROW1_posedge : VitalDelayType := 0 ns;
|
|
tpw_CROW1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; CROW1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE;
|
|
|
|
end CROW_1_B;
|
|
|
|
architecture Structure of CROW_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal CROW1_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
CROW_pad_1: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>CROW1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, CROW1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_CROW1_CROW1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CROW1_ipd,
|
|
TestSignalName => "CROW1",
|
|
Period => tperiod_CROW1,
|
|
PulseWidthHigh => tpw_CROW1_posedge,
|
|
PulseWidthLow => tpw_CROW1_negedge,
|
|
PeriodData => periodcheckinfo_CROW1,
|
|
Violation => tviol_CROW1_CROW1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => CROW1_ipd'last_event,
|
|
PathDelay => tpd_CROW1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity CROW_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity CROW_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "CROW_0_B";
|
|
|
|
tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_CROW0 : VitalDelayType := 0 ns;
|
|
tpw_CROW0_posedge : VitalDelayType := 0 ns;
|
|
tpw_CROW0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; CROW0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE;
|
|
|
|
end CROW_0_B;
|
|
|
|
architecture Structure of CROW_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal CROW0_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
CROW_pad_0: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>CROW0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, CROW0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_CROW0_CROW0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => CROW0_ipd,
|
|
TestSignalName => "CROW0",
|
|
Period => tperiod_CROW0,
|
|
PulseWidthHigh => tpw_CROW0_posedge,
|
|
PulseWidthLow => tpw_CROW0_negedge,
|
|
PeriodData => periodcheckinfo_CROW0,
|
|
Violation => tviol_CROW0_CROW0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => CROW0_ipd'last_event,
|
|
PathDelay => tpd_CROW0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_9_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_9_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_9_B";
|
|
|
|
tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin9 : VitalDelayType := 0 ns;
|
|
tpw_MAin9_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin9_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin9: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE;
|
|
|
|
end MAin_9_B;
|
|
|
|
architecture Structure of MAin_9_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin9_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_9: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin9_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin9_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin9_MAin9 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin9_ipd,
|
|
TestSignalName => "MAin9",
|
|
Period => tperiod_MAin9,
|
|
PulseWidthHigh => tpw_MAin9_posedge,
|
|
PulseWidthLow => tpw_MAin9_negedge,
|
|
PeriodData => periodcheckinfo_MAin9,
|
|
Violation => tviol_MAin9_MAin9,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin9_ipd'last_event,
|
|
PathDelay => tpd_MAin9_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_8_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_8_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_8_B";
|
|
|
|
tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin8 : VitalDelayType := 0 ns;
|
|
tpw_MAin8_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin8_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin8: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE;
|
|
|
|
end MAin_8_B;
|
|
|
|
architecture Structure of MAin_8_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin8_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_8: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin8_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin8_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin8_MAin8 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin8_ipd,
|
|
TestSignalName => "MAin8",
|
|
Period => tperiod_MAin8,
|
|
PulseWidthHigh => tpw_MAin8_posedge,
|
|
PulseWidthLow => tpw_MAin8_negedge,
|
|
PeriodData => periodcheckinfo_MAin8,
|
|
Violation => tviol_MAin8_MAin8,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin8_ipd'last_event,
|
|
PathDelay => tpd_MAin8_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_7_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_7_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_7_B";
|
|
|
|
tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin7 : VitalDelayType := 0 ns;
|
|
tpw_MAin7_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin7_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin7: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE;
|
|
|
|
end MAin_7_B;
|
|
|
|
architecture Structure of MAin_7_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin7_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_7: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin7_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin7_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin7_MAin7 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin7_ipd,
|
|
TestSignalName => "MAin7",
|
|
Period => tperiod_MAin7,
|
|
PulseWidthHigh => tpw_MAin7_posedge,
|
|
PulseWidthLow => tpw_MAin7_negedge,
|
|
PeriodData => periodcheckinfo_MAin7,
|
|
Violation => tviol_MAin7_MAin7,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin7_ipd'last_event,
|
|
PathDelay => tpd_MAin7_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_6_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_6_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_6_B";
|
|
|
|
tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin6 : VitalDelayType := 0 ns;
|
|
tpw_MAin6_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin6_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin6: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE;
|
|
|
|
end MAin_6_B;
|
|
|
|
architecture Structure of MAin_6_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin6_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_6: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin6_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin6_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin6_MAin6 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin6_ipd,
|
|
TestSignalName => "MAin6",
|
|
Period => tperiod_MAin6,
|
|
PulseWidthHigh => tpw_MAin6_posedge,
|
|
PulseWidthLow => tpw_MAin6_negedge,
|
|
PeriodData => periodcheckinfo_MAin6,
|
|
Violation => tviol_MAin6_MAin6,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin6_ipd'last_event,
|
|
PathDelay => tpd_MAin6_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_5_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_5_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_5_B";
|
|
|
|
tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin5 : VitalDelayType := 0 ns;
|
|
tpw_MAin5_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin5_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin5: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE;
|
|
|
|
end MAin_5_B;
|
|
|
|
architecture Structure of MAin_5_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin5_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_5: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin5_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin5_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin5_MAin5 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin5_ipd,
|
|
TestSignalName => "MAin5",
|
|
Period => tperiod_MAin5,
|
|
PulseWidthHigh => tpw_MAin5_posedge,
|
|
PulseWidthLow => tpw_MAin5_negedge,
|
|
PeriodData => periodcheckinfo_MAin5,
|
|
Violation => tviol_MAin5_MAin5,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin5_ipd'last_event,
|
|
PathDelay => tpd_MAin5_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_4_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_4_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_4_B";
|
|
|
|
tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin4 : VitalDelayType := 0 ns;
|
|
tpw_MAin4_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin4_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin4: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE;
|
|
|
|
end MAin_4_B;
|
|
|
|
architecture Structure of MAin_4_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin4_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_4: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin4_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin4_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin4_MAin4 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin4_ipd,
|
|
TestSignalName => "MAin4",
|
|
Period => tperiod_MAin4,
|
|
PulseWidthHigh => tpw_MAin4_posedge,
|
|
PulseWidthLow => tpw_MAin4_negedge,
|
|
PeriodData => periodcheckinfo_MAin4,
|
|
Violation => tviol_MAin4_MAin4,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin4_ipd'last_event,
|
|
PathDelay => tpd_MAin4_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_3_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_3_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_3_B";
|
|
|
|
tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin3 : VitalDelayType := 0 ns;
|
|
tpw_MAin3_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin3_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin3: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE;
|
|
|
|
end MAin_3_B;
|
|
|
|
architecture Structure of MAin_3_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin3_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_3: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin3_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin3_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin3_MAin3 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin3_ipd,
|
|
TestSignalName => "MAin3",
|
|
Period => tperiod_MAin3,
|
|
PulseWidthHigh => tpw_MAin3_posedge,
|
|
PulseWidthLow => tpw_MAin3_negedge,
|
|
PeriodData => periodcheckinfo_MAin3,
|
|
Violation => tviol_MAin3_MAin3,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin3_ipd'last_event,
|
|
PathDelay => tpd_MAin3_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_2_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_2_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_2_B";
|
|
|
|
tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin2 : VitalDelayType := 0 ns;
|
|
tpw_MAin2_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin2_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin2: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE;
|
|
|
|
end MAin_2_B;
|
|
|
|
architecture Structure of MAin_2_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin2_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_2: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin2_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin2_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin2_MAin2 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin2_ipd,
|
|
TestSignalName => "MAin2",
|
|
Period => tperiod_MAin2,
|
|
PulseWidthHigh => tpw_MAin2_posedge,
|
|
PulseWidthLow => tpw_MAin2_negedge,
|
|
PeriodData => periodcheckinfo_MAin2,
|
|
Violation => tviol_MAin2_MAin2,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin2_ipd'last_event,
|
|
PathDelay => tpd_MAin2_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_1_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_1_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_1_B";
|
|
|
|
tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin1 : VitalDelayType := 0 ns;
|
|
tpw_MAin1_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin1_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin1: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE;
|
|
|
|
end MAin_1_B;
|
|
|
|
architecture Structure of MAin_1_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin1_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_1: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin1_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin1_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin1_MAin1 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin1_ipd,
|
|
TestSignalName => "MAin1",
|
|
Period => tperiod_MAin1,
|
|
PulseWidthHigh => tpw_MAin1_posedge,
|
|
PulseWidthLow => tpw_MAin1_negedge,
|
|
PeriodData => periodcheckinfo_MAin1,
|
|
Violation => tviol_MAin1_MAin1,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin1_ipd'last_event,
|
|
PathDelay => tpd_MAin1_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity MAin_0_B
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity MAin_0_B is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "MAin_0_B";
|
|
|
|
tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns);
|
|
tperiod_MAin0 : VitalDelayType := 0 ns;
|
|
tpw_MAin0_posedge : VitalDelayType := 0 ns;
|
|
tpw_MAin0_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (PADDI: out Std_logic; MAin0: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE;
|
|
|
|
end MAin_0_B;
|
|
|
|
architecture Structure of MAin_0_B is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal PADDI_out : std_logic := 'X';
|
|
signal MAin0_ipd : std_logic := 'X';
|
|
|
|
component xo2iobuf0113
|
|
port (Z: out Std_logic; PAD: in Std_logic);
|
|
end component;
|
|
begin
|
|
MAin_pad_0: xo2iobuf0113
|
|
port map (Z=>PADDI_out, PAD=>MAin0_ipd);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (PADDI_out, MAin0_ipd)
|
|
VARIABLE PADDI_zd : std_logic := 'X';
|
|
VARIABLE PADDI_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_MAin0_MAin0 : x01 := '0';
|
|
VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType;
|
|
|
|
BEGIN
|
|
|
|
IF (TimingChecksOn) THEN
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => MAin0_ipd,
|
|
TestSignalName => "MAin0",
|
|
Period => tperiod_MAin0,
|
|
PulseWidthHigh => tpw_MAin0_posedge,
|
|
PulseWidthLow => tpw_MAin0_negedge,
|
|
PeriodData => periodcheckinfo_MAin0,
|
|
Violation => tviol_MAin0_MAin0,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
PADDI_zd := PADDI_out;
|
|
|
|
VitalPathDelay01 (
|
|
OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd,
|
|
Paths => (0 => (InputChangeTime => MAin0_ipd'last_event,
|
|
PathDelay => tpd_MAin0_PADDI,
|
|
PathCondition => TRUE)),
|
|
GlitchData => PADDI_GlitchData,
|
|
Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity EFB_Buffer_Block
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity EFB_Buffer_Block is
|
|
-- miscellaneous vital GENERICs
|
|
GENERIC (
|
|
TimingChecksOn : boolean := TRUE;
|
|
XOn : boolean := FALSE;
|
|
MsgOn : boolean := TRUE;
|
|
InstancePath : string := "EFB_Buffer_Block";
|
|
|
|
tipd_WBCLKIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBRSTIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBCYCIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBSTBIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBWEIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBADRI0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATI0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0DATI0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0ACKIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1DATI0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1ACKIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1SCLIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1SDAIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2SCLIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2SDAIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPISCKIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMISOIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMOSIIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPISCSNin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_TCCLKIin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_TCRSTNin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_TCICin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_UFMSNin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBDATO0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBACKOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLCLKOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLRSTOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL0STBOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLL1STBOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLWEOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLADRO4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLADRO3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLADRO2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLADRO1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLADRO0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_PLLDATO0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1SCLOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1SCLOENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1SDAOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1SDAOENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2SCLOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2SCLOENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2SDAOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2SDAOENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C1IRQOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_I2C2IRQOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPISCKOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPISCKENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMISOOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMISOENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMOSIOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMOSIENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN0in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN1in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN2in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN3in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN4in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN5in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN6in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIMCSN7in : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPICSNENin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_SPIIRQOin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_TCINTin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_TCOCin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_WBCUFMIRQin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CFGWAKEin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tipd_CFGSTDBYin : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_WBCLKIin_WBDATO0out : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_WBCLKIin_WBDATO1out : VitalDelayType01 := (0 ns, 0 ns);
|
|
tpd_WBCLKIin_WBACKOout : VitalDelayType01 := (0 ns, 0 ns);
|
|
ticd_WBCLKIin : VitalDelayType := 0 ns;
|
|
tisd_WBRSTIin_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBRSTIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBRSTIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBCYCIin_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBCYCIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBCYCIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBSTBIin_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBSTBIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBSTBIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBWEIin_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBWEIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBWEIin_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI0in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI1in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI2in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI3in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI4in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI5in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI6in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBADRI7in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBADRI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBADRI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI0in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI0in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI1in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI1in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI2in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI2in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI3in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI3in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI4in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI4in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI5in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI5in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI6in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI6in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tisd_WBDATI7in_WBCLKIin : VitalDelayType := 0 ns;
|
|
tsetup_WBDATI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
thold_WBDATI7in_WBCLKIin_noedge_posedge : VitalDelayType := 0 ns;
|
|
tperiod_WBCLKIin : VitalDelayType := 0 ns;
|
|
tpw_WBCLKIin_posedge : VitalDelayType := 0 ns;
|
|
tpw_WBCLKIin_negedge : VitalDelayType := 0 ns);
|
|
|
|
port (WBCLKIin: in Std_logic; WBCLKIout: out Std_logic;
|
|
WBRSTIin: in Std_logic; WBRSTIout: out Std_logic;
|
|
WBCYCIin: in Std_logic; WBCYCIout: out Std_logic;
|
|
WBSTBIin: in Std_logic; WBSTBIout: out Std_logic;
|
|
WBWEIin: in Std_logic; WBWEIout: out Std_logic;
|
|
WBADRI7in: in Std_logic; WBADRI7out: out Std_logic;
|
|
WBADRI6in: in Std_logic; WBADRI6out: out Std_logic;
|
|
WBADRI5in: in Std_logic; WBADRI5out: out Std_logic;
|
|
WBADRI4in: in Std_logic; WBADRI4out: out Std_logic;
|
|
WBADRI3in: in Std_logic; WBADRI3out: out Std_logic;
|
|
WBADRI2in: in Std_logic; WBADRI2out: out Std_logic;
|
|
WBADRI1in: in Std_logic; WBADRI1out: out Std_logic;
|
|
WBADRI0in: in Std_logic; WBADRI0out: out Std_logic;
|
|
WBDATI7in: in Std_logic; WBDATI7out: out Std_logic;
|
|
WBDATI6in: in Std_logic; WBDATI6out: out Std_logic;
|
|
WBDATI5in: in Std_logic; WBDATI5out: out Std_logic;
|
|
WBDATI4in: in Std_logic; WBDATI4out: out Std_logic;
|
|
WBDATI3in: in Std_logic; WBDATI3out: out Std_logic;
|
|
WBDATI2in: in Std_logic; WBDATI2out: out Std_logic;
|
|
WBDATI1in: in Std_logic; WBDATI1out: out Std_logic;
|
|
WBDATI0in: in Std_logic; WBDATI0out: out Std_logic;
|
|
PLL0DATI7in: in Std_logic; PLL0DATI7out: out Std_logic;
|
|
PLL0DATI6in: in Std_logic; PLL0DATI6out: out Std_logic;
|
|
PLL0DATI5in: in Std_logic; PLL0DATI5out: out Std_logic;
|
|
PLL0DATI4in: in Std_logic; PLL0DATI4out: out Std_logic;
|
|
PLL0DATI3in: in Std_logic; PLL0DATI3out: out Std_logic;
|
|
PLL0DATI2in: in Std_logic; PLL0DATI2out: out Std_logic;
|
|
PLL0DATI1in: in Std_logic; PLL0DATI1out: out Std_logic;
|
|
PLL0DATI0in: in Std_logic; PLL0DATI0out: out Std_logic;
|
|
PLL0ACKIin: in Std_logic; PLL0ACKIout: out Std_logic;
|
|
PLL1DATI7in: in Std_logic; PLL1DATI7out: out Std_logic;
|
|
PLL1DATI6in: in Std_logic; PLL1DATI6out: out Std_logic;
|
|
PLL1DATI5in: in Std_logic; PLL1DATI5out: out Std_logic;
|
|
PLL1DATI4in: in Std_logic; PLL1DATI4out: out Std_logic;
|
|
PLL1DATI3in: in Std_logic; PLL1DATI3out: out Std_logic;
|
|
PLL1DATI2in: in Std_logic; PLL1DATI2out: out Std_logic;
|
|
PLL1DATI1in: in Std_logic; PLL1DATI1out: out Std_logic;
|
|
PLL1DATI0in: in Std_logic; PLL1DATI0out: out Std_logic;
|
|
PLL1ACKIin: in Std_logic; PLL1ACKIout: out Std_logic;
|
|
I2C1SCLIin: in Std_logic; I2C1SCLIout: out Std_logic;
|
|
I2C1SDAIin: in Std_logic; I2C1SDAIout: out Std_logic;
|
|
I2C2SCLIin: in Std_logic; I2C2SCLIout: out Std_logic;
|
|
I2C2SDAIin: in Std_logic; I2C2SDAIout: out Std_logic;
|
|
SPISCKIin: in Std_logic; SPISCKIout: out Std_logic;
|
|
SPIMISOIin: in Std_logic; SPIMISOIout: out Std_logic;
|
|
SPIMOSIIin: in Std_logic; SPIMOSIIout: out Std_logic;
|
|
SPISCSNin: in Std_logic; SPISCSNout: out Std_logic;
|
|
TCCLKIin: in Std_logic; TCCLKIout: out Std_logic;
|
|
TCRSTNin: in Std_logic; TCRSTNout: out Std_logic;
|
|
TCICin: in Std_logic; TCICout: out Std_logic; UFMSNin: in Std_logic;
|
|
UFMSNout: out Std_logic; WBDATO7out: out Std_logic;
|
|
WBDATO7in: in Std_logic; WBDATO6out: out Std_logic;
|
|
WBDATO6in: in Std_logic; WBDATO5out: out Std_logic;
|
|
WBDATO5in: in Std_logic; WBDATO4out: out Std_logic;
|
|
WBDATO4in: in Std_logic; WBDATO3out: out Std_logic;
|
|
WBDATO3in: in Std_logic; WBDATO2out: out Std_logic;
|
|
WBDATO2in: in Std_logic; WBDATO1out: out Std_logic;
|
|
WBDATO1in: in Std_logic; WBDATO0out: out Std_logic;
|
|
WBDATO0in: in Std_logic; WBACKOout: out Std_logic;
|
|
WBACKOin: in Std_logic; PLLCLKOout: out Std_logic;
|
|
PLLCLKOin: in Std_logic; PLLRSTOout: out Std_logic;
|
|
PLLRSTOin: in Std_logic; PLL0STBOout: out Std_logic;
|
|
PLL0STBOin: in Std_logic; PLL1STBOout: out Std_logic;
|
|
PLL1STBOin: in Std_logic; PLLWEOout: out Std_logic;
|
|
PLLWEOin: in Std_logic; PLLADRO4out: out Std_logic;
|
|
PLLADRO4in: in Std_logic; PLLADRO3out: out Std_logic;
|
|
PLLADRO3in: in Std_logic; PLLADRO2out: out Std_logic;
|
|
PLLADRO2in: in Std_logic; PLLADRO1out: out Std_logic;
|
|
PLLADRO1in: in Std_logic; PLLADRO0out: out Std_logic;
|
|
PLLADRO0in: in Std_logic; PLLDATO7out: out Std_logic;
|
|
PLLDATO7in: in Std_logic; PLLDATO6out: out Std_logic;
|
|
PLLDATO6in: in Std_logic; PLLDATO5out: out Std_logic;
|
|
PLLDATO5in: in Std_logic; PLLDATO4out: out Std_logic;
|
|
PLLDATO4in: in Std_logic; PLLDATO3out: out Std_logic;
|
|
PLLDATO3in: in Std_logic; PLLDATO2out: out Std_logic;
|
|
PLLDATO2in: in Std_logic; PLLDATO1out: out Std_logic;
|
|
PLLDATO1in: in Std_logic; PLLDATO0out: out Std_logic;
|
|
PLLDATO0in: in Std_logic; I2C1SCLOout: out Std_logic;
|
|
I2C1SCLOin: in Std_logic; I2C1SCLOENout: out Std_logic;
|
|
I2C1SCLOENin: in Std_logic; I2C1SDAOout: out Std_logic;
|
|
I2C1SDAOin: in Std_logic; I2C1SDAOENout: out Std_logic;
|
|
I2C1SDAOENin: in Std_logic; I2C2SCLOout: out Std_logic;
|
|
I2C2SCLOin: in Std_logic; I2C2SCLOENout: out Std_logic;
|
|
I2C2SCLOENin: in Std_logic; I2C2SDAOout: out Std_logic;
|
|
I2C2SDAOin: in Std_logic; I2C2SDAOENout: out Std_logic;
|
|
I2C2SDAOENin: in Std_logic; I2C1IRQOout: out Std_logic;
|
|
I2C1IRQOin: in Std_logic; I2C2IRQOout: out Std_logic;
|
|
I2C2IRQOin: in Std_logic; SPISCKOout: out Std_logic;
|
|
SPISCKOin: in Std_logic; SPISCKENout: out Std_logic;
|
|
SPISCKENin: in Std_logic; SPIMISOOout: out Std_logic;
|
|
SPIMISOOin: in Std_logic; SPIMISOENout: out Std_logic;
|
|
SPIMISOENin: in Std_logic; SPIMOSIOout: out Std_logic;
|
|
SPIMOSIOin: in Std_logic; SPIMOSIENout: out Std_logic;
|
|
SPIMOSIENin: in Std_logic; SPIMCSN0out: out Std_logic;
|
|
SPIMCSN0in: in Std_logic; SPIMCSN1out: out Std_logic;
|
|
SPIMCSN1in: in Std_logic; SPIMCSN2out: out Std_logic;
|
|
SPIMCSN2in: in Std_logic; SPIMCSN3out: out Std_logic;
|
|
SPIMCSN3in: in Std_logic; SPIMCSN4out: out Std_logic;
|
|
SPIMCSN4in: in Std_logic; SPIMCSN5out: out Std_logic;
|
|
SPIMCSN5in: in Std_logic; SPIMCSN6out: out Std_logic;
|
|
SPIMCSN6in: in Std_logic; SPIMCSN7out: out Std_logic;
|
|
SPIMCSN7in: in Std_logic; SPICSNENout: out Std_logic;
|
|
SPICSNENin: in Std_logic; SPIIRQOout: out Std_logic;
|
|
SPIIRQOin: in Std_logic; TCINTout: out Std_logic;
|
|
TCINTin: in Std_logic; TCOCout: out Std_logic; TCOCin: in Std_logic;
|
|
WBCUFMIRQout: out Std_logic; WBCUFMIRQin: in Std_logic;
|
|
CFGWAKEout: out Std_logic; CFGWAKEin: in Std_logic;
|
|
CFGSTDBYout: out Std_logic; CFGSTDBYin: in Std_logic);
|
|
|
|
ATTRIBUTE Vital_Level0 OF EFB_Buffer_Block : ENTITY IS TRUE;
|
|
|
|
end EFB_Buffer_Block;
|
|
|
|
architecture Structure of EFB_Buffer_Block is
|
|
ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE;
|
|
|
|
signal WBCLKIin_ipd : std_logic := 'X';
|
|
signal WBCLKIin_dly : std_logic := 'X';
|
|
signal WBCLKIout_out : std_logic := 'X';
|
|
signal WBRSTIin_ipd : std_logic := 'X';
|
|
signal WBRSTIin_dly : std_logic := 'X';
|
|
signal WBRSTIout_out : std_logic := 'X';
|
|
signal WBCYCIin_ipd : std_logic := 'X';
|
|
signal WBCYCIin_dly : std_logic := 'X';
|
|
signal WBCYCIout_out : std_logic := 'X';
|
|
signal WBSTBIin_ipd : std_logic := 'X';
|
|
signal WBSTBIin_dly : std_logic := 'X';
|
|
signal WBSTBIout_out : std_logic := 'X';
|
|
signal WBWEIin_ipd : std_logic := 'X';
|
|
signal WBWEIin_dly : std_logic := 'X';
|
|
signal WBWEIout_out : std_logic := 'X';
|
|
signal WBADRI7in_ipd : std_logic := 'X';
|
|
signal WBADRI7in_dly : std_logic := 'X';
|
|
signal WBADRI7out_out : std_logic := 'X';
|
|
signal WBADRI6in_ipd : std_logic := 'X';
|
|
signal WBADRI6in_dly : std_logic := 'X';
|
|
signal WBADRI6out_out : std_logic := 'X';
|
|
signal WBADRI5in_ipd : std_logic := 'X';
|
|
signal WBADRI5in_dly : std_logic := 'X';
|
|
signal WBADRI5out_out : std_logic := 'X';
|
|
signal WBADRI4in_ipd : std_logic := 'X';
|
|
signal WBADRI4in_dly : std_logic := 'X';
|
|
signal WBADRI4out_out : std_logic := 'X';
|
|
signal WBADRI3in_ipd : std_logic := 'X';
|
|
signal WBADRI3in_dly : std_logic := 'X';
|
|
signal WBADRI3out_out : std_logic := 'X';
|
|
signal WBADRI2in_ipd : std_logic := 'X';
|
|
signal WBADRI2in_dly : std_logic := 'X';
|
|
signal WBADRI2out_out : std_logic := 'X';
|
|
signal WBADRI1in_ipd : std_logic := 'X';
|
|
signal WBADRI1in_dly : std_logic := 'X';
|
|
signal WBADRI1out_out : std_logic := 'X';
|
|
signal WBADRI0in_ipd : std_logic := 'X';
|
|
signal WBADRI0in_dly : std_logic := 'X';
|
|
signal WBADRI0out_out : std_logic := 'X';
|
|
signal WBDATI7in_ipd : std_logic := 'X';
|
|
signal WBDATI7in_dly : std_logic := 'X';
|
|
signal WBDATI7out_out : std_logic := 'X';
|
|
signal WBDATI6in_ipd : std_logic := 'X';
|
|
signal WBDATI6in_dly : std_logic := 'X';
|
|
signal WBDATI6out_out : std_logic := 'X';
|
|
signal WBDATI5in_ipd : std_logic := 'X';
|
|
signal WBDATI5in_dly : std_logic := 'X';
|
|
signal WBDATI5out_out : std_logic := 'X';
|
|
signal WBDATI4in_ipd : std_logic := 'X';
|
|
signal WBDATI4in_dly : std_logic := 'X';
|
|
signal WBDATI4out_out : std_logic := 'X';
|
|
signal WBDATI3in_ipd : std_logic := 'X';
|
|
signal WBDATI3in_dly : std_logic := 'X';
|
|
signal WBDATI3out_out : std_logic := 'X';
|
|
signal WBDATI2in_ipd : std_logic := 'X';
|
|
signal WBDATI2in_dly : std_logic := 'X';
|
|
signal WBDATI2out_out : std_logic := 'X';
|
|
signal WBDATI1in_ipd : std_logic := 'X';
|
|
signal WBDATI1in_dly : std_logic := 'X';
|
|
signal WBDATI1out_out : std_logic := 'X';
|
|
signal WBDATI0in_ipd : std_logic := 'X';
|
|
signal WBDATI0in_dly : std_logic := 'X';
|
|
signal WBDATI0out_out : std_logic := 'X';
|
|
signal PLL0DATI7in_ipd : std_logic := 'X';
|
|
signal PLL0DATI7out_out : std_logic := 'X';
|
|
signal PLL0DATI6in_ipd : std_logic := 'X';
|
|
signal PLL0DATI6out_out : std_logic := 'X';
|
|
signal PLL0DATI5in_ipd : std_logic := 'X';
|
|
signal PLL0DATI5out_out : std_logic := 'X';
|
|
signal PLL0DATI4in_ipd : std_logic := 'X';
|
|
signal PLL0DATI4out_out : std_logic := 'X';
|
|
signal PLL0DATI3in_ipd : std_logic := 'X';
|
|
signal PLL0DATI3out_out : std_logic := 'X';
|
|
signal PLL0DATI2in_ipd : std_logic := 'X';
|
|
signal PLL0DATI2out_out : std_logic := 'X';
|
|
signal PLL0DATI1in_ipd : std_logic := 'X';
|
|
signal PLL0DATI1out_out : std_logic := 'X';
|
|
signal PLL0DATI0in_ipd : std_logic := 'X';
|
|
signal PLL0DATI0out_out : std_logic := 'X';
|
|
signal PLL0ACKIin_ipd : std_logic := 'X';
|
|
signal PLL0ACKIout_out : std_logic := 'X';
|
|
signal PLL1DATI7in_ipd : std_logic := 'X';
|
|
signal PLL1DATI7out_out : std_logic := 'X';
|
|
signal PLL1DATI6in_ipd : std_logic := 'X';
|
|
signal PLL1DATI6out_out : std_logic := 'X';
|
|
signal PLL1DATI5in_ipd : std_logic := 'X';
|
|
signal PLL1DATI5out_out : std_logic := 'X';
|
|
signal PLL1DATI4in_ipd : std_logic := 'X';
|
|
signal PLL1DATI4out_out : std_logic := 'X';
|
|
signal PLL1DATI3in_ipd : std_logic := 'X';
|
|
signal PLL1DATI3out_out : std_logic := 'X';
|
|
signal PLL1DATI2in_ipd : std_logic := 'X';
|
|
signal PLL1DATI2out_out : std_logic := 'X';
|
|
signal PLL1DATI1in_ipd : std_logic := 'X';
|
|
signal PLL1DATI1out_out : std_logic := 'X';
|
|
signal PLL1DATI0in_ipd : std_logic := 'X';
|
|
signal PLL1DATI0out_out : std_logic := 'X';
|
|
signal PLL1ACKIin_ipd : std_logic := 'X';
|
|
signal PLL1ACKIout_out : std_logic := 'X';
|
|
signal I2C1SCLIin_ipd : std_logic := 'X';
|
|
signal I2C1SCLIout_out : std_logic := 'X';
|
|
signal I2C1SDAIin_ipd : std_logic := 'X';
|
|
signal I2C1SDAIout_out : std_logic := 'X';
|
|
signal I2C2SCLIin_ipd : std_logic := 'X';
|
|
signal I2C2SCLIout_out : std_logic := 'X';
|
|
signal I2C2SDAIin_ipd : std_logic := 'X';
|
|
signal I2C2SDAIout_out : std_logic := 'X';
|
|
signal SPISCKIin_ipd : std_logic := 'X';
|
|
signal SPISCKIout_out : std_logic := 'X';
|
|
signal SPIMISOIin_ipd : std_logic := 'X';
|
|
signal SPIMISOIout_out : std_logic := 'X';
|
|
signal SPIMOSIIin_ipd : std_logic := 'X';
|
|
signal SPIMOSIIout_out : std_logic := 'X';
|
|
signal SPISCSNin_ipd : std_logic := 'X';
|
|
signal SPISCSNout_out : std_logic := 'X';
|
|
signal TCCLKIin_ipd : std_logic := 'X';
|
|
signal TCCLKIout_out : std_logic := 'X';
|
|
signal TCRSTNin_ipd : std_logic := 'X';
|
|
signal TCRSTNout_out : std_logic := 'X';
|
|
signal TCICin_ipd : std_logic := 'X';
|
|
signal TCICout_out : std_logic := 'X';
|
|
signal UFMSNin_ipd : std_logic := 'X';
|
|
signal UFMSNout_out : std_logic := 'X';
|
|
signal WBDATO7out_out : std_logic := 'X';
|
|
signal WBDATO7in_ipd : std_logic := 'X';
|
|
signal WBDATO6out_out : std_logic := 'X';
|
|
signal WBDATO6in_ipd : std_logic := 'X';
|
|
signal WBDATO5out_out : std_logic := 'X';
|
|
signal WBDATO5in_ipd : std_logic := 'X';
|
|
signal WBDATO4out_out : std_logic := 'X';
|
|
signal WBDATO4in_ipd : std_logic := 'X';
|
|
signal WBDATO3out_out : std_logic := 'X';
|
|
signal WBDATO3in_ipd : std_logic := 'X';
|
|
signal WBDATO2out_out : std_logic := 'X';
|
|
signal WBDATO2in_ipd : std_logic := 'X';
|
|
signal WBDATO1out_out : std_logic := 'X';
|
|
signal WBDATO1in_ipd : std_logic := 'X';
|
|
signal WBDATO0out_out : std_logic := 'X';
|
|
signal WBDATO0in_ipd : std_logic := 'X';
|
|
signal WBACKOout_out : std_logic := 'X';
|
|
signal WBACKOin_ipd : std_logic := 'X';
|
|
signal PLLCLKOout_out : std_logic := 'X';
|
|
signal PLLCLKOin_ipd : std_logic := 'X';
|
|
signal PLLRSTOout_out : std_logic := 'X';
|
|
signal PLLRSTOin_ipd : std_logic := 'X';
|
|
signal PLL0STBOout_out : std_logic := 'X';
|
|
signal PLL0STBOin_ipd : std_logic := 'X';
|
|
signal PLL1STBOout_out : std_logic := 'X';
|
|
signal PLL1STBOin_ipd : std_logic := 'X';
|
|
signal PLLWEOout_out : std_logic := 'X';
|
|
signal PLLWEOin_ipd : std_logic := 'X';
|
|
signal PLLADRO4out_out : std_logic := 'X';
|
|
signal PLLADRO4in_ipd : std_logic := 'X';
|
|
signal PLLADRO3out_out : std_logic := 'X';
|
|
signal PLLADRO3in_ipd : std_logic := 'X';
|
|
signal PLLADRO2out_out : std_logic := 'X';
|
|
signal PLLADRO2in_ipd : std_logic := 'X';
|
|
signal PLLADRO1out_out : std_logic := 'X';
|
|
signal PLLADRO1in_ipd : std_logic := 'X';
|
|
signal PLLADRO0out_out : std_logic := 'X';
|
|
signal PLLADRO0in_ipd : std_logic := 'X';
|
|
signal PLLDATO7out_out : std_logic := 'X';
|
|
signal PLLDATO7in_ipd : std_logic := 'X';
|
|
signal PLLDATO6out_out : std_logic := 'X';
|
|
signal PLLDATO6in_ipd : std_logic := 'X';
|
|
signal PLLDATO5out_out : std_logic := 'X';
|
|
signal PLLDATO5in_ipd : std_logic := 'X';
|
|
signal PLLDATO4out_out : std_logic := 'X';
|
|
signal PLLDATO4in_ipd : std_logic := 'X';
|
|
signal PLLDATO3out_out : std_logic := 'X';
|
|
signal PLLDATO3in_ipd : std_logic := 'X';
|
|
signal PLLDATO2out_out : std_logic := 'X';
|
|
signal PLLDATO2in_ipd : std_logic := 'X';
|
|
signal PLLDATO1out_out : std_logic := 'X';
|
|
signal PLLDATO1in_ipd : std_logic := 'X';
|
|
signal PLLDATO0out_out : std_logic := 'X';
|
|
signal PLLDATO0in_ipd : std_logic := 'X';
|
|
signal I2C1SCLOout_out : std_logic := 'X';
|
|
signal I2C1SCLOin_ipd : std_logic := 'X';
|
|
signal I2C1SCLOENout_out : std_logic := 'X';
|
|
signal I2C1SCLOENin_ipd : std_logic := 'X';
|
|
signal I2C1SDAOout_out : std_logic := 'X';
|
|
signal I2C1SDAOin_ipd : std_logic := 'X';
|
|
signal I2C1SDAOENout_out : std_logic := 'X';
|
|
signal I2C1SDAOENin_ipd : std_logic := 'X';
|
|
signal I2C2SCLOout_out : std_logic := 'X';
|
|
signal I2C2SCLOin_ipd : std_logic := 'X';
|
|
signal I2C2SCLOENout_out : std_logic := 'X';
|
|
signal I2C2SCLOENin_ipd : std_logic := 'X';
|
|
signal I2C2SDAOout_out : std_logic := 'X';
|
|
signal I2C2SDAOin_ipd : std_logic := 'X';
|
|
signal I2C2SDAOENout_out : std_logic := 'X';
|
|
signal I2C2SDAOENin_ipd : std_logic := 'X';
|
|
signal I2C1IRQOout_out : std_logic := 'X';
|
|
signal I2C1IRQOin_ipd : std_logic := 'X';
|
|
signal I2C2IRQOout_out : std_logic := 'X';
|
|
signal I2C2IRQOin_ipd : std_logic := 'X';
|
|
signal SPISCKOout_out : std_logic := 'X';
|
|
signal SPISCKOin_ipd : std_logic := 'X';
|
|
signal SPISCKENout_out : std_logic := 'X';
|
|
signal SPISCKENin_ipd : std_logic := 'X';
|
|
signal SPIMISOOout_out : std_logic := 'X';
|
|
signal SPIMISOOin_ipd : std_logic := 'X';
|
|
signal SPIMISOENout_out : std_logic := 'X';
|
|
signal SPIMISOENin_ipd : std_logic := 'X';
|
|
signal SPIMOSIOout_out : std_logic := 'X';
|
|
signal SPIMOSIOin_ipd : std_logic := 'X';
|
|
signal SPIMOSIENout_out : std_logic := 'X';
|
|
signal SPIMOSIENin_ipd : std_logic := 'X';
|
|
signal SPIMCSN0out_out : std_logic := 'X';
|
|
signal SPIMCSN0in_ipd : std_logic := 'X';
|
|
signal SPIMCSN1out_out : std_logic := 'X';
|
|
signal SPIMCSN1in_ipd : std_logic := 'X';
|
|
signal SPIMCSN2out_out : std_logic := 'X';
|
|
signal SPIMCSN2in_ipd : std_logic := 'X';
|
|
signal SPIMCSN3out_out : std_logic := 'X';
|
|
signal SPIMCSN3in_ipd : std_logic := 'X';
|
|
signal SPIMCSN4out_out : std_logic := 'X';
|
|
signal SPIMCSN4in_ipd : std_logic := 'X';
|
|
signal SPIMCSN5out_out : std_logic := 'X';
|
|
signal SPIMCSN5in_ipd : std_logic := 'X';
|
|
signal SPIMCSN6out_out : std_logic := 'X';
|
|
signal SPIMCSN6in_ipd : std_logic := 'X';
|
|
signal SPIMCSN7out_out : std_logic := 'X';
|
|
signal SPIMCSN7in_ipd : std_logic := 'X';
|
|
signal SPICSNENout_out : std_logic := 'X';
|
|
signal SPICSNENin_ipd : std_logic := 'X';
|
|
signal SPIIRQOout_out : std_logic := 'X';
|
|
signal SPIIRQOin_ipd : std_logic := 'X';
|
|
signal TCINTout_out : std_logic := 'X';
|
|
signal TCINTin_ipd : std_logic := 'X';
|
|
signal TCOCout_out : std_logic := 'X';
|
|
signal TCOCin_ipd : std_logic := 'X';
|
|
signal WBCUFMIRQout_out : std_logic := 'X';
|
|
signal WBCUFMIRQin_ipd : std_logic := 'X';
|
|
signal CFGWAKEout_out : std_logic := 'X';
|
|
signal CFGWAKEin_ipd : std_logic := 'X';
|
|
signal CFGSTDBYout_out : std_logic := 'X';
|
|
signal CFGSTDBYin_ipd : std_logic := 'X';
|
|
|
|
begin
|
|
WBCLKI_buf: BUFBA
|
|
port map (A=>WBCLKIin_dly, Z=>WBCLKIout_out);
|
|
WBRSTI_buf: BUFBA
|
|
port map (A=>WBRSTIin_dly, Z=>WBRSTIout_out);
|
|
WBCYCI_buf: BUFBA
|
|
port map (A=>WBCYCIin_dly, Z=>WBCYCIout_out);
|
|
WBSTBI_buf: BUFBA
|
|
port map (A=>WBSTBIin_dly, Z=>WBSTBIout_out);
|
|
WBWEI_buf: BUFBA
|
|
port map (A=>WBWEIin_dly, Z=>WBWEIout_out);
|
|
WBADRI7_buf: BUFBA
|
|
port map (A=>WBADRI7in_dly, Z=>WBADRI7out_out);
|
|
WBADRI6_buf: BUFBA
|
|
port map (A=>WBADRI6in_dly, Z=>WBADRI6out_out);
|
|
WBADRI5_buf: BUFBA
|
|
port map (A=>WBADRI5in_dly, Z=>WBADRI5out_out);
|
|
WBADRI4_buf: BUFBA
|
|
port map (A=>WBADRI4in_dly, Z=>WBADRI4out_out);
|
|
WBADRI3_buf: BUFBA
|
|
port map (A=>WBADRI3in_dly, Z=>WBADRI3out_out);
|
|
WBADRI2_buf: BUFBA
|
|
port map (A=>WBADRI2in_dly, Z=>WBADRI2out_out);
|
|
WBADRI1_buf: BUFBA
|
|
port map (A=>WBADRI1in_dly, Z=>WBADRI1out_out);
|
|
WBADRI0_buf: BUFBA
|
|
port map (A=>WBADRI0in_dly, Z=>WBADRI0out_out);
|
|
WBDATI7_buf: BUFBA
|
|
port map (A=>WBDATI7in_dly, Z=>WBDATI7out_out);
|
|
WBDATI6_buf: BUFBA
|
|
port map (A=>WBDATI6in_dly, Z=>WBDATI6out_out);
|
|
WBDATI5_buf: BUFBA
|
|
port map (A=>WBDATI5in_dly, Z=>WBDATI5out_out);
|
|
WBDATI4_buf: BUFBA
|
|
port map (A=>WBDATI4in_dly, Z=>WBDATI4out_out);
|
|
WBDATI3_buf: BUFBA
|
|
port map (A=>WBDATI3in_dly, Z=>WBDATI3out_out);
|
|
WBDATI2_buf: BUFBA
|
|
port map (A=>WBDATI2in_dly, Z=>WBDATI2out_out);
|
|
WBDATI1_buf: BUFBA
|
|
port map (A=>WBDATI1in_dly, Z=>WBDATI1out_out);
|
|
WBDATI0_buf: BUFBA
|
|
port map (A=>WBDATI0in_dly, Z=>WBDATI0out_out);
|
|
PLL0DATI7_buf: BUFBA
|
|
port map (A=>PLL0DATI7in_ipd, Z=>PLL0DATI7out_out);
|
|
PLL0DATI6_buf: BUFBA
|
|
port map (A=>PLL0DATI6in_ipd, Z=>PLL0DATI6out_out);
|
|
PLL0DATI5_buf: BUFBA
|
|
port map (A=>PLL0DATI5in_ipd, Z=>PLL0DATI5out_out);
|
|
PLL0DATI4_buf: BUFBA
|
|
port map (A=>PLL0DATI4in_ipd, Z=>PLL0DATI4out_out);
|
|
PLL0DATI3_buf: BUFBA
|
|
port map (A=>PLL0DATI3in_ipd, Z=>PLL0DATI3out_out);
|
|
PLL0DATI2_buf: BUFBA
|
|
port map (A=>PLL0DATI2in_ipd, Z=>PLL0DATI2out_out);
|
|
PLL0DATI1_buf: BUFBA
|
|
port map (A=>PLL0DATI1in_ipd, Z=>PLL0DATI1out_out);
|
|
PLL0DATI0_buf: BUFBA
|
|
port map (A=>PLL0DATI0in_ipd, Z=>PLL0DATI0out_out);
|
|
PLL0ACKI_buf: BUFBA
|
|
port map (A=>PLL0ACKIin_ipd, Z=>PLL0ACKIout_out);
|
|
PLL1DATI7_buf: BUFBA
|
|
port map (A=>PLL1DATI7in_ipd, Z=>PLL1DATI7out_out);
|
|
PLL1DATI6_buf: BUFBA
|
|
port map (A=>PLL1DATI6in_ipd, Z=>PLL1DATI6out_out);
|
|
PLL1DATI5_buf: BUFBA
|
|
port map (A=>PLL1DATI5in_ipd, Z=>PLL1DATI5out_out);
|
|
PLL1DATI4_buf: BUFBA
|
|
port map (A=>PLL1DATI4in_ipd, Z=>PLL1DATI4out_out);
|
|
PLL1DATI3_buf: BUFBA
|
|
port map (A=>PLL1DATI3in_ipd, Z=>PLL1DATI3out_out);
|
|
PLL1DATI2_buf: BUFBA
|
|
port map (A=>PLL1DATI2in_ipd, Z=>PLL1DATI2out_out);
|
|
PLL1DATI1_buf: BUFBA
|
|
port map (A=>PLL1DATI1in_ipd, Z=>PLL1DATI1out_out);
|
|
PLL1DATI0_buf: BUFBA
|
|
port map (A=>PLL1DATI0in_ipd, Z=>PLL1DATI0out_out);
|
|
PLL1ACKI_buf: BUFBA
|
|
port map (A=>PLL1ACKIin_ipd, Z=>PLL1ACKIout_out);
|
|
I2C1SCLI_buf: BUFBA
|
|
port map (A=>I2C1SCLIin_ipd, Z=>I2C1SCLIout_out);
|
|
I2C1SDAI_buf: BUFBA
|
|
port map (A=>I2C1SDAIin_ipd, Z=>I2C1SDAIout_out);
|
|
I2C2SCLI_buf: BUFBA
|
|
port map (A=>I2C2SCLIin_ipd, Z=>I2C2SCLIout_out);
|
|
I2C2SDAI_buf: BUFBA
|
|
port map (A=>I2C2SDAIin_ipd, Z=>I2C2SDAIout_out);
|
|
SPISCKI_buf: BUFBA
|
|
port map (A=>SPISCKIin_ipd, Z=>SPISCKIout_out);
|
|
SPIMISOI_buf: BUFBA
|
|
port map (A=>SPIMISOIin_ipd, Z=>SPIMISOIout_out);
|
|
SPIMOSII_buf: BUFBA
|
|
port map (A=>SPIMOSIIin_ipd, Z=>SPIMOSIIout_out);
|
|
SPISCSN_buf: BUFBA
|
|
port map (A=>SPISCSNin_ipd, Z=>SPISCSNout_out);
|
|
TCCLKI_buf: BUFBA
|
|
port map (A=>TCCLKIin_ipd, Z=>TCCLKIout_out);
|
|
TCRSTN_buf: BUFBA
|
|
port map (A=>TCRSTNin_ipd, Z=>TCRSTNout_out);
|
|
TCIC_buf: BUFBA
|
|
port map (A=>TCICin_ipd, Z=>TCICout_out);
|
|
UFMSN_buf: BUFBA
|
|
port map (A=>UFMSNin_ipd, Z=>UFMSNout_out);
|
|
WBDATO7_buf: BUFBA
|
|
port map (A=>WBDATO7in_ipd, Z=>WBDATO7out_out);
|
|
WBDATO6_buf: BUFBA
|
|
port map (A=>WBDATO6in_ipd, Z=>WBDATO6out_out);
|
|
WBDATO5_buf: BUFBA
|
|
port map (A=>WBDATO5in_ipd, Z=>WBDATO5out_out);
|
|
WBDATO4_buf: BUFBA
|
|
port map (A=>WBDATO4in_ipd, Z=>WBDATO4out_out);
|
|
WBDATO3_buf: BUFBA
|
|
port map (A=>WBDATO3in_ipd, Z=>WBDATO3out_out);
|
|
WBDATO2_buf: BUFBA
|
|
port map (A=>WBDATO2in_ipd, Z=>WBDATO2out_out);
|
|
WBDATO1_buf: BUFBA
|
|
port map (A=>WBDATO1in_ipd, Z=>WBDATO1out_out);
|
|
WBDATO0_buf: BUFBA
|
|
port map (A=>WBDATO0in_ipd, Z=>WBDATO0out_out);
|
|
WBACKO_buf: BUFBA
|
|
port map (A=>WBACKOin_ipd, Z=>WBACKOout_out);
|
|
PLLCLKO_buf: BUFBA
|
|
port map (A=>PLLCLKOin_ipd, Z=>PLLCLKOout_out);
|
|
PLLRSTO_buf: BUFBA
|
|
port map (A=>PLLRSTOin_ipd, Z=>PLLRSTOout_out);
|
|
PLL0STBO_buf: BUFBA
|
|
port map (A=>PLL0STBOin_ipd, Z=>PLL0STBOout_out);
|
|
PLL1STBO_buf: BUFBA
|
|
port map (A=>PLL1STBOin_ipd, Z=>PLL1STBOout_out);
|
|
PLLWEO_buf: BUFBA
|
|
port map (A=>PLLWEOin_ipd, Z=>PLLWEOout_out);
|
|
PLLADRO4_buf: BUFBA
|
|
port map (A=>PLLADRO4in_ipd, Z=>PLLADRO4out_out);
|
|
PLLADRO3_buf: BUFBA
|
|
port map (A=>PLLADRO3in_ipd, Z=>PLLADRO3out_out);
|
|
PLLADRO2_buf: BUFBA
|
|
port map (A=>PLLADRO2in_ipd, Z=>PLLADRO2out_out);
|
|
PLLADRO1_buf: BUFBA
|
|
port map (A=>PLLADRO1in_ipd, Z=>PLLADRO1out_out);
|
|
PLLADRO0_buf: BUFBA
|
|
port map (A=>PLLADRO0in_ipd, Z=>PLLADRO0out_out);
|
|
PLLDATO7_buf: BUFBA
|
|
port map (A=>PLLDATO7in_ipd, Z=>PLLDATO7out_out);
|
|
PLLDATO6_buf: BUFBA
|
|
port map (A=>PLLDATO6in_ipd, Z=>PLLDATO6out_out);
|
|
PLLDATO5_buf: BUFBA
|
|
port map (A=>PLLDATO5in_ipd, Z=>PLLDATO5out_out);
|
|
PLLDATO4_buf: BUFBA
|
|
port map (A=>PLLDATO4in_ipd, Z=>PLLDATO4out_out);
|
|
PLLDATO3_buf: BUFBA
|
|
port map (A=>PLLDATO3in_ipd, Z=>PLLDATO3out_out);
|
|
PLLDATO2_buf: BUFBA
|
|
port map (A=>PLLDATO2in_ipd, Z=>PLLDATO2out_out);
|
|
PLLDATO1_buf: BUFBA
|
|
port map (A=>PLLDATO1in_ipd, Z=>PLLDATO1out_out);
|
|
PLLDATO0_buf: BUFBA
|
|
port map (A=>PLLDATO0in_ipd, Z=>PLLDATO0out_out);
|
|
I2C1SCLO_buf: BUFBA
|
|
port map (A=>I2C1SCLOin_ipd, Z=>I2C1SCLOout_out);
|
|
I2C1SCLOEN_buf: BUFBA
|
|
port map (A=>I2C1SCLOENin_ipd, Z=>I2C1SCLOENout_out);
|
|
I2C1SDAO_buf: BUFBA
|
|
port map (A=>I2C1SDAOin_ipd, Z=>I2C1SDAOout_out);
|
|
I2C1SDAOEN_buf: BUFBA
|
|
port map (A=>I2C1SDAOENin_ipd, Z=>I2C1SDAOENout_out);
|
|
I2C2SCLO_buf: BUFBA
|
|
port map (A=>I2C2SCLOin_ipd, Z=>I2C2SCLOout_out);
|
|
I2C2SCLOEN_buf: BUFBA
|
|
port map (A=>I2C2SCLOENin_ipd, Z=>I2C2SCLOENout_out);
|
|
I2C2SDAO_buf: BUFBA
|
|
port map (A=>I2C2SDAOin_ipd, Z=>I2C2SDAOout_out);
|
|
I2C2SDAOEN_buf: BUFBA
|
|
port map (A=>I2C2SDAOENin_ipd, Z=>I2C2SDAOENout_out);
|
|
I2C1IRQO_buf: BUFBA
|
|
port map (A=>I2C1IRQOin_ipd, Z=>I2C1IRQOout_out);
|
|
I2C2IRQO_buf: BUFBA
|
|
port map (A=>I2C2IRQOin_ipd, Z=>I2C2IRQOout_out);
|
|
SPISCKO_buf: BUFBA
|
|
port map (A=>SPISCKOin_ipd, Z=>SPISCKOout_out);
|
|
SPISCKEN_buf: BUFBA
|
|
port map (A=>SPISCKENin_ipd, Z=>SPISCKENout_out);
|
|
SPIMISOO_buf: BUFBA
|
|
port map (A=>SPIMISOOin_ipd, Z=>SPIMISOOout_out);
|
|
SPIMISOEN_buf: BUFBA
|
|
port map (A=>SPIMISOENin_ipd, Z=>SPIMISOENout_out);
|
|
SPIMOSIO_buf: BUFBA
|
|
port map (A=>SPIMOSIOin_ipd, Z=>SPIMOSIOout_out);
|
|
SPIMOSIEN_buf: BUFBA
|
|
port map (A=>SPIMOSIENin_ipd, Z=>SPIMOSIENout_out);
|
|
SPIMCSN0_buf: BUFBA
|
|
port map (A=>SPIMCSN0in_ipd, Z=>SPIMCSN0out_out);
|
|
SPIMCSN1_buf: BUFBA
|
|
port map (A=>SPIMCSN1in_ipd, Z=>SPIMCSN1out_out);
|
|
SPIMCSN2_buf: BUFBA
|
|
port map (A=>SPIMCSN2in_ipd, Z=>SPIMCSN2out_out);
|
|
SPIMCSN3_buf: BUFBA
|
|
port map (A=>SPIMCSN3in_ipd, Z=>SPIMCSN3out_out);
|
|
SPIMCSN4_buf: BUFBA
|
|
port map (A=>SPIMCSN4in_ipd, Z=>SPIMCSN4out_out);
|
|
SPIMCSN5_buf: BUFBA
|
|
port map (A=>SPIMCSN5in_ipd, Z=>SPIMCSN5out_out);
|
|
SPIMCSN6_buf: BUFBA
|
|
port map (A=>SPIMCSN6in_ipd, Z=>SPIMCSN6out_out);
|
|
SPIMCSN7_buf: BUFBA
|
|
port map (A=>SPIMCSN7in_ipd, Z=>SPIMCSN7out_out);
|
|
SPICSNEN_buf: BUFBA
|
|
port map (A=>SPICSNENin_ipd, Z=>SPICSNENout_out);
|
|
SPIIRQO_buf: BUFBA
|
|
port map (A=>SPIIRQOin_ipd, Z=>SPIIRQOout_out);
|
|
TCINT_buf: BUFBA
|
|
port map (A=>TCINTin_ipd, Z=>TCINTout_out);
|
|
TCOC_buf: BUFBA
|
|
port map (A=>TCOCin_ipd, Z=>TCOCout_out);
|
|
WBCUFMIRQ_buf: BUFBA
|
|
port map (A=>WBCUFMIRQin_ipd, Z=>WBCUFMIRQout_out);
|
|
CFGWAKE_buf: BUFBA
|
|
port map (A=>CFGWAKEin_ipd, Z=>CFGWAKEout_out);
|
|
CFGSTDBY_buf: BUFBA
|
|
port map (A=>CFGSTDBYin_ipd, Z=>CFGSTDBYout_out);
|
|
|
|
-- INPUT PATH DELAYs
|
|
WireDelay : BLOCK
|
|
BEGIN
|
|
VitalWireDelay(WBCLKIin_ipd, WBCLKIin, tipd_WBCLKIin);
|
|
VitalWireDelay(WBRSTIin_ipd, WBRSTIin, tipd_WBRSTIin);
|
|
VitalWireDelay(WBCYCIin_ipd, WBCYCIin, tipd_WBCYCIin);
|
|
VitalWireDelay(WBSTBIin_ipd, WBSTBIin, tipd_WBSTBIin);
|
|
VitalWireDelay(WBWEIin_ipd, WBWEIin, tipd_WBWEIin);
|
|
VitalWireDelay(WBADRI7in_ipd, WBADRI7in, tipd_WBADRI7in);
|
|
VitalWireDelay(WBADRI6in_ipd, WBADRI6in, tipd_WBADRI6in);
|
|
VitalWireDelay(WBADRI5in_ipd, WBADRI5in, tipd_WBADRI5in);
|
|
VitalWireDelay(WBADRI4in_ipd, WBADRI4in, tipd_WBADRI4in);
|
|
VitalWireDelay(WBADRI3in_ipd, WBADRI3in, tipd_WBADRI3in);
|
|
VitalWireDelay(WBADRI2in_ipd, WBADRI2in, tipd_WBADRI2in);
|
|
VitalWireDelay(WBADRI1in_ipd, WBADRI1in, tipd_WBADRI1in);
|
|
VitalWireDelay(WBADRI0in_ipd, WBADRI0in, tipd_WBADRI0in);
|
|
VitalWireDelay(WBDATI7in_ipd, WBDATI7in, tipd_WBDATI7in);
|
|
VitalWireDelay(WBDATI6in_ipd, WBDATI6in, tipd_WBDATI6in);
|
|
VitalWireDelay(WBDATI5in_ipd, WBDATI5in, tipd_WBDATI5in);
|
|
VitalWireDelay(WBDATI4in_ipd, WBDATI4in, tipd_WBDATI4in);
|
|
VitalWireDelay(WBDATI3in_ipd, WBDATI3in, tipd_WBDATI3in);
|
|
VitalWireDelay(WBDATI2in_ipd, WBDATI2in, tipd_WBDATI2in);
|
|
VitalWireDelay(WBDATI1in_ipd, WBDATI1in, tipd_WBDATI1in);
|
|
VitalWireDelay(WBDATI0in_ipd, WBDATI0in, tipd_WBDATI0in);
|
|
VitalWireDelay(PLL0DATI7in_ipd, PLL0DATI7in, tipd_PLL0DATI7in);
|
|
VitalWireDelay(PLL0DATI6in_ipd, PLL0DATI6in, tipd_PLL0DATI6in);
|
|
VitalWireDelay(PLL0DATI5in_ipd, PLL0DATI5in, tipd_PLL0DATI5in);
|
|
VitalWireDelay(PLL0DATI4in_ipd, PLL0DATI4in, tipd_PLL0DATI4in);
|
|
VitalWireDelay(PLL0DATI3in_ipd, PLL0DATI3in, tipd_PLL0DATI3in);
|
|
VitalWireDelay(PLL0DATI2in_ipd, PLL0DATI2in, tipd_PLL0DATI2in);
|
|
VitalWireDelay(PLL0DATI1in_ipd, PLL0DATI1in, tipd_PLL0DATI1in);
|
|
VitalWireDelay(PLL0DATI0in_ipd, PLL0DATI0in, tipd_PLL0DATI0in);
|
|
VitalWireDelay(PLL0ACKIin_ipd, PLL0ACKIin, tipd_PLL0ACKIin);
|
|
VitalWireDelay(PLL1DATI7in_ipd, PLL1DATI7in, tipd_PLL1DATI7in);
|
|
VitalWireDelay(PLL1DATI6in_ipd, PLL1DATI6in, tipd_PLL1DATI6in);
|
|
VitalWireDelay(PLL1DATI5in_ipd, PLL1DATI5in, tipd_PLL1DATI5in);
|
|
VitalWireDelay(PLL1DATI4in_ipd, PLL1DATI4in, tipd_PLL1DATI4in);
|
|
VitalWireDelay(PLL1DATI3in_ipd, PLL1DATI3in, tipd_PLL1DATI3in);
|
|
VitalWireDelay(PLL1DATI2in_ipd, PLL1DATI2in, tipd_PLL1DATI2in);
|
|
VitalWireDelay(PLL1DATI1in_ipd, PLL1DATI1in, tipd_PLL1DATI1in);
|
|
VitalWireDelay(PLL1DATI0in_ipd, PLL1DATI0in, tipd_PLL1DATI0in);
|
|
VitalWireDelay(PLL1ACKIin_ipd, PLL1ACKIin, tipd_PLL1ACKIin);
|
|
VitalWireDelay(I2C1SCLIin_ipd, I2C1SCLIin, tipd_I2C1SCLIin);
|
|
VitalWireDelay(I2C1SDAIin_ipd, I2C1SDAIin, tipd_I2C1SDAIin);
|
|
VitalWireDelay(I2C2SCLIin_ipd, I2C2SCLIin, tipd_I2C2SCLIin);
|
|
VitalWireDelay(I2C2SDAIin_ipd, I2C2SDAIin, tipd_I2C2SDAIin);
|
|
VitalWireDelay(SPISCKIin_ipd, SPISCKIin, tipd_SPISCKIin);
|
|
VitalWireDelay(SPIMISOIin_ipd, SPIMISOIin, tipd_SPIMISOIin);
|
|
VitalWireDelay(SPIMOSIIin_ipd, SPIMOSIIin, tipd_SPIMOSIIin);
|
|
VitalWireDelay(SPISCSNin_ipd, SPISCSNin, tipd_SPISCSNin);
|
|
VitalWireDelay(TCCLKIin_ipd, TCCLKIin, tipd_TCCLKIin);
|
|
VitalWireDelay(TCRSTNin_ipd, TCRSTNin, tipd_TCRSTNin);
|
|
VitalWireDelay(TCICin_ipd, TCICin, tipd_TCICin);
|
|
VitalWireDelay(UFMSNin_ipd, UFMSNin, tipd_UFMSNin);
|
|
VitalWireDelay(WBDATO7in_ipd, WBDATO7in, tipd_WBDATO7in);
|
|
VitalWireDelay(WBDATO6in_ipd, WBDATO6in, tipd_WBDATO6in);
|
|
VitalWireDelay(WBDATO5in_ipd, WBDATO5in, tipd_WBDATO5in);
|
|
VitalWireDelay(WBDATO4in_ipd, WBDATO4in, tipd_WBDATO4in);
|
|
VitalWireDelay(WBDATO3in_ipd, WBDATO3in, tipd_WBDATO3in);
|
|
VitalWireDelay(WBDATO2in_ipd, WBDATO2in, tipd_WBDATO2in);
|
|
VitalWireDelay(WBDATO1in_ipd, WBDATO1in, tipd_WBDATO1in);
|
|
VitalWireDelay(WBDATO0in_ipd, WBDATO0in, tipd_WBDATO0in);
|
|
VitalWireDelay(WBACKOin_ipd, WBACKOin, tipd_WBACKOin);
|
|
VitalWireDelay(PLLCLKOin_ipd, PLLCLKOin, tipd_PLLCLKOin);
|
|
VitalWireDelay(PLLRSTOin_ipd, PLLRSTOin, tipd_PLLRSTOin);
|
|
VitalWireDelay(PLL0STBOin_ipd, PLL0STBOin, tipd_PLL0STBOin);
|
|
VitalWireDelay(PLL1STBOin_ipd, PLL1STBOin, tipd_PLL1STBOin);
|
|
VitalWireDelay(PLLWEOin_ipd, PLLWEOin, tipd_PLLWEOin);
|
|
VitalWireDelay(PLLADRO4in_ipd, PLLADRO4in, tipd_PLLADRO4in);
|
|
VitalWireDelay(PLLADRO3in_ipd, PLLADRO3in, tipd_PLLADRO3in);
|
|
VitalWireDelay(PLLADRO2in_ipd, PLLADRO2in, tipd_PLLADRO2in);
|
|
VitalWireDelay(PLLADRO1in_ipd, PLLADRO1in, tipd_PLLADRO1in);
|
|
VitalWireDelay(PLLADRO0in_ipd, PLLADRO0in, tipd_PLLADRO0in);
|
|
VitalWireDelay(PLLDATO7in_ipd, PLLDATO7in, tipd_PLLDATO7in);
|
|
VitalWireDelay(PLLDATO6in_ipd, PLLDATO6in, tipd_PLLDATO6in);
|
|
VitalWireDelay(PLLDATO5in_ipd, PLLDATO5in, tipd_PLLDATO5in);
|
|
VitalWireDelay(PLLDATO4in_ipd, PLLDATO4in, tipd_PLLDATO4in);
|
|
VitalWireDelay(PLLDATO3in_ipd, PLLDATO3in, tipd_PLLDATO3in);
|
|
VitalWireDelay(PLLDATO2in_ipd, PLLDATO2in, tipd_PLLDATO2in);
|
|
VitalWireDelay(PLLDATO1in_ipd, PLLDATO1in, tipd_PLLDATO1in);
|
|
VitalWireDelay(PLLDATO0in_ipd, PLLDATO0in, tipd_PLLDATO0in);
|
|
VitalWireDelay(I2C1SCLOin_ipd, I2C1SCLOin, tipd_I2C1SCLOin);
|
|
VitalWireDelay(I2C1SCLOENin_ipd, I2C1SCLOENin, tipd_I2C1SCLOENin);
|
|
VitalWireDelay(I2C1SDAOin_ipd, I2C1SDAOin, tipd_I2C1SDAOin);
|
|
VitalWireDelay(I2C1SDAOENin_ipd, I2C1SDAOENin, tipd_I2C1SDAOENin);
|
|
VitalWireDelay(I2C2SCLOin_ipd, I2C2SCLOin, tipd_I2C2SCLOin);
|
|
VitalWireDelay(I2C2SCLOENin_ipd, I2C2SCLOENin, tipd_I2C2SCLOENin);
|
|
VitalWireDelay(I2C2SDAOin_ipd, I2C2SDAOin, tipd_I2C2SDAOin);
|
|
VitalWireDelay(I2C2SDAOENin_ipd, I2C2SDAOENin, tipd_I2C2SDAOENin);
|
|
VitalWireDelay(I2C1IRQOin_ipd, I2C1IRQOin, tipd_I2C1IRQOin);
|
|
VitalWireDelay(I2C2IRQOin_ipd, I2C2IRQOin, tipd_I2C2IRQOin);
|
|
VitalWireDelay(SPISCKOin_ipd, SPISCKOin, tipd_SPISCKOin);
|
|
VitalWireDelay(SPISCKENin_ipd, SPISCKENin, tipd_SPISCKENin);
|
|
VitalWireDelay(SPIMISOOin_ipd, SPIMISOOin, tipd_SPIMISOOin);
|
|
VitalWireDelay(SPIMISOENin_ipd, SPIMISOENin, tipd_SPIMISOENin);
|
|
VitalWireDelay(SPIMOSIOin_ipd, SPIMOSIOin, tipd_SPIMOSIOin);
|
|
VitalWireDelay(SPIMOSIENin_ipd, SPIMOSIENin, tipd_SPIMOSIENin);
|
|
VitalWireDelay(SPIMCSN0in_ipd, SPIMCSN0in, tipd_SPIMCSN0in);
|
|
VitalWireDelay(SPIMCSN1in_ipd, SPIMCSN1in, tipd_SPIMCSN1in);
|
|
VitalWireDelay(SPIMCSN2in_ipd, SPIMCSN2in, tipd_SPIMCSN2in);
|
|
VitalWireDelay(SPIMCSN3in_ipd, SPIMCSN3in, tipd_SPIMCSN3in);
|
|
VitalWireDelay(SPIMCSN4in_ipd, SPIMCSN4in, tipd_SPIMCSN4in);
|
|
VitalWireDelay(SPIMCSN5in_ipd, SPIMCSN5in, tipd_SPIMCSN5in);
|
|
VitalWireDelay(SPIMCSN6in_ipd, SPIMCSN6in, tipd_SPIMCSN6in);
|
|
VitalWireDelay(SPIMCSN7in_ipd, SPIMCSN7in, tipd_SPIMCSN7in);
|
|
VitalWireDelay(SPICSNENin_ipd, SPICSNENin, tipd_SPICSNENin);
|
|
VitalWireDelay(SPIIRQOin_ipd, SPIIRQOin, tipd_SPIIRQOin);
|
|
VitalWireDelay(TCINTin_ipd, TCINTin, tipd_TCINTin);
|
|
VitalWireDelay(TCOCin_ipd, TCOCin, tipd_TCOCin);
|
|
VitalWireDelay(WBCUFMIRQin_ipd, WBCUFMIRQin, tipd_WBCUFMIRQin);
|
|
VitalWireDelay(CFGWAKEin_ipd, CFGWAKEin, tipd_CFGWAKEin);
|
|
VitalWireDelay(CFGSTDBYin_ipd, CFGSTDBYin, tipd_CFGSTDBYin);
|
|
END BLOCK;
|
|
|
|
-- Setup and Hold DELAYs
|
|
SignalDelay : BLOCK
|
|
BEGIN
|
|
VitalSignalDelay(WBCLKIin_dly, WBCLKIin_ipd, ticd_WBCLKIin);
|
|
VitalSignalDelay(WBRSTIin_dly, WBRSTIin_ipd, tisd_WBRSTIin_WBCLKIin);
|
|
VitalSignalDelay(WBCYCIin_dly, WBCYCIin_ipd, tisd_WBCYCIin_WBCLKIin);
|
|
VitalSignalDelay(WBSTBIin_dly, WBSTBIin_ipd, tisd_WBSTBIin_WBCLKIin);
|
|
VitalSignalDelay(WBWEIin_dly, WBWEIin_ipd, tisd_WBWEIin_WBCLKIin);
|
|
VitalSignalDelay(WBADRI7in_dly, WBADRI7in_ipd, tisd_WBADRI7in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI6in_dly, WBADRI6in_ipd, tisd_WBADRI6in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI5in_dly, WBADRI5in_ipd, tisd_WBADRI5in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI4in_dly, WBADRI4in_ipd, tisd_WBADRI4in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI3in_dly, WBADRI3in_ipd, tisd_WBADRI3in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI2in_dly, WBADRI2in_ipd, tisd_WBADRI2in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI1in_dly, WBADRI1in_ipd, tisd_WBADRI1in_WBCLKIin);
|
|
VitalSignalDelay(WBADRI0in_dly, WBADRI0in_ipd, tisd_WBADRI0in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI7in_dly, WBDATI7in_ipd, tisd_WBDATI7in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI6in_dly, WBDATI6in_ipd, tisd_WBDATI6in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI5in_dly, WBDATI5in_ipd, tisd_WBDATI5in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI4in_dly, WBDATI4in_ipd, tisd_WBDATI4in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI3in_dly, WBDATI3in_ipd, tisd_WBDATI3in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI2in_dly, WBDATI2in_ipd, tisd_WBDATI2in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI1in_dly, WBDATI1in_ipd, tisd_WBDATI1in_WBCLKIin);
|
|
VitalSignalDelay(WBDATI0in_dly, WBDATI0in_ipd, tisd_WBDATI0in_WBCLKIin);
|
|
END BLOCK;
|
|
|
|
VitalBehavior : PROCESS (WBCLKIin_dly, WBCLKIout_out, WBRSTIin_dly,
|
|
WBRSTIout_out, WBCYCIin_dly, WBCYCIout_out, WBSTBIin_dly, WBSTBIout_out,
|
|
WBWEIin_dly, WBWEIout_out, WBADRI7in_dly, WBADRI7out_out, WBADRI6in_dly,
|
|
WBADRI6out_out, WBADRI5in_dly, WBADRI5out_out, WBADRI4in_dly,
|
|
WBADRI4out_out, WBADRI3in_dly, WBADRI3out_out, WBADRI2in_dly,
|
|
WBADRI2out_out, WBADRI1in_dly, WBADRI1out_out, WBADRI0in_dly,
|
|
WBADRI0out_out, WBDATI7in_dly, WBDATI7out_out, WBDATI6in_dly,
|
|
WBDATI6out_out, WBDATI5in_dly, WBDATI5out_out, WBDATI4in_dly,
|
|
WBDATI4out_out, WBDATI3in_dly, WBDATI3out_out, WBDATI2in_dly,
|
|
WBDATI2out_out, WBDATI1in_dly, WBDATI1out_out, WBDATI0in_dly,
|
|
WBDATI0out_out, PLL0DATI7in_ipd, PLL0DATI7out_out, PLL0DATI6in_ipd,
|
|
PLL0DATI6out_out, PLL0DATI5in_ipd, PLL0DATI5out_out, PLL0DATI4in_ipd,
|
|
PLL0DATI4out_out, PLL0DATI3in_ipd, PLL0DATI3out_out, PLL0DATI2in_ipd,
|
|
PLL0DATI2out_out, PLL0DATI1in_ipd, PLL0DATI1out_out, PLL0DATI0in_ipd,
|
|
PLL0DATI0out_out, PLL0ACKIin_ipd, PLL0ACKIout_out, PLL1DATI7in_ipd,
|
|
PLL1DATI7out_out, PLL1DATI6in_ipd, PLL1DATI6out_out, PLL1DATI5in_ipd,
|
|
PLL1DATI5out_out, PLL1DATI4in_ipd, PLL1DATI4out_out, PLL1DATI3in_ipd,
|
|
PLL1DATI3out_out, PLL1DATI2in_ipd, PLL1DATI2out_out, PLL1DATI1in_ipd,
|
|
PLL1DATI1out_out, PLL1DATI0in_ipd, PLL1DATI0out_out, PLL1ACKIin_ipd,
|
|
PLL1ACKIout_out, I2C1SCLIin_ipd, I2C1SCLIout_out, I2C1SDAIin_ipd,
|
|
I2C1SDAIout_out, I2C2SCLIin_ipd, I2C2SCLIout_out, I2C2SDAIin_ipd,
|
|
I2C2SDAIout_out, SPISCKIin_ipd, SPISCKIout_out, SPIMISOIin_ipd,
|
|
SPIMISOIout_out, SPIMOSIIin_ipd, SPIMOSIIout_out, SPISCSNin_ipd,
|
|
SPISCSNout_out, TCCLKIin_ipd, TCCLKIout_out, TCRSTNin_ipd, TCRSTNout_out,
|
|
TCICin_ipd, TCICout_out, UFMSNin_ipd, UFMSNout_out, WBDATO7out_out,
|
|
WBDATO7in_ipd, WBDATO6out_out, WBDATO6in_ipd, WBDATO5out_out,
|
|
WBDATO5in_ipd, WBDATO4out_out, WBDATO4in_ipd, WBDATO3out_out,
|
|
WBDATO3in_ipd, WBDATO2out_out, WBDATO2in_ipd, WBDATO1out_out,
|
|
WBDATO1in_ipd, WBDATO0out_out, WBDATO0in_ipd, WBACKOout_out,
|
|
WBACKOin_ipd, PLLCLKOout_out, PLLCLKOin_ipd, PLLRSTOout_out,
|
|
PLLRSTOin_ipd, PLL0STBOout_out, PLL0STBOin_ipd, PLL1STBOout_out,
|
|
PLL1STBOin_ipd, PLLWEOout_out, PLLWEOin_ipd, PLLADRO4out_out,
|
|
PLLADRO4in_ipd, PLLADRO3out_out, PLLADRO3in_ipd, PLLADRO2out_out,
|
|
PLLADRO2in_ipd, PLLADRO1out_out, PLLADRO1in_ipd, PLLADRO0out_out,
|
|
PLLADRO0in_ipd, PLLDATO7out_out, PLLDATO7in_ipd, PLLDATO6out_out,
|
|
PLLDATO6in_ipd, PLLDATO5out_out, PLLDATO5in_ipd, PLLDATO4out_out,
|
|
PLLDATO4in_ipd, PLLDATO3out_out, PLLDATO3in_ipd, PLLDATO2out_out,
|
|
PLLDATO2in_ipd, PLLDATO1out_out, PLLDATO1in_ipd, PLLDATO0out_out,
|
|
PLLDATO0in_ipd, I2C1SCLOout_out, I2C1SCLOin_ipd, I2C1SCLOENout_out,
|
|
I2C1SCLOENin_ipd, I2C1SDAOout_out, I2C1SDAOin_ipd, I2C1SDAOENout_out,
|
|
I2C1SDAOENin_ipd, I2C2SCLOout_out, I2C2SCLOin_ipd, I2C2SCLOENout_out,
|
|
I2C2SCLOENin_ipd, I2C2SDAOout_out, I2C2SDAOin_ipd, I2C2SDAOENout_out,
|
|
I2C2SDAOENin_ipd, I2C1IRQOout_out, I2C1IRQOin_ipd, I2C2IRQOout_out,
|
|
I2C2IRQOin_ipd, SPISCKOout_out, SPISCKOin_ipd, SPISCKENout_out,
|
|
SPISCKENin_ipd, SPIMISOOout_out, SPIMISOOin_ipd, SPIMISOENout_out,
|
|
SPIMISOENin_ipd, SPIMOSIOout_out, SPIMOSIOin_ipd, SPIMOSIENout_out,
|
|
SPIMOSIENin_ipd, SPIMCSN0out_out, SPIMCSN0in_ipd, SPIMCSN1out_out,
|
|
SPIMCSN1in_ipd, SPIMCSN2out_out, SPIMCSN2in_ipd, SPIMCSN3out_out,
|
|
SPIMCSN3in_ipd, SPIMCSN4out_out, SPIMCSN4in_ipd, SPIMCSN5out_out,
|
|
SPIMCSN5in_ipd, SPIMCSN6out_out, SPIMCSN6in_ipd, SPIMCSN7out_out,
|
|
SPIMCSN7in_ipd, SPICSNENout_out, SPICSNENin_ipd, SPIIRQOout_out,
|
|
SPIIRQOin_ipd, TCINTout_out, TCINTin_ipd, TCOCout_out, TCOCin_ipd,
|
|
WBCUFMIRQout_out, WBCUFMIRQin_ipd, CFGWAKEout_out, CFGWAKEin_ipd,
|
|
CFGSTDBYout_out, CFGSTDBYin_ipd)
|
|
VARIABLE WBDATO1out_zd : std_logic := 'X';
|
|
VARIABLE WBDATO1out_GlitchData : VitalGlitchDataType;
|
|
VARIABLE WBDATO0out_zd : std_logic := 'X';
|
|
VARIABLE WBDATO0out_GlitchData : VitalGlitchDataType;
|
|
VARIABLE WBACKOout_zd : std_logic := 'X';
|
|
VARIABLE WBACKOout_GlitchData : VitalGlitchDataType;
|
|
|
|
VARIABLE tviol_WBRSTIin_WBCLKIin : x01 := '0';
|
|
VARIABLE WBRSTIin_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBCYCIin_WBCLKIin : x01 := '0';
|
|
VARIABLE WBCYCIin_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBSTBIin_WBCLKIin : x01 := '0';
|
|
VARIABLE WBSTBIin_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBWEIin_WBCLKIin : x01 := '0';
|
|
VARIABLE WBWEIin_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI0in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI0in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI1in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI1in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI2in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI2in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI3in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI3in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI4in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI4in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI5in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI5in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI6in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI6in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBADRI7in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBADRI7in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBDATI0in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBDATI0in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBDATI1in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBDATI1in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
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VARIABLE tviol_WBDATI2in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBDATI2in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBDATI3in_WBCLKIin : x01 := '0';
|
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VARIABLE WBDATI3in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBDATI4in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBDATI4in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBDATI5in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBDATI5in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
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VARIABLE tviol_WBDATI6in_WBCLKIin : x01 := '0';
|
|
VARIABLE WBDATI6in_WBCLKIin_TimingDatash : VitalTimingDataType;
|
|
VARIABLE tviol_WBDATI7in_WBCLKIin : x01 := '0';
|
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VARIABLE WBDATI7in_WBCLKIin_TimingDatash : VitalTimingDataType;
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VARIABLE tviol_WBCLKIin_WBCLKIin : x01 := '0';
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VARIABLE periodcheckinfo_WBCLKIin : VitalPeriodDataType;
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BEGIN
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|
|
|
IF (TimingChecksOn) THEN
|
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VitalSetupHoldCheck (
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TestSignal => WBRSTIin_dly,
|
|
TestSignalName => "WBRSTIin",
|
|
TestDelay => tisd_WBRSTIin_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBRSTIin_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBRSTIin_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBRSTIin_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBRSTIin_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBRSTIin_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBRSTIin_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
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TestSignal => WBCYCIin_dly,
|
|
TestSignalName => "WBCYCIin",
|
|
TestDelay => tisd_WBCYCIin_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBCYCIin_WBCLKIin_noedge_posedge,
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|
SetupLow => tsetup_WBCYCIin_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBCYCIin_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBCYCIin_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBCYCIin_WBCLKIin_TimingDatash,
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Violation => tviol_WBCYCIin_WBCLKIin,
|
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MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
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TestSignal => WBSTBIin_dly,
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|
TestSignalName => "WBSTBIin",
|
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TestDelay => tisd_WBSTBIin_WBCLKIin,
|
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RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
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|
RefDelay => ticd_WBCLKIin,
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SetupHigh => tsetup_WBSTBIin_WBCLKIin_noedge_posedge,
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SetupLow => tsetup_WBSTBIin_WBCLKIin_noedge_posedge,
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HoldHigh => thold_WBSTBIin_WBCLKIin_noedge_posedge,
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HoldLow => thold_WBSTBIin_WBCLKIin_noedge_posedge,
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|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
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HeaderMsg => InstancePath,
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TimingData => WBSTBIin_WBCLKIin_TimingDatash,
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Violation => tviol_WBSTBIin_WBCLKIin,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => WBWEIin_dly,
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TestSignalName => "WBWEIin",
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TestDelay => tisd_WBWEIin_WBCLKIin,
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RefSignal => WBCLKIin_dly,
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RefSignalName => "WBCLKIin",
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RefDelay => ticd_WBCLKIin,
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SetupHigh => tsetup_WBWEIin_WBCLKIin_noedge_posedge,
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SetupLow => tsetup_WBWEIin_WBCLKIin_noedge_posedge,
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HoldHigh => thold_WBWEIin_WBCLKIin_noedge_posedge,
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HoldLow => thold_WBWEIin_WBCLKIin_noedge_posedge,
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CheckEnabled => TRUE,
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RefTransition => '/',
|
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MsgOn => MsgOn, XOn => XOn,
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HeaderMsg => InstancePath,
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TimingData => WBWEIin_WBCLKIin_TimingDatash,
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Violation => tviol_WBWEIin_WBCLKIin,
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|
MsgSeverity => warning);
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VitalSetupHoldCheck (
|
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TestSignal => WBADRI0in_dly,
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TestSignalName => "WBADRI0in",
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TestDelay => tisd_WBADRI0in_WBCLKIin,
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RefSignal => WBCLKIin_dly,
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|
RefSignalName => "WBCLKIin",
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RefDelay => ticd_WBCLKIin,
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SetupHigh => tsetup_WBADRI0in_WBCLKIin_noedge_posedge,
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SetupLow => tsetup_WBADRI0in_WBCLKIin_noedge_posedge,
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HoldHigh => thold_WBADRI0in_WBCLKIin_noedge_posedge,
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HoldLow => thold_WBADRI0in_WBCLKIin_noedge_posedge,
|
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CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBADRI0in_WBCLKIin_TimingDatash,
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Violation => tviol_WBADRI0in_WBCLKIin,
|
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MsgSeverity => warning);
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VitalSetupHoldCheck (
|
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TestSignal => WBADRI1in_dly,
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TestSignalName => "WBADRI1in",
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TestDelay => tisd_WBADRI1in_WBCLKIin,
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RefSignal => WBCLKIin_dly,
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|
RefSignalName => "WBCLKIin",
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|
RefDelay => ticd_WBCLKIin,
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SetupHigh => tsetup_WBADRI1in_WBCLKIin_noedge_posedge,
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|
SetupLow => tsetup_WBADRI1in_WBCLKIin_noedge_posedge,
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HoldHigh => thold_WBADRI1in_WBCLKIin_noedge_posedge,
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HoldLow => thold_WBADRI1in_WBCLKIin_noedge_posedge,
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CheckEnabled => TRUE,
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|
RefTransition => '/',
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MsgOn => MsgOn, XOn => XOn,
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|
HeaderMsg => InstancePath,
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TimingData => WBADRI1in_WBCLKIin_TimingDatash,
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Violation => tviol_WBADRI1in_WBCLKIin,
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MsgSeverity => warning);
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VitalSetupHoldCheck (
|
|
TestSignal => WBADRI2in_dly,
|
|
TestSignalName => "WBADRI2in",
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TestDelay => tisd_WBADRI2in_WBCLKIin,
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|
RefSignal => WBCLKIin_dly,
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|
RefSignalName => "WBCLKIin",
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|
RefDelay => ticd_WBCLKIin,
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SetupHigh => tsetup_WBADRI2in_WBCLKIin_noedge_posedge,
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|
SetupLow => tsetup_WBADRI2in_WBCLKIin_noedge_posedge,
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HoldHigh => thold_WBADRI2in_WBCLKIin_noedge_posedge,
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|
HoldLow => thold_WBADRI2in_WBCLKIin_noedge_posedge,
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|
CheckEnabled => TRUE,
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|
RefTransition => '/',
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|
MsgOn => MsgOn, XOn => XOn,
|
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HeaderMsg => InstancePath,
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|
TimingData => WBADRI2in_WBCLKIin_TimingDatash,
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Violation => tviol_WBADRI2in_WBCLKIin,
|
|
MsgSeverity => warning);
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VitalSetupHoldCheck (
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TestSignal => WBADRI3in_dly,
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|
TestSignalName => "WBADRI3in",
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TestDelay => tisd_WBADRI3in_WBCLKIin,
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|
RefSignal => WBCLKIin_dly,
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|
RefSignalName => "WBCLKIin",
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|
RefDelay => ticd_WBCLKIin,
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SetupHigh => tsetup_WBADRI3in_WBCLKIin_noedge_posedge,
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|
SetupLow => tsetup_WBADRI3in_WBCLKIin_noedge_posedge,
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HoldHigh => thold_WBADRI3in_WBCLKIin_noedge_posedge,
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|
HoldLow => thold_WBADRI3in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
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|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBADRI3in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBADRI3in_WBCLKIin,
|
|
MsgSeverity => warning);
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|
VitalSetupHoldCheck (
|
|
TestSignal => WBADRI4in_dly,
|
|
TestSignalName => "WBADRI4in",
|
|
TestDelay => tisd_WBADRI4in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBADRI4in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBADRI4in_WBCLKIin_noedge_posedge,
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|
HoldHigh => thold_WBADRI4in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBADRI4in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBADRI4in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBADRI4in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBADRI5in_dly,
|
|
TestSignalName => "WBADRI5in",
|
|
TestDelay => tisd_WBADRI5in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBADRI5in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBADRI5in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBADRI5in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBADRI5in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBADRI5in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBADRI5in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBADRI6in_dly,
|
|
TestSignalName => "WBADRI6in",
|
|
TestDelay => tisd_WBADRI6in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBADRI6in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBADRI6in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBADRI6in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBADRI6in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBADRI6in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBADRI6in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBADRI7in_dly,
|
|
TestSignalName => "WBADRI7in",
|
|
TestDelay => tisd_WBADRI7in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBADRI7in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBADRI7in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBADRI7in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBADRI7in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBADRI7in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBADRI7in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI0in_dly,
|
|
TestSignalName => "WBDATI0in",
|
|
TestDelay => tisd_WBDATI0in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI0in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI0in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI0in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI0in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI0in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI0in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI1in_dly,
|
|
TestSignalName => "WBDATI1in",
|
|
TestDelay => tisd_WBDATI1in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI1in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI1in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI1in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI1in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI1in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI1in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI2in_dly,
|
|
TestSignalName => "WBDATI2in",
|
|
TestDelay => tisd_WBDATI2in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI2in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI2in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI2in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI2in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI2in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI2in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI3in_dly,
|
|
TestSignalName => "WBDATI3in",
|
|
TestDelay => tisd_WBDATI3in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI3in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI3in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI3in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI3in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI3in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI3in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI4in_dly,
|
|
TestSignalName => "WBDATI4in",
|
|
TestDelay => tisd_WBDATI4in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI4in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI4in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI4in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI4in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI4in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI4in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI5in_dly,
|
|
TestSignalName => "WBDATI5in",
|
|
TestDelay => tisd_WBDATI5in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI5in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI5in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI5in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI5in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI5in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI5in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI6in_dly,
|
|
TestSignalName => "WBDATI6in",
|
|
TestDelay => tisd_WBDATI6in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI6in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI6in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI6in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI6in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI6in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI6in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalSetupHoldCheck (
|
|
TestSignal => WBDATI7in_dly,
|
|
TestSignalName => "WBDATI7in",
|
|
TestDelay => tisd_WBDATI7in_WBCLKIin,
|
|
RefSignal => WBCLKIin_dly,
|
|
RefSignalName => "WBCLKIin",
|
|
RefDelay => ticd_WBCLKIin,
|
|
SetupHigh => tsetup_WBDATI7in_WBCLKIin_noedge_posedge,
|
|
SetupLow => tsetup_WBDATI7in_WBCLKIin_noedge_posedge,
|
|
HoldHigh => thold_WBDATI7in_WBCLKIin_noedge_posedge,
|
|
HoldLow => thold_WBDATI7in_WBCLKIin_noedge_posedge,
|
|
CheckEnabled => TRUE,
|
|
RefTransition => '/',
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
TimingData => WBDATI7in_WBCLKIin_TimingDatash,
|
|
Violation => tviol_WBDATI7in_WBCLKIin,
|
|
MsgSeverity => warning);
|
|
VitalPeriodPulseCheck (
|
|
TestSignal => WBCLKIin_ipd,
|
|
TestSignalName => "WBCLKIin",
|
|
Period => tperiod_WBCLKIin,
|
|
PulseWidthHigh => tpw_WBCLKIin_posedge,
|
|
PulseWidthLow => tpw_WBCLKIin_negedge,
|
|
PeriodData => periodcheckinfo_WBCLKIin,
|
|
Violation => tviol_WBCLKIin_WBCLKIin,
|
|
MsgOn => MsgOn, XOn => XOn,
|
|
HeaderMsg => InstancePath,
|
|
CheckEnabled => TRUE,
|
|
MsgSeverity => warning);
|
|
|
|
END IF;
|
|
|
|
WBCLKIout <= WBCLKIout_out;
|
|
WBRSTIout <= WBRSTIout_out;
|
|
WBCYCIout <= WBCYCIout_out;
|
|
WBSTBIout <= WBSTBIout_out;
|
|
WBWEIout <= WBWEIout_out;
|
|
WBADRI7out <= WBADRI7out_out;
|
|
WBADRI6out <= WBADRI6out_out;
|
|
WBADRI5out <= WBADRI5out_out;
|
|
WBADRI4out <= WBADRI4out_out;
|
|
WBADRI3out <= WBADRI3out_out;
|
|
WBADRI2out <= WBADRI2out_out;
|
|
WBADRI1out <= WBADRI1out_out;
|
|
WBADRI0out <= WBADRI0out_out;
|
|
WBDATI7out <= WBDATI7out_out;
|
|
WBDATI6out <= WBDATI6out_out;
|
|
WBDATI5out <= WBDATI5out_out;
|
|
WBDATI4out <= WBDATI4out_out;
|
|
WBDATI3out <= WBDATI3out_out;
|
|
WBDATI2out <= WBDATI2out_out;
|
|
WBDATI1out <= WBDATI1out_out;
|
|
WBDATI0out <= WBDATI0out_out;
|
|
PLL0DATI7out <= PLL0DATI7out_out;
|
|
PLL0DATI6out <= PLL0DATI6out_out;
|
|
PLL0DATI5out <= PLL0DATI5out_out;
|
|
PLL0DATI4out <= PLL0DATI4out_out;
|
|
PLL0DATI3out <= PLL0DATI3out_out;
|
|
PLL0DATI2out <= PLL0DATI2out_out;
|
|
PLL0DATI1out <= PLL0DATI1out_out;
|
|
PLL0DATI0out <= PLL0DATI0out_out;
|
|
PLL0ACKIout <= PLL0ACKIout_out;
|
|
PLL1DATI7out <= PLL1DATI7out_out;
|
|
PLL1DATI6out <= PLL1DATI6out_out;
|
|
PLL1DATI5out <= PLL1DATI5out_out;
|
|
PLL1DATI4out <= PLL1DATI4out_out;
|
|
PLL1DATI3out <= PLL1DATI3out_out;
|
|
PLL1DATI2out <= PLL1DATI2out_out;
|
|
PLL1DATI1out <= PLL1DATI1out_out;
|
|
PLL1DATI0out <= PLL1DATI0out_out;
|
|
PLL1ACKIout <= PLL1ACKIout_out;
|
|
I2C1SCLIout <= I2C1SCLIout_out;
|
|
I2C1SDAIout <= I2C1SDAIout_out;
|
|
I2C2SCLIout <= I2C2SCLIout_out;
|
|
I2C2SDAIout <= I2C2SDAIout_out;
|
|
SPISCKIout <= SPISCKIout_out;
|
|
SPIMISOIout <= SPIMISOIout_out;
|
|
SPIMOSIIout <= SPIMOSIIout_out;
|
|
SPISCSNout <= SPISCSNout_out;
|
|
TCCLKIout <= TCCLKIout_out;
|
|
TCRSTNout <= TCRSTNout_out;
|
|
TCICout <= TCICout_out;
|
|
UFMSNout <= UFMSNout_out;
|
|
WBDATO7out <= WBDATO7out_out;
|
|
WBDATO6out <= WBDATO6out_out;
|
|
WBDATO5out <= WBDATO5out_out;
|
|
WBDATO4out <= WBDATO4out_out;
|
|
WBDATO3out <= WBDATO3out_out;
|
|
WBDATO2out <= WBDATO2out_out;
|
|
WBDATO1out_zd := WBDATO1out_out;
|
|
WBDATO0out_zd := WBDATO0out_out;
|
|
WBACKOout_zd := WBACKOout_out;
|
|
PLLCLKOout <= PLLCLKOout_out;
|
|
PLLRSTOout <= PLLRSTOout_out;
|
|
PLL0STBOout <= PLL0STBOout_out;
|
|
PLL1STBOout <= PLL1STBOout_out;
|
|
PLLWEOout <= PLLWEOout_out;
|
|
PLLADRO4out <= PLLADRO4out_out;
|
|
PLLADRO3out <= PLLADRO3out_out;
|
|
PLLADRO2out <= PLLADRO2out_out;
|
|
PLLADRO1out <= PLLADRO1out_out;
|
|
PLLADRO0out <= PLLADRO0out_out;
|
|
PLLDATO7out <= PLLDATO7out_out;
|
|
PLLDATO6out <= PLLDATO6out_out;
|
|
PLLDATO5out <= PLLDATO5out_out;
|
|
PLLDATO4out <= PLLDATO4out_out;
|
|
PLLDATO3out <= PLLDATO3out_out;
|
|
PLLDATO2out <= PLLDATO2out_out;
|
|
PLLDATO1out <= PLLDATO1out_out;
|
|
PLLDATO0out <= PLLDATO0out_out;
|
|
I2C1SCLOout <= I2C1SCLOout_out;
|
|
I2C1SCLOENout <= I2C1SCLOENout_out;
|
|
I2C1SDAOout <= I2C1SDAOout_out;
|
|
I2C1SDAOENout <= I2C1SDAOENout_out;
|
|
I2C2SCLOout <= I2C2SCLOout_out;
|
|
I2C2SCLOENout <= I2C2SCLOENout_out;
|
|
I2C2SDAOout <= I2C2SDAOout_out;
|
|
I2C2SDAOENout <= I2C2SDAOENout_out;
|
|
I2C1IRQOout <= I2C1IRQOout_out;
|
|
I2C2IRQOout <= I2C2IRQOout_out;
|
|
SPISCKOout <= SPISCKOout_out;
|
|
SPISCKENout <= SPISCKENout_out;
|
|
SPIMISOOout <= SPIMISOOout_out;
|
|
SPIMISOENout <= SPIMISOENout_out;
|
|
SPIMOSIOout <= SPIMOSIOout_out;
|
|
SPIMOSIENout <= SPIMOSIENout_out;
|
|
SPIMCSN0out <= SPIMCSN0out_out;
|
|
SPIMCSN1out <= SPIMCSN1out_out;
|
|
SPIMCSN2out <= SPIMCSN2out_out;
|
|
SPIMCSN3out <= SPIMCSN3out_out;
|
|
SPIMCSN4out <= SPIMCSN4out_out;
|
|
SPIMCSN5out <= SPIMCSN5out_out;
|
|
SPIMCSN6out <= SPIMCSN6out_out;
|
|
SPIMCSN7out <= SPIMCSN7out_out;
|
|
SPICSNENout <= SPICSNENout_out;
|
|
SPIIRQOout <= SPIIRQOout_out;
|
|
TCINTout <= TCINTout_out;
|
|
TCOCout <= TCOCout_out;
|
|
WBCUFMIRQout <= WBCUFMIRQout_out;
|
|
CFGWAKEout <= CFGWAKEout_out;
|
|
CFGSTDBYout <= CFGSTDBYout_out;
|
|
|
|
VitalPathDelay01 (
|
|
|
|
OutSignal => WBDATO0out, OutSignalName => "WBDATO0out", OutTemp => WBDATO0out_zd,
|
|
Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event,
|
|
PathDelay => tpd_WBCLKIin_WBDATO0out,
|
|
PathCondition => TRUE)),
|
|
GlitchData => WBDATO0out_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
|
|
OutSignal => WBDATO1out, OutSignalName => "WBDATO1out", OutTemp => WBDATO1out_zd,
|
|
Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event,
|
|
PathDelay => tpd_WBCLKIin_WBDATO1out,
|
|
PathCondition => TRUE)),
|
|
GlitchData => WBDATO1out_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
VitalPathDelay01 (
|
|
OutSignal => WBACKOout, OutSignalName => "WBACKOout", OutTemp => WBACKOout_zd,
|
|
Paths => (0 => (InputChangeTime => WBCLKIin_dly'last_event,
|
|
PathDelay => tpd_WBCLKIin_WBACKOout,
|
|
PathCondition => TRUE)),
|
|
GlitchData => WBACKOout_GlitchData,
|
|
Mode => ondetect, XOn => XOn, MsgOn => MsgOn);
|
|
|
|
END PROCESS;
|
|
|
|
end Structure;
|
|
|
|
-- entity EFBB
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity EFBB is
|
|
port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic;
|
|
WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic;
|
|
WBADRI1: in Std_logic; WBADRI2: in Std_logic; WBADRI3: in Std_logic;
|
|
WBADRI4: in Std_logic; WBADRI5: in Std_logic; WBADRI6: in Std_logic;
|
|
WBADRI7: in Std_logic; WBDATI0: in Std_logic; WBDATI1: in Std_logic;
|
|
WBDATI2: in Std_logic; WBDATI3: in Std_logic; WBDATI4: in Std_logic;
|
|
WBDATI5: in Std_logic; WBDATI6: in Std_logic; WBDATI7: in Std_logic;
|
|
WBDATO0: out Std_logic; WBDATO1: out Std_logic;
|
|
WBDATO2: out Std_logic; WBDATO3: out Std_logic;
|
|
WBDATO4: out Std_logic; WBDATO5: out Std_logic;
|
|
WBDATO6: out Std_logic; WBDATO7: out Std_logic;
|
|
WBACKO: out Std_logic; WBCUFMIRQ: out Std_logic; UFMSN: in Std_logic;
|
|
CFGWAKE: out Std_logic; CFGSTDBY: out Std_logic;
|
|
I2C1SCLI: in Std_logic; I2C1SCLO: out Std_logic;
|
|
I2C1SCLOEN: out Std_logic; I2C1SDAI: in Std_logic;
|
|
I2C1SDAO: out Std_logic; I2C1SDAOEN: out Std_logic;
|
|
I2C2SCLI: in Std_logic; I2C2SCLO: out Std_logic;
|
|
I2C2SCLOEN: out Std_logic; I2C2SDAI: in Std_logic;
|
|
I2C2SDAO: out Std_logic; I2C2SDAOEN: out Std_logic;
|
|
I2C1IRQO: out Std_logic; I2C2IRQO: out Std_logic;
|
|
SPISCKI: in Std_logic; SPISCKO: out Std_logic;
|
|
SPISCKEN: out Std_logic; SPIMISOI: in Std_logic;
|
|
SPIMISOO: out Std_logic; SPIMISOEN: out Std_logic;
|
|
SPIMOSII: in Std_logic; SPIMOSIO: out Std_logic;
|
|
SPIMOSIEN: out Std_logic; SPIMCSN0: out Std_logic;
|
|
SPIMCSN1: out Std_logic; SPIMCSN2: out Std_logic;
|
|
SPIMCSN3: out Std_logic; SPIMCSN4: out Std_logic;
|
|
SPIMCSN5: out Std_logic; SPIMCSN6: out Std_logic;
|
|
SPIMCSN7: out Std_logic; SPICSNEN: out Std_logic;
|
|
SPISCSN: in Std_logic; SPIIRQO: out Std_logic; TCCLKI: in Std_logic;
|
|
TCRSTN: in Std_logic; TCIC: in Std_logic; TCINT: out Std_logic;
|
|
TCOC: out Std_logic; PLLCLKO: out Std_logic; PLLRSTO: out Std_logic;
|
|
PLL0STBO: out Std_logic; PLL1STBO: out Std_logic;
|
|
PLLWEO: out Std_logic; PLLADRO0: out Std_logic;
|
|
PLLADRO1: out Std_logic; PLLADRO2: out Std_logic;
|
|
PLLADRO3: out Std_logic; PLLADRO4: out Std_logic;
|
|
PLLDATO0: out Std_logic; PLLDATO1: out Std_logic;
|
|
PLLDATO2: out Std_logic; PLLDATO3: out Std_logic;
|
|
PLLDATO4: out Std_logic; PLLDATO5: out Std_logic;
|
|
PLLDATO6: out Std_logic; PLLDATO7: out Std_logic;
|
|
PLL0DATI0: in Std_logic; PLL0DATI1: in Std_logic;
|
|
PLL0DATI2: in Std_logic; PLL0DATI3: in Std_logic;
|
|
PLL0DATI4: in Std_logic; PLL0DATI5: in Std_logic;
|
|
PLL0DATI6: in Std_logic; PLL0DATI7: in Std_logic;
|
|
PLL0ACKI: in Std_logic; PLL1DATI0: in Std_logic;
|
|
PLL1DATI1: in Std_logic; PLL1DATI2: in Std_logic;
|
|
PLL1DATI3: in Std_logic; PLL1DATI4: in Std_logic;
|
|
PLL1DATI5: in Std_logic; PLL1DATI6: in Std_logic;
|
|
PLL1DATI7: in Std_logic; PLL1ACKI: in Std_logic);
|
|
|
|
|
|
|
|
end EFBB;
|
|
|
|
architecture Structure of EFBB is
|
|
signal WBCLKI_buf: Std_logic;
|
|
signal WBRSTI_buf: Std_logic;
|
|
signal WBCYCI_buf: Std_logic;
|
|
signal WBSTBI_buf: Std_logic;
|
|
signal WBWEI_buf: Std_logic;
|
|
signal WBADRI7_buf: Std_logic;
|
|
signal WBADRI6_buf: Std_logic;
|
|
signal WBADRI5_buf: Std_logic;
|
|
signal WBADRI4_buf: Std_logic;
|
|
signal WBADRI3_buf: Std_logic;
|
|
signal WBADRI2_buf: Std_logic;
|
|
signal WBADRI1_buf: Std_logic;
|
|
signal WBADRI0_buf: Std_logic;
|
|
signal WBDATI7_buf: Std_logic;
|
|
signal WBDATI6_buf: Std_logic;
|
|
signal WBDATI5_buf: Std_logic;
|
|
signal WBDATI4_buf: Std_logic;
|
|
signal WBDATI3_buf: Std_logic;
|
|
signal WBDATI2_buf: Std_logic;
|
|
signal WBDATI1_buf: Std_logic;
|
|
signal WBDATI0_buf: Std_logic;
|
|
signal PLL0DATI7_buf: Std_logic;
|
|
signal PLL0DATI6_buf: Std_logic;
|
|
signal PLL0DATI5_buf: Std_logic;
|
|
signal PLL0DATI4_buf: Std_logic;
|
|
signal PLL0DATI3_buf: Std_logic;
|
|
signal PLL0DATI2_buf: Std_logic;
|
|
signal PLL0DATI1_buf: Std_logic;
|
|
signal PLL0DATI0_buf: Std_logic;
|
|
signal PLL0ACKI_buf: Std_logic;
|
|
signal PLL1DATI7_buf: Std_logic;
|
|
signal PLL1DATI6_buf: Std_logic;
|
|
signal PLL1DATI5_buf: Std_logic;
|
|
signal PLL1DATI4_buf: Std_logic;
|
|
signal PLL1DATI3_buf: Std_logic;
|
|
signal PLL1DATI2_buf: Std_logic;
|
|
signal PLL1DATI1_buf: Std_logic;
|
|
signal PLL1DATI0_buf: Std_logic;
|
|
signal PLL1ACKI_buf: Std_logic;
|
|
signal I2C1SCLI_buf: Std_logic;
|
|
signal I2C1SDAI_buf: Std_logic;
|
|
signal I2C2SCLI_buf: Std_logic;
|
|
signal I2C2SDAI_buf: Std_logic;
|
|
signal SPISCKI_buf: Std_logic;
|
|
signal SPIMISOI_buf: Std_logic;
|
|
signal SPIMOSII_buf: Std_logic;
|
|
signal SPISCSN_buf: Std_logic;
|
|
signal TCCLKI_buf: Std_logic;
|
|
signal TCRSTN_buf: Std_logic;
|
|
signal TCIC_buf: Std_logic;
|
|
signal UFMSN_buf: Std_logic;
|
|
signal WBDATO7_buf: Std_logic;
|
|
signal WBDATO6_buf: Std_logic;
|
|
signal WBDATO5_buf: Std_logic;
|
|
signal WBDATO4_buf: Std_logic;
|
|
signal WBDATO3_buf: Std_logic;
|
|
signal WBDATO2_buf: Std_logic;
|
|
signal WBDATO1_buf: Std_logic;
|
|
signal WBDATO0_buf: Std_logic;
|
|
signal WBACKO_buf: Std_logic;
|
|
signal PLLCLKO_buf: Std_logic;
|
|
signal PLLRSTO_buf: Std_logic;
|
|
signal PLL0STBO_buf: Std_logic;
|
|
signal PLL1STBO_buf: Std_logic;
|
|
signal PLLWEO_buf: Std_logic;
|
|
signal PLLADRO4_buf: Std_logic;
|
|
signal PLLADRO3_buf: Std_logic;
|
|
signal PLLADRO2_buf: Std_logic;
|
|
signal PLLADRO1_buf: Std_logic;
|
|
signal PLLADRO0_buf: Std_logic;
|
|
signal PLLDATO7_buf: Std_logic;
|
|
signal PLLDATO6_buf: Std_logic;
|
|
signal PLLDATO5_buf: Std_logic;
|
|
signal PLLDATO4_buf: Std_logic;
|
|
signal PLLDATO3_buf: Std_logic;
|
|
signal PLLDATO2_buf: Std_logic;
|
|
signal PLLDATO1_buf: Std_logic;
|
|
signal PLLDATO0_buf: Std_logic;
|
|
signal I2C1SCLO_buf: Std_logic;
|
|
signal I2C1SCLOEN_buf: Std_logic;
|
|
signal I2C1SDAO_buf: Std_logic;
|
|
signal I2C1SDAOEN_buf: Std_logic;
|
|
signal I2C2SCLO_buf: Std_logic;
|
|
signal I2C2SCLOEN_buf: Std_logic;
|
|
signal I2C2SDAO_buf: Std_logic;
|
|
signal I2C2SDAOEN_buf: Std_logic;
|
|
signal I2C1IRQO_buf: Std_logic;
|
|
signal I2C2IRQO_buf: Std_logic;
|
|
signal SPISCKO_buf: Std_logic;
|
|
signal SPISCKEN_buf: Std_logic;
|
|
signal SPIMISOO_buf: Std_logic;
|
|
signal SPIMISOEN_buf: Std_logic;
|
|
signal SPIMOSIO_buf: Std_logic;
|
|
signal SPIMOSIEN_buf: Std_logic;
|
|
signal SPIMCSN0_buf: Std_logic;
|
|
signal SPIMCSN1_buf: Std_logic;
|
|
signal SPIMCSN2_buf: Std_logic;
|
|
signal SPIMCSN3_buf: Std_logic;
|
|
signal SPIMCSN4_buf: Std_logic;
|
|
signal SPIMCSN5_buf: Std_logic;
|
|
signal SPIMCSN6_buf: Std_logic;
|
|
signal SPIMCSN7_buf: Std_logic;
|
|
signal SPICSNEN_buf: Std_logic;
|
|
signal SPIIRQO_buf: Std_logic;
|
|
signal TCINT_buf: Std_logic;
|
|
signal TCOC_buf: Std_logic;
|
|
signal WBCUFMIRQ_buf: Std_logic;
|
|
signal CFGWAKE_buf: Std_logic;
|
|
signal CFGSTDBY_buf: Std_logic;
|
|
component EFB_Buffer_Block
|
|
port (WBCLKIin: in Std_logic; WBCLKIout: out Std_logic;
|
|
WBRSTIin: in Std_logic; WBRSTIout: out Std_logic;
|
|
WBCYCIin: in Std_logic; WBCYCIout: out Std_logic;
|
|
WBSTBIin: in Std_logic; WBSTBIout: out Std_logic;
|
|
WBWEIin: in Std_logic; WBWEIout: out Std_logic;
|
|
WBADRI7in: in Std_logic; WBADRI7out: out Std_logic;
|
|
WBADRI6in: in Std_logic; WBADRI6out: out Std_logic;
|
|
WBADRI5in: in Std_logic; WBADRI5out: out Std_logic;
|
|
WBADRI4in: in Std_logic; WBADRI4out: out Std_logic;
|
|
WBADRI3in: in Std_logic; WBADRI3out: out Std_logic;
|
|
WBADRI2in: in Std_logic; WBADRI2out: out Std_logic;
|
|
WBADRI1in: in Std_logic; WBADRI1out: out Std_logic;
|
|
WBADRI0in: in Std_logic; WBADRI0out: out Std_logic;
|
|
WBDATI7in: in Std_logic; WBDATI7out: out Std_logic;
|
|
WBDATI6in: in Std_logic; WBDATI6out: out Std_logic;
|
|
WBDATI5in: in Std_logic; WBDATI5out: out Std_logic;
|
|
WBDATI4in: in Std_logic; WBDATI4out: out Std_logic;
|
|
WBDATI3in: in Std_logic; WBDATI3out: out Std_logic;
|
|
WBDATI2in: in Std_logic; WBDATI2out: out Std_logic;
|
|
WBDATI1in: in Std_logic; WBDATI1out: out Std_logic;
|
|
WBDATI0in: in Std_logic; WBDATI0out: out Std_logic;
|
|
PLL0DATI7in: in Std_logic; PLL0DATI7out: out Std_logic;
|
|
PLL0DATI6in: in Std_logic; PLL0DATI6out: out Std_logic;
|
|
PLL0DATI5in: in Std_logic; PLL0DATI5out: out Std_logic;
|
|
PLL0DATI4in: in Std_logic; PLL0DATI4out: out Std_logic;
|
|
PLL0DATI3in: in Std_logic; PLL0DATI3out: out Std_logic;
|
|
PLL0DATI2in: in Std_logic; PLL0DATI2out: out Std_logic;
|
|
PLL0DATI1in: in Std_logic; PLL0DATI1out: out Std_logic;
|
|
PLL0DATI0in: in Std_logic; PLL0DATI0out: out Std_logic;
|
|
PLL0ACKIin: in Std_logic; PLL0ACKIout: out Std_logic;
|
|
PLL1DATI7in: in Std_logic; PLL1DATI7out: out Std_logic;
|
|
PLL1DATI6in: in Std_logic; PLL1DATI6out: out Std_logic;
|
|
PLL1DATI5in: in Std_logic; PLL1DATI5out: out Std_logic;
|
|
PLL1DATI4in: in Std_logic; PLL1DATI4out: out Std_logic;
|
|
PLL1DATI3in: in Std_logic; PLL1DATI3out: out Std_logic;
|
|
PLL1DATI2in: in Std_logic; PLL1DATI2out: out Std_logic;
|
|
PLL1DATI1in: in Std_logic; PLL1DATI1out: out Std_logic;
|
|
PLL1DATI0in: in Std_logic; PLL1DATI0out: out Std_logic;
|
|
PLL1ACKIin: in Std_logic; PLL1ACKIout: out Std_logic;
|
|
I2C1SCLIin: in Std_logic; I2C1SCLIout: out Std_logic;
|
|
I2C1SDAIin: in Std_logic; I2C1SDAIout: out Std_logic;
|
|
I2C2SCLIin: in Std_logic; I2C2SCLIout: out Std_logic;
|
|
I2C2SDAIin: in Std_logic; I2C2SDAIout: out Std_logic;
|
|
SPISCKIin: in Std_logic; SPISCKIout: out Std_logic;
|
|
SPIMISOIin: in Std_logic; SPIMISOIout: out Std_logic;
|
|
SPIMOSIIin: in Std_logic; SPIMOSIIout: out Std_logic;
|
|
SPISCSNin: in Std_logic; SPISCSNout: out Std_logic;
|
|
TCCLKIin: in Std_logic; TCCLKIout: out Std_logic;
|
|
TCRSTNin: in Std_logic; TCRSTNout: out Std_logic;
|
|
TCICin: in Std_logic; TCICout: out Std_logic;
|
|
UFMSNin: in Std_logic; UFMSNout: out Std_logic;
|
|
WBDATO7out: out Std_logic; WBDATO7in: in Std_logic;
|
|
WBDATO6out: out Std_logic; WBDATO6in: in Std_logic;
|
|
WBDATO5out: out Std_logic; WBDATO5in: in Std_logic;
|
|
WBDATO4out: out Std_logic; WBDATO4in: in Std_logic;
|
|
WBDATO3out: out Std_logic; WBDATO3in: in Std_logic;
|
|
WBDATO2out: out Std_logic; WBDATO2in: in Std_logic;
|
|
WBDATO1out: out Std_logic; WBDATO1in: in Std_logic;
|
|
WBDATO0out: out Std_logic; WBDATO0in: in Std_logic;
|
|
WBACKOout: out Std_logic; WBACKOin: in Std_logic;
|
|
PLLCLKOout: out Std_logic; PLLCLKOin: in Std_logic;
|
|
PLLRSTOout: out Std_logic; PLLRSTOin: in Std_logic;
|
|
PLL0STBOout: out Std_logic; PLL0STBOin: in Std_logic;
|
|
PLL1STBOout: out Std_logic; PLL1STBOin: in Std_logic;
|
|
PLLWEOout: out Std_logic; PLLWEOin: in Std_logic;
|
|
PLLADRO4out: out Std_logic; PLLADRO4in: in Std_logic;
|
|
PLLADRO3out: out Std_logic; PLLADRO3in: in Std_logic;
|
|
PLLADRO2out: out Std_logic; PLLADRO2in: in Std_logic;
|
|
PLLADRO1out: out Std_logic; PLLADRO1in: in Std_logic;
|
|
PLLADRO0out: out Std_logic; PLLADRO0in: in Std_logic;
|
|
PLLDATO7out: out Std_logic; PLLDATO7in: in Std_logic;
|
|
PLLDATO6out: out Std_logic; PLLDATO6in: in Std_logic;
|
|
PLLDATO5out: out Std_logic; PLLDATO5in: in Std_logic;
|
|
PLLDATO4out: out Std_logic; PLLDATO4in: in Std_logic;
|
|
PLLDATO3out: out Std_logic; PLLDATO3in: in Std_logic;
|
|
PLLDATO2out: out Std_logic; PLLDATO2in: in Std_logic;
|
|
PLLDATO1out: out Std_logic; PLLDATO1in: in Std_logic;
|
|
PLLDATO0out: out Std_logic; PLLDATO0in: in Std_logic;
|
|
I2C1SCLOout: out Std_logic; I2C1SCLOin: in Std_logic;
|
|
I2C1SCLOENout: out Std_logic; I2C1SCLOENin: in Std_logic;
|
|
I2C1SDAOout: out Std_logic; I2C1SDAOin: in Std_logic;
|
|
I2C1SDAOENout: out Std_logic; I2C1SDAOENin: in Std_logic;
|
|
I2C2SCLOout: out Std_logic; I2C2SCLOin: in Std_logic;
|
|
I2C2SCLOENout: out Std_logic; I2C2SCLOENin: in Std_logic;
|
|
I2C2SDAOout: out Std_logic; I2C2SDAOin: in Std_logic;
|
|
I2C2SDAOENout: out Std_logic; I2C2SDAOENin: in Std_logic;
|
|
I2C1IRQOout: out Std_logic; I2C1IRQOin: in Std_logic;
|
|
I2C2IRQOout: out Std_logic; I2C2IRQOin: in Std_logic;
|
|
SPISCKOout: out Std_logic; SPISCKOin: in Std_logic;
|
|
SPISCKENout: out Std_logic; SPISCKENin: in Std_logic;
|
|
SPIMISOOout: out Std_logic; SPIMISOOin: in Std_logic;
|
|
SPIMISOENout: out Std_logic; SPIMISOENin: in Std_logic;
|
|
SPIMOSIOout: out Std_logic; SPIMOSIOin: in Std_logic;
|
|
SPIMOSIENout: out Std_logic; SPIMOSIENin: in Std_logic;
|
|
SPIMCSN0out: out Std_logic; SPIMCSN0in: in Std_logic;
|
|
SPIMCSN1out: out Std_logic; SPIMCSN1in: in Std_logic;
|
|
SPIMCSN2out: out Std_logic; SPIMCSN2in: in Std_logic;
|
|
SPIMCSN3out: out Std_logic; SPIMCSN3in: in Std_logic;
|
|
SPIMCSN4out: out Std_logic; SPIMCSN4in: in Std_logic;
|
|
SPIMCSN5out: out Std_logic; SPIMCSN5in: in Std_logic;
|
|
SPIMCSN6out: out Std_logic; SPIMCSN6in: in Std_logic;
|
|
SPIMCSN7out: out Std_logic; SPIMCSN7in: in Std_logic;
|
|
SPICSNENout: out Std_logic; SPICSNENin: in Std_logic;
|
|
SPIIRQOout: out Std_logic; SPIIRQOin: in Std_logic;
|
|
TCINTout: out Std_logic; TCINTin: in Std_logic;
|
|
TCOCout: out Std_logic; TCOCin: in Std_logic;
|
|
WBCUFMIRQout: out Std_logic; WBCUFMIRQin: in Std_logic;
|
|
CFGWAKEout: out Std_logic; CFGWAKEin: in Std_logic;
|
|
CFGSTDBYout: out Std_logic; CFGSTDBYin: in Std_logic);
|
|
end component;
|
|
begin
|
|
INST10: EFB
|
|
generic map (DEV_DENSITY => "640L", EFB_I2C1 => "DISABLED",
|
|
EFB_I2C2 => "DISABLED", EFB_SPI => "DISABLED",
|
|
EFB_TC => "DISABLED", EFB_TC_PORTMODE => "WB",
|
|
EFB_UFM => "ENABLED", EFB_WB_CLK_FREQ => "66.7",
|
|
GSR => "ENABLED", I2C1_ADDRESSING => "7BIT",
|
|
I2C1_BUS_PERF => "100kHz", I2C1_CLK_DIVIDER => 1,
|
|
I2C1_GEN_CALL => "DISABLED", I2C1_SLAVE_ADDR => "0b1000001",
|
|
I2C1_WAKEUP => "DISABLED", I2C2_ADDRESSING => "7BIT",
|
|
I2C2_BUS_PERF => "100kHz", I2C2_CLK_DIVIDER => 1,
|
|
I2C2_GEN_CALL => "DISABLED", I2C2_SLAVE_ADDR => "0b1000010",
|
|
I2C2_WAKEUP => "DISABLED", SPI_CLK_DIVIDER => 1,
|
|
SPI_CLK_INV => "DISABLED", SPI_INTR_RXOVR => "DISABLED",
|
|
SPI_INTR_RXRDY => "DISABLED", SPI_INTR_TXOVR => "DISABLED",
|
|
SPI_INTR_TXRDY => "DISABLED", SPI_LSB_FIRST => "DISABLED",
|
|
SPI_MODE => "MASTER", SPI_PHASE_ADJ => "DISABLED",
|
|
SPI_SLAVE_HANDSHAKE => "DISABLED", SPI_WAKEUP => "DISABLED",
|
|
TC_CCLK_SEL => 1, TC_ICAPTURE => "DISABLED",
|
|
TC_ICR_INT => "OFF", TC_MODE => "CTCM", TC_OCR_INT => "OFF",
|
|
TC_OCR_SET => 32767, TC_OC_MODE => "TOGGLE",
|
|
TC_OVERFLOW => "DISABLED", TC_OV_INT => "OFF",
|
|
TC_RESETN => "ENABLED", TC_SCLK_SEL => "PCLOCK",
|
|
TC_TOP_SEL => "OFF", TC_TOP_SET => 65535,
|
|
UFM_INIT_ALL_ZEROS => "DISABLED",
|
|
UFM_INIT_FILE_FORMAT => "HEX",
|
|
UFM_INIT_FILE_NAME => "../RAM2GS-LCMXO2.mem",
|
|
UFM_INIT_PAGES => 1, UFM_INIT_START_PAGE => 190)
|
|
port map (WBCLKI=>WBCLKI_buf, WBRSTI=>WBRSTI_buf, WBCYCI=>WBCYCI_buf,
|
|
WBSTBI=>WBSTBI_buf, WBWEI=>WBWEI_buf, WBADRI7=>WBADRI7_buf,
|
|
WBADRI6=>WBADRI6_buf, WBADRI5=>WBADRI5_buf,
|
|
WBADRI4=>WBADRI4_buf, WBADRI3=>WBADRI3_buf,
|
|
WBADRI2=>WBADRI2_buf, WBADRI1=>WBADRI1_buf,
|
|
WBADRI0=>WBADRI0_buf, WBDATI7=>WBDATI7_buf,
|
|
WBDATI6=>WBDATI6_buf, WBDATI5=>WBDATI5_buf,
|
|
WBDATI4=>WBDATI4_buf, WBDATI3=>WBDATI3_buf,
|
|
WBDATI2=>WBDATI2_buf, WBDATI1=>WBDATI1_buf,
|
|
WBDATI0=>WBDATI0_buf, PLL0DATI7=>PLL0DATI7_buf,
|
|
PLL0DATI6=>PLL0DATI6_buf, PLL0DATI5=>PLL0DATI5_buf,
|
|
PLL0DATI4=>PLL0DATI4_buf, PLL0DATI3=>PLL0DATI3_buf,
|
|
PLL0DATI2=>PLL0DATI2_buf, PLL0DATI1=>PLL0DATI1_buf,
|
|
PLL0DATI0=>PLL0DATI0_buf, PLL0ACKI=>PLL0ACKI_buf,
|
|
PLL1DATI7=>PLL1DATI7_buf, PLL1DATI6=>PLL1DATI6_buf,
|
|
PLL1DATI5=>PLL1DATI5_buf, PLL1DATI4=>PLL1DATI4_buf,
|
|
PLL1DATI3=>PLL1DATI3_buf, PLL1DATI2=>PLL1DATI2_buf,
|
|
PLL1DATI1=>PLL1DATI1_buf, PLL1DATI0=>PLL1DATI0_buf,
|
|
PLL1ACKI=>PLL1ACKI_buf, I2C1SCLI=>I2C1SCLI_buf,
|
|
I2C1SDAI=>I2C1SDAI_buf, I2C2SCLI=>I2C2SCLI_buf,
|
|
I2C2SDAI=>I2C2SDAI_buf, SPISCKI=>SPISCKI_buf,
|
|
SPIMISOI=>SPIMISOI_buf, SPIMOSII=>SPIMOSII_buf,
|
|
SPISCSN=>SPISCSN_buf, TCCLKI=>TCCLKI_buf, TCRSTN=>TCRSTN_buf,
|
|
TCIC=>TCIC_buf, UFMSN=>UFMSN_buf, WBDATO7=>WBDATO7_buf,
|
|
WBDATO6=>WBDATO6_buf, WBDATO5=>WBDATO5_buf,
|
|
WBDATO4=>WBDATO4_buf, WBDATO3=>WBDATO3_buf,
|
|
WBDATO2=>WBDATO2_buf, WBDATO1=>WBDATO1_buf,
|
|
WBDATO0=>WBDATO0_buf, WBACKO=>WBACKO_buf, PLLCLKO=>PLLCLKO_buf,
|
|
PLLRSTO=>PLLRSTO_buf, PLL0STBO=>PLL0STBO_buf,
|
|
PLL1STBO=>PLL1STBO_buf, PLLWEO=>PLLWEO_buf,
|
|
PLLADRO4=>PLLADRO4_buf, PLLADRO3=>PLLADRO3_buf,
|
|
PLLADRO2=>PLLADRO2_buf, PLLADRO1=>PLLADRO1_buf,
|
|
PLLADRO0=>PLLADRO0_buf, PLLDATO7=>PLLDATO7_buf,
|
|
PLLDATO6=>PLLDATO6_buf, PLLDATO5=>PLLDATO5_buf,
|
|
PLLDATO4=>PLLDATO4_buf, PLLDATO3=>PLLDATO3_buf,
|
|
PLLDATO2=>PLLDATO2_buf, PLLDATO1=>PLLDATO1_buf,
|
|
PLLDATO0=>PLLDATO0_buf, I2C1SCLO=>I2C1SCLO_buf,
|
|
I2C1SCLOEN=>I2C1SCLOEN_buf, I2C1SDAO=>I2C1SDAO_buf,
|
|
I2C1SDAOEN=>I2C1SDAOEN_buf, I2C2SCLO=>I2C2SCLO_buf,
|
|
I2C2SCLOEN=>I2C2SCLOEN_buf, I2C2SDAO=>I2C2SDAO_buf,
|
|
I2C2SDAOEN=>I2C2SDAOEN_buf, I2C1IRQO=>I2C1IRQO_buf,
|
|
I2C2IRQO=>I2C2IRQO_buf, SPISCKO=>SPISCKO_buf,
|
|
SPISCKEN=>SPISCKEN_buf, SPIMISOO=>SPIMISOO_buf,
|
|
SPIMISOEN=>SPIMISOEN_buf, SPIMOSIO=>SPIMOSIO_buf,
|
|
SPIMOSIEN=>SPIMOSIEN_buf, SPIMCSN0=>SPIMCSN0_buf,
|
|
SPIMCSN1=>SPIMCSN1_buf, SPIMCSN2=>SPIMCSN2_buf,
|
|
SPIMCSN3=>SPIMCSN3_buf, SPIMCSN4=>SPIMCSN4_buf,
|
|
SPIMCSN5=>SPIMCSN5_buf, SPIMCSN6=>SPIMCSN6_buf,
|
|
SPIMCSN7=>SPIMCSN7_buf, SPICSNEN=>SPICSNEN_buf,
|
|
SPIIRQO=>SPIIRQO_buf, TCINT=>TCINT_buf, TCOC=>TCOC_buf,
|
|
WBCUFMIRQ=>WBCUFMIRQ_buf, CFGWAKE=>CFGWAKE_buf,
|
|
CFGSTDBY=>CFGSTDBY_buf);
|
|
INST20: EFB_Buffer_Block
|
|
port map (WBCLKIin=>WBCLKI, WBCLKIout=>WBCLKI_buf, WBRSTIin=>WBRSTI,
|
|
WBRSTIout=>WBRSTI_buf, WBCYCIin=>WBCYCI, WBCYCIout=>WBCYCI_buf,
|
|
WBSTBIin=>WBSTBI, WBSTBIout=>WBSTBI_buf, WBWEIin=>WBWEI,
|
|
WBWEIout=>WBWEI_buf, WBADRI7in=>WBADRI7,
|
|
WBADRI7out=>WBADRI7_buf, WBADRI6in=>WBADRI6,
|
|
WBADRI6out=>WBADRI6_buf, WBADRI5in=>WBADRI5,
|
|
WBADRI5out=>WBADRI5_buf, WBADRI4in=>WBADRI4,
|
|
WBADRI4out=>WBADRI4_buf, WBADRI3in=>WBADRI3,
|
|
WBADRI3out=>WBADRI3_buf, WBADRI2in=>WBADRI2,
|
|
WBADRI2out=>WBADRI2_buf, WBADRI1in=>WBADRI1,
|
|
WBADRI1out=>WBADRI1_buf, WBADRI0in=>WBADRI0,
|
|
WBADRI0out=>WBADRI0_buf, WBDATI7in=>WBDATI7,
|
|
WBDATI7out=>WBDATI7_buf, WBDATI6in=>WBDATI6,
|
|
WBDATI6out=>WBDATI6_buf, WBDATI5in=>WBDATI5,
|
|
WBDATI5out=>WBDATI5_buf, WBDATI4in=>WBDATI4,
|
|
WBDATI4out=>WBDATI4_buf, WBDATI3in=>WBDATI3,
|
|
WBDATI3out=>WBDATI3_buf, WBDATI2in=>WBDATI2,
|
|
WBDATI2out=>WBDATI2_buf, WBDATI1in=>WBDATI1,
|
|
WBDATI1out=>WBDATI1_buf, WBDATI0in=>WBDATI0,
|
|
WBDATI0out=>WBDATI0_buf, PLL0DATI7in=>PLL0DATI7,
|
|
PLL0DATI7out=>PLL0DATI7_buf, PLL0DATI6in=>PLL0DATI6,
|
|
PLL0DATI6out=>PLL0DATI6_buf, PLL0DATI5in=>PLL0DATI5,
|
|
PLL0DATI5out=>PLL0DATI5_buf, PLL0DATI4in=>PLL0DATI4,
|
|
PLL0DATI4out=>PLL0DATI4_buf, PLL0DATI3in=>PLL0DATI3,
|
|
PLL0DATI3out=>PLL0DATI3_buf, PLL0DATI2in=>PLL0DATI2,
|
|
PLL0DATI2out=>PLL0DATI2_buf, PLL0DATI1in=>PLL0DATI1,
|
|
PLL0DATI1out=>PLL0DATI1_buf, PLL0DATI0in=>PLL0DATI0,
|
|
PLL0DATI0out=>PLL0DATI0_buf, PLL0ACKIin=>PLL0ACKI,
|
|
PLL0ACKIout=>PLL0ACKI_buf, PLL1DATI7in=>PLL1DATI7,
|
|
PLL1DATI7out=>PLL1DATI7_buf, PLL1DATI6in=>PLL1DATI6,
|
|
PLL1DATI6out=>PLL1DATI6_buf, PLL1DATI5in=>PLL1DATI5,
|
|
PLL1DATI5out=>PLL1DATI5_buf, PLL1DATI4in=>PLL1DATI4,
|
|
PLL1DATI4out=>PLL1DATI4_buf, PLL1DATI3in=>PLL1DATI3,
|
|
PLL1DATI3out=>PLL1DATI3_buf, PLL1DATI2in=>PLL1DATI2,
|
|
PLL1DATI2out=>PLL1DATI2_buf, PLL1DATI1in=>PLL1DATI1,
|
|
PLL1DATI1out=>PLL1DATI1_buf, PLL1DATI0in=>PLL1DATI0,
|
|
PLL1DATI0out=>PLL1DATI0_buf, PLL1ACKIin=>PLL1ACKI,
|
|
PLL1ACKIout=>PLL1ACKI_buf, I2C1SCLIin=>I2C1SCLI,
|
|
I2C1SCLIout=>I2C1SCLI_buf, I2C1SDAIin=>I2C1SDAI,
|
|
I2C1SDAIout=>I2C1SDAI_buf, I2C2SCLIin=>I2C2SCLI,
|
|
I2C2SCLIout=>I2C2SCLI_buf, I2C2SDAIin=>I2C2SDAI,
|
|
I2C2SDAIout=>I2C2SDAI_buf, SPISCKIin=>SPISCKI,
|
|
SPISCKIout=>SPISCKI_buf, SPIMISOIin=>SPIMISOI,
|
|
SPIMISOIout=>SPIMISOI_buf, SPIMOSIIin=>SPIMOSII,
|
|
SPIMOSIIout=>SPIMOSII_buf, SPISCSNin=>SPISCSN,
|
|
SPISCSNout=>SPISCSN_buf, TCCLKIin=>TCCLKI,
|
|
TCCLKIout=>TCCLKI_buf, TCRSTNin=>TCRSTN, TCRSTNout=>TCRSTN_buf,
|
|
TCICin=>TCIC, TCICout=>TCIC_buf, UFMSNin=>UFMSN,
|
|
UFMSNout=>UFMSN_buf, WBDATO7out=>WBDATO7,
|
|
WBDATO7in=>WBDATO7_buf, WBDATO6out=>WBDATO6,
|
|
WBDATO6in=>WBDATO6_buf, WBDATO5out=>WBDATO5,
|
|
WBDATO5in=>WBDATO5_buf, WBDATO4out=>WBDATO4,
|
|
WBDATO4in=>WBDATO4_buf, WBDATO3out=>WBDATO3,
|
|
WBDATO3in=>WBDATO3_buf, WBDATO2out=>WBDATO2,
|
|
WBDATO2in=>WBDATO2_buf, WBDATO1out=>WBDATO1,
|
|
WBDATO1in=>WBDATO1_buf, WBDATO0out=>WBDATO0,
|
|
WBDATO0in=>WBDATO0_buf, WBACKOout=>WBACKO,
|
|
WBACKOin=>WBACKO_buf, PLLCLKOout=>PLLCLKO,
|
|
PLLCLKOin=>PLLCLKO_buf, PLLRSTOout=>PLLRSTO,
|
|
PLLRSTOin=>PLLRSTO_buf, PLL0STBOout=>PLL0STBO,
|
|
PLL0STBOin=>PLL0STBO_buf, PLL1STBOout=>PLL1STBO,
|
|
PLL1STBOin=>PLL1STBO_buf, PLLWEOout=>PLLWEO,
|
|
PLLWEOin=>PLLWEO_buf, PLLADRO4out=>PLLADRO4,
|
|
PLLADRO4in=>PLLADRO4_buf, PLLADRO3out=>PLLADRO3,
|
|
PLLADRO3in=>PLLADRO3_buf, PLLADRO2out=>PLLADRO2,
|
|
PLLADRO2in=>PLLADRO2_buf, PLLADRO1out=>PLLADRO1,
|
|
PLLADRO1in=>PLLADRO1_buf, PLLADRO0out=>PLLADRO0,
|
|
PLLADRO0in=>PLLADRO0_buf, PLLDATO7out=>PLLDATO7,
|
|
PLLDATO7in=>PLLDATO7_buf, PLLDATO6out=>PLLDATO6,
|
|
PLLDATO6in=>PLLDATO6_buf, PLLDATO5out=>PLLDATO5,
|
|
PLLDATO5in=>PLLDATO5_buf, PLLDATO4out=>PLLDATO4,
|
|
PLLDATO4in=>PLLDATO4_buf, PLLDATO3out=>PLLDATO3,
|
|
PLLDATO3in=>PLLDATO3_buf, PLLDATO2out=>PLLDATO2,
|
|
PLLDATO2in=>PLLDATO2_buf, PLLDATO1out=>PLLDATO1,
|
|
PLLDATO1in=>PLLDATO1_buf, PLLDATO0out=>PLLDATO0,
|
|
PLLDATO0in=>PLLDATO0_buf, I2C1SCLOout=>I2C1SCLO,
|
|
I2C1SCLOin=>I2C1SCLO_buf, I2C1SCLOENout=>I2C1SCLOEN,
|
|
I2C1SCLOENin=>I2C1SCLOEN_buf, I2C1SDAOout=>I2C1SDAO,
|
|
I2C1SDAOin=>I2C1SDAO_buf, I2C1SDAOENout=>I2C1SDAOEN,
|
|
I2C1SDAOENin=>I2C1SDAOEN_buf, I2C2SCLOout=>I2C2SCLO,
|
|
I2C2SCLOin=>I2C2SCLO_buf, I2C2SCLOENout=>I2C2SCLOEN,
|
|
I2C2SCLOENin=>I2C2SCLOEN_buf, I2C2SDAOout=>I2C2SDAO,
|
|
I2C2SDAOin=>I2C2SDAO_buf, I2C2SDAOENout=>I2C2SDAOEN,
|
|
I2C2SDAOENin=>I2C2SDAOEN_buf, I2C1IRQOout=>I2C1IRQO,
|
|
I2C1IRQOin=>I2C1IRQO_buf, I2C2IRQOout=>I2C2IRQO,
|
|
I2C2IRQOin=>I2C2IRQO_buf, SPISCKOout=>SPISCKO,
|
|
SPISCKOin=>SPISCKO_buf, SPISCKENout=>SPISCKEN,
|
|
SPISCKENin=>SPISCKEN_buf, SPIMISOOout=>SPIMISOO,
|
|
SPIMISOOin=>SPIMISOO_buf, SPIMISOENout=>SPIMISOEN,
|
|
SPIMISOENin=>SPIMISOEN_buf, SPIMOSIOout=>SPIMOSIO,
|
|
SPIMOSIOin=>SPIMOSIO_buf, SPIMOSIENout=>SPIMOSIEN,
|
|
SPIMOSIENin=>SPIMOSIEN_buf, SPIMCSN0out=>SPIMCSN0,
|
|
SPIMCSN0in=>SPIMCSN0_buf, SPIMCSN1out=>SPIMCSN1,
|
|
SPIMCSN1in=>SPIMCSN1_buf, SPIMCSN2out=>SPIMCSN2,
|
|
SPIMCSN2in=>SPIMCSN2_buf, SPIMCSN3out=>SPIMCSN3,
|
|
SPIMCSN3in=>SPIMCSN3_buf, SPIMCSN4out=>SPIMCSN4,
|
|
SPIMCSN4in=>SPIMCSN4_buf, SPIMCSN5out=>SPIMCSN5,
|
|
SPIMCSN5in=>SPIMCSN5_buf, SPIMCSN6out=>SPIMCSN6,
|
|
SPIMCSN6in=>SPIMCSN6_buf, SPIMCSN7out=>SPIMCSN7,
|
|
SPIMCSN7in=>SPIMCSN7_buf, SPICSNENout=>SPICSNEN,
|
|
SPICSNENin=>SPICSNEN_buf, SPIIRQOout=>SPIIRQO,
|
|
SPIIRQOin=>SPIIRQO_buf, TCINTout=>TCINT, TCINTin=>TCINT_buf,
|
|
TCOCout=>TCOC, TCOCin=>TCOC_buf, WBCUFMIRQout=>WBCUFMIRQ,
|
|
WBCUFMIRQin=>WBCUFMIRQ_buf, CFGWAKEout=>CFGWAKE,
|
|
CFGWAKEin=>CFGWAKE_buf, CFGSTDBYout=>CFGSTDBY,
|
|
CFGSTDBYin=>CFGSTDBY_buf);
|
|
end Structure;
|
|
|
|
-- entity ufmefb_EFBInst_0
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity ufmefb_EFBInst_0 is
|
|
port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic;
|
|
WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic;
|
|
WBADRI1: in Std_logic; WBADRI2: in Std_logic; WBADRI3: in Std_logic;
|
|
WBADRI4: in Std_logic; WBADRI5: in Std_logic; WBADRI6: in Std_logic;
|
|
WBADRI7: in Std_logic; WBDATI0: in Std_logic; WBDATI1: in Std_logic;
|
|
WBDATI2: in Std_logic; WBDATI3: in Std_logic; WBDATI4: in Std_logic;
|
|
WBDATI5: in Std_logic; WBDATI6: in Std_logic; WBDATI7: in Std_logic;
|
|
WBDATO0: out Std_logic; WBDATO1: out Std_logic;
|
|
WBACKO: out Std_logic);
|
|
|
|
|
|
|
|
end ufmefb_EFBInst_0;
|
|
|
|
architecture Structure of ufmefb_EFBInst_0 is
|
|
signal VCCI: Std_logic;
|
|
signal GNDI: Std_logic;
|
|
component vcc
|
|
port (PWR1: out Std_logic);
|
|
end component;
|
|
component gnd
|
|
port (PWR0: out Std_logic);
|
|
end component;
|
|
component EFBB
|
|
port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic;
|
|
WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic;
|
|
WBADRI1: in Std_logic; WBADRI2: in Std_logic;
|
|
WBADRI3: in Std_logic; WBADRI4: in Std_logic;
|
|
WBADRI5: in Std_logic; WBADRI6: in Std_logic;
|
|
WBADRI7: in Std_logic; WBDATI0: in Std_logic;
|
|
WBDATI1: in Std_logic; WBDATI2: in Std_logic;
|
|
WBDATI3: in Std_logic; WBDATI4: in Std_logic;
|
|
WBDATI5: in Std_logic; WBDATI6: in Std_logic;
|
|
WBDATI7: in Std_logic; WBDATO0: out Std_logic;
|
|
WBDATO1: out Std_logic; WBDATO2: out Std_logic;
|
|
WBDATO3: out Std_logic; WBDATO4: out Std_logic;
|
|
WBDATO5: out Std_logic; WBDATO6: out Std_logic;
|
|
WBDATO7: out Std_logic; WBACKO: out Std_logic;
|
|
WBCUFMIRQ: out Std_logic; UFMSN: in Std_logic;
|
|
CFGWAKE: out Std_logic; CFGSTDBY: out Std_logic;
|
|
I2C1SCLI: in Std_logic; I2C1SCLO: out Std_logic;
|
|
I2C1SCLOEN: out Std_logic; I2C1SDAI: in Std_logic;
|
|
I2C1SDAO: out Std_logic; I2C1SDAOEN: out Std_logic;
|
|
I2C2SCLI: in Std_logic; I2C2SCLO: out Std_logic;
|
|
I2C2SCLOEN: out Std_logic; I2C2SDAI: in Std_logic;
|
|
I2C2SDAO: out Std_logic; I2C2SDAOEN: out Std_logic;
|
|
I2C1IRQO: out Std_logic; I2C2IRQO: out Std_logic;
|
|
SPISCKI: in Std_logic; SPISCKO: out Std_logic;
|
|
SPISCKEN: out Std_logic; SPIMISOI: in Std_logic;
|
|
SPIMISOO: out Std_logic; SPIMISOEN: out Std_logic;
|
|
SPIMOSII: in Std_logic; SPIMOSIO: out Std_logic;
|
|
SPIMOSIEN: out Std_logic; SPIMCSN0: out Std_logic;
|
|
SPIMCSN1: out Std_logic; SPIMCSN2: out Std_logic;
|
|
SPIMCSN3: out Std_logic; SPIMCSN4: out Std_logic;
|
|
SPIMCSN5: out Std_logic; SPIMCSN6: out Std_logic;
|
|
SPIMCSN7: out Std_logic; SPICSNEN: out Std_logic;
|
|
SPISCSN: in Std_logic; SPIIRQO: out Std_logic;
|
|
TCCLKI: in Std_logic; TCRSTN: in Std_logic; TCIC: in Std_logic;
|
|
TCINT: out Std_logic; TCOC: out Std_logic; PLLCLKO: out Std_logic;
|
|
PLLRSTO: out Std_logic; PLL0STBO: out Std_logic;
|
|
PLL1STBO: out Std_logic; PLLWEO: out Std_logic;
|
|
PLLADRO0: out Std_logic; PLLADRO1: out Std_logic;
|
|
PLLADRO2: out Std_logic; PLLADRO3: out Std_logic;
|
|
PLLADRO4: out Std_logic; PLLDATO0: out Std_logic;
|
|
PLLDATO1: out Std_logic; PLLDATO2: out Std_logic;
|
|
PLLDATO3: out Std_logic; PLLDATO4: out Std_logic;
|
|
PLLDATO5: out Std_logic; PLLDATO6: out Std_logic;
|
|
PLLDATO7: out Std_logic; PLL0DATI0: in Std_logic;
|
|
PLL0DATI1: in Std_logic; PLL0DATI2: in Std_logic;
|
|
PLL0DATI3: in Std_logic; PLL0DATI4: in Std_logic;
|
|
PLL0DATI5: in Std_logic; PLL0DATI6: in Std_logic;
|
|
PLL0DATI7: in Std_logic; PLL0ACKI: in Std_logic;
|
|
PLL1DATI0: in Std_logic; PLL1DATI1: in Std_logic;
|
|
PLL1DATI2: in Std_logic; PLL1DATI3: in Std_logic;
|
|
PLL1DATI4: in Std_logic; PLL1DATI5: in Std_logic;
|
|
PLL1DATI6: in Std_logic; PLL1DATI7: in Std_logic;
|
|
PLL1ACKI: in Std_logic);
|
|
end component;
|
|
begin
|
|
ufmefb_EFBInst_0_EFB: EFBB
|
|
port map (WBCLKI=>WBCLKI, WBRSTI=>WBRSTI, WBCYCI=>WBCYCI, WBSTBI=>WBSTBI,
|
|
WBWEI=>WBWEI, WBADRI0=>WBADRI0, WBADRI1=>WBADRI1,
|
|
WBADRI2=>WBADRI2, WBADRI3=>WBADRI3, WBADRI4=>WBADRI4,
|
|
WBADRI5=>WBADRI5, WBADRI6=>WBADRI6, WBADRI7=>WBADRI7,
|
|
WBDATI0=>WBDATI0, WBDATI1=>WBDATI1, WBDATI2=>WBDATI2,
|
|
WBDATI3=>WBDATI3, WBDATI4=>WBDATI4, WBDATI5=>WBDATI5,
|
|
WBDATI6=>WBDATI6, WBDATI7=>WBDATI7, WBDATO0=>WBDATO0,
|
|
WBDATO1=>WBDATO1, WBDATO2=>open, WBDATO3=>open, WBDATO4=>open,
|
|
WBDATO5=>open, WBDATO6=>open, WBDATO7=>open, WBACKO=>WBACKO,
|
|
WBCUFMIRQ=>open, UFMSN=>VCCI, CFGWAKE=>open, CFGSTDBY=>open,
|
|
I2C1SCLI=>GNDI, I2C1SCLO=>open, I2C1SCLOEN=>open,
|
|
I2C1SDAI=>GNDI, I2C1SDAO=>open, I2C1SDAOEN=>open,
|
|
I2C2SCLI=>GNDI, I2C2SCLO=>open, I2C2SCLOEN=>open,
|
|
I2C2SDAI=>GNDI, I2C2SDAO=>open, I2C2SDAOEN=>open,
|
|
I2C1IRQO=>open, I2C2IRQO=>open, SPISCKI=>GNDI, SPISCKO=>open,
|
|
SPISCKEN=>open, SPIMISOI=>GNDI, SPIMISOO=>open,
|
|
SPIMISOEN=>open, SPIMOSII=>GNDI, SPIMOSIO=>open,
|
|
SPIMOSIEN=>open, SPIMCSN0=>open, SPIMCSN1=>open,
|
|
SPIMCSN2=>open, SPIMCSN3=>open, SPIMCSN4=>open, SPIMCSN5=>open,
|
|
SPIMCSN6=>open, SPIMCSN7=>open, SPICSNEN=>open, SPISCSN=>GNDI,
|
|
SPIIRQO=>open, TCCLKI=>GNDI, TCRSTN=>GNDI, TCIC=>GNDI,
|
|
TCINT=>open, TCOC=>open, PLLCLKO=>open, PLLRSTO=>open,
|
|
PLL0STBO=>open, PLL1STBO=>open, PLLWEO=>open, PLLADRO0=>open,
|
|
PLLADRO1=>open, PLLADRO2=>open, PLLADRO3=>open, PLLADRO4=>open,
|
|
PLLDATO0=>open, PLLDATO1=>open, PLLDATO2=>open, PLLDATO3=>open,
|
|
PLLDATO4=>open, PLLDATO5=>open, PLLDATO6=>open, PLLDATO7=>open,
|
|
PLL0DATI0=>GNDI, PLL0DATI1=>GNDI, PLL0DATI2=>GNDI,
|
|
PLL0DATI3=>GNDI, PLL0DATI4=>GNDI, PLL0DATI5=>GNDI,
|
|
PLL0DATI6=>GNDI, PLL0DATI7=>GNDI, PLL0ACKI=>GNDI,
|
|
PLL1DATI0=>GNDI, PLL1DATI1=>GNDI, PLL1DATI2=>GNDI,
|
|
PLL1DATI3=>GNDI, PLL1DATI4=>GNDI, PLL1DATI5=>GNDI,
|
|
PLL1DATI6=>GNDI, PLL1DATI7=>GNDI, PLL1ACKI=>GNDI);
|
|
DRIVEVCC: vcc
|
|
port map (PWR1=>VCCI);
|
|
DRIVEGND: gnd
|
|
port map (PWR0=>GNDI);
|
|
end Structure;
|
|
|
|
-- entity RAM2GS
|
|
library IEEE, vital2000, MACHXO2;
|
|
use IEEE.STD_LOGIC_1164.all;
|
|
use vital2000.vital_timing.all;
|
|
use MACHXO2.COMPONENTS.ALL;
|
|
|
|
entity RAM2GS is
|
|
port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0);
|
|
CROW: in Std_logic_vector (1 downto 0);
|
|
Din: in Std_logic_vector (7 downto 0);
|
|
Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic;
|
|
nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic;
|
|
RBA: out Std_logic_vector (1 downto 0);
|
|
RA: out Std_logic_vector (11 downto 0);
|
|
RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic;
|
|
RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic;
|
|
nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic;
|
|
RDQML: out Std_logic);
|
|
|
|
|
|
|
|
end RAM2GS;
|
|
|
|
architecture Structure of RAM2GS is
|
|
signal FS_0: Std_logic;
|
|
signal FS_s_0: Std_logic;
|
|
signal RCLK_c: Std_logic;
|
|
signal FS_cry_0: Std_logic;
|
|
signal FS_17: Std_logic;
|
|
signal FS_s_17: Std_logic;
|
|
signal FS_cry_16: Std_logic;
|
|
signal FS_16: Std_logic;
|
|
signal FS_15: Std_logic;
|
|
signal FS_s_16: Std_logic;
|
|
signal FS_s_15: Std_logic;
|
|
signal FS_cry_14: Std_logic;
|
|
signal FS_14: Std_logic;
|
|
signal FS_13: Std_logic;
|
|
signal FS_s_14: Std_logic;
|
|
signal FS_s_13: Std_logic;
|
|
signal FS_cry_12: Std_logic;
|
|
signal FS_12: Std_logic;
|
|
signal FS_11: Std_logic;
|
|
signal FS_s_12: Std_logic;
|
|
signal FS_s_11: Std_logic;
|
|
signal FS_cry_10: Std_logic;
|
|
signal FS_10: Std_logic;
|
|
signal FS_9: Std_logic;
|
|
signal FS_s_10: Std_logic;
|
|
signal FS_s_9: Std_logic;
|
|
signal FS_cry_8: Std_logic;
|
|
signal FS_8: Std_logic;
|
|
signal FS_7: Std_logic;
|
|
signal FS_s_8: Std_logic;
|
|
signal FS_s_7: Std_logic;
|
|
signal FS_cry_6: Std_logic;
|
|
signal FS_6: Std_logic;
|
|
signal FS_5: Std_logic;
|
|
signal FS_s_6: Std_logic;
|
|
signal FS_s_5: Std_logic;
|
|
signal FS_cry_4: Std_logic;
|
|
signal FS_4: Std_logic;
|
|
signal FS_3: Std_logic;
|
|
signal FS_s_4: Std_logic;
|
|
signal FS_s_3: Std_logic;
|
|
signal FS_cry_2: Std_logic;
|
|
signal FS_2: Std_logic;
|
|
signal FS_1: Std_logic;
|
|
signal FS_s_2: Std_logic;
|
|
signal FS_s_1: Std_logic;
|
|
signal N_304: Std_logic;
|
|
signal CmdEnable17_5: Std_logic;
|
|
signal CmdEnable17_4: Std_logic;
|
|
signal ADWR_7: Std_logic;
|
|
signal CmdEnable16: Std_logic;
|
|
signal CmdEnable17: Std_logic;
|
|
signal un1_ADWR: Std_logic;
|
|
signal ADSubmitted: Std_logic;
|
|
signal ADSubmitted_r: Std_logic;
|
|
signal PHI2_c: Std_logic;
|
|
signal CmdEnable16_5: Std_logic;
|
|
signal CmdEnable16_4: Std_logic;
|
|
signal C1WR_7: Std_logic;
|
|
signal C1WR_2: Std_logic;
|
|
signal C1Submitted: Std_logic;
|
|
signal C1Submitted_s: Std_logic;
|
|
signal nCCAS_c: Std_logic;
|
|
signal nCCAS_c_i: Std_logic;
|
|
signal CASr: Std_logic;
|
|
signal CASr2: Std_logic;
|
|
signal S_1: Std_logic;
|
|
signal RASr2: Std_logic;
|
|
signal IS_3: Std_logic;
|
|
signal CO0: Std_logic;
|
|
signal N_79_i: Std_logic;
|
|
signal Ready_0_sqmuxa_0_a3_2: Std_logic;
|
|
signal CmdEnable: Std_logic;
|
|
signal un1_CMDWR: Std_logic;
|
|
signal CmdEnable_s: Std_logic;
|
|
signal XOR8MEG11: Std_logic;
|
|
signal Din_c_1: Std_logic;
|
|
signal CmdLEDEN: Std_logic;
|
|
signal XOR8MEG14: Std_logic;
|
|
signal N_75: Std_logic;
|
|
signal LEDEN: Std_logic;
|
|
signal CmdLEDEN_4: Std_logic;
|
|
signal XOR8MEG18: Std_logic;
|
|
signal CmdUFMShift: Std_logic;
|
|
signal CmdUFMShift_3: Std_logic;
|
|
signal CmdUFMShift_fast: Std_logic;
|
|
signal CmdUFMShift_3_fast: Std_logic;
|
|
signal Din_c_0: Std_logic;
|
|
signal CmdUFMWrite_2: Std_logic;
|
|
signal CmdUFMWrite: Std_logic;
|
|
signal CmdUFMWrite_3: Std_logic;
|
|
signal Din_c_7: Std_logic;
|
|
signal Din_c_6: Std_logic;
|
|
signal Din_c_5: Std_logic;
|
|
signal Din_c_4: Std_logic;
|
|
signal CmdValid_r: Std_logic;
|
|
signal CmdValid: Std_logic;
|
|
signal CMDWR_2: Std_logic;
|
|
signal N_36_fast: Std_logic;
|
|
signal CmdValid_fast: Std_logic;
|
|
signal Cmdn8MEGEN: Std_logic;
|
|
signal n8MEGEN: Std_logic;
|
|
signal N_93: Std_logic;
|
|
signal Cmdn8MEGEN_4: Std_logic;
|
|
signal nFWE_c: Std_logic;
|
|
signal nFWE_c_i: Std_logic;
|
|
signal nCRAS_c: Std_logic;
|
|
signal FWEr: Std_logic;
|
|
signal RD_1_i: Std_logic;
|
|
signal Ready: Std_logic;
|
|
signal N_250: Std_logic;
|
|
signal IS_0: Std_logic;
|
|
signal N_60_i_i: Std_logic;
|
|
signal RA10s_i: Std_logic;
|
|
signal IS_2: Std_logic;
|
|
signal IS_1: Std_logic;
|
|
signal N_57_i_i: Std_logic;
|
|
signal IS_n1_0_x2: Std_logic;
|
|
signal N_253_i: Std_logic;
|
|
signal N_58_i_i: Std_logic;
|
|
signal N_45: Std_logic;
|
|
signal N_116: Std_logic;
|
|
signal InitReady3_0_a3_2: Std_logic;
|
|
signal InitReady: Std_logic;
|
|
signal InitReady3: Std_logic;
|
|
signal N_487_0: Std_logic;
|
|
signal wb_dato_1: Std_logic;
|
|
signal LEDEN_6: Std_logic;
|
|
signal un1_FS_38_i: Std_logic;
|
|
signal CBR: Std_logic;
|
|
signal nCRAS_c_i_0: Std_logic;
|
|
signal RASr: Std_logic;
|
|
signal LED_c: Std_logic;
|
|
signal nRowColSel: Std_logic;
|
|
signal RowA_4: Std_logic;
|
|
signal MAin_c_4: Std_logic;
|
|
signal PHI2r: Std_logic;
|
|
signal RA_c_4: Std_logic;
|
|
signal RASr3: Std_logic;
|
|
signal un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1: Std_logic;
|
|
signal PHI2r2: Std_logic;
|
|
signal N_41: Std_logic;
|
|
signal RCKEEN_8_u_1_0: Std_logic;
|
|
signal RCKEEN_8_u_0_0: Std_logic;
|
|
signal RCKEEN_8: Std_logic;
|
|
signal RCKEEN: Std_logic;
|
|
signal Bank_7: Std_logic;
|
|
signal Bank_6: Std_logic;
|
|
signal Bank_5: Std_logic;
|
|
signal Bank_2: Std_logic;
|
|
signal RCKE_2: Std_logic;
|
|
signal RCKE_c: Std_logic;
|
|
signal un1_Bank_1_4: Std_logic;
|
|
signal N_258: Std_logic;
|
|
signal N_486_0: Std_logic;
|
|
signal Ready_fast: Std_logic;
|
|
signal Ready_0_sqmuxa: Std_logic;
|
|
signal N_489_0: Std_logic;
|
|
signal MAin_c_1: Std_logic;
|
|
signal MAin_c_0: Std_logic;
|
|
signal RowAd_0_1: Std_logic;
|
|
signal RowAd_0_0: Std_logic;
|
|
signal RowA_0: Std_logic;
|
|
signal RowA_1: Std_logic;
|
|
signal MAin_c_3: Std_logic;
|
|
signal MAin_c_2: Std_logic;
|
|
signal RowAd_0_3: Std_logic;
|
|
signal RowAd_0_2: Std_logic;
|
|
signal RowA_2: Std_logic;
|
|
signal RowA_3: Std_logic;
|
|
signal MAin_c_5: Std_logic;
|
|
signal RowAd_0_5: Std_logic;
|
|
signal RowAd_0_4: Std_logic;
|
|
signal RowA_5: Std_logic;
|
|
signal MAin_c_7: Std_logic;
|
|
signal MAin_c_6: Std_logic;
|
|
signal RowAd_0_7: Std_logic;
|
|
signal RowAd_0_6: Std_logic;
|
|
signal RowA_6: Std_logic;
|
|
signal RowA_7: Std_logic;
|
|
signal MAin_c_9: Std_logic;
|
|
signal MAin_c_8: Std_logic;
|
|
signal RowAd_0_9: Std_logic;
|
|
signal RowAd_0_8: Std_logic;
|
|
signal RowA_8: Std_logic;
|
|
signal RowA_9: Std_logic;
|
|
signal nRRAS_5_u_i_0: Std_logic;
|
|
signal XOR8MEG9_1: Std_logic;
|
|
signal un1_Din_2: Std_logic;
|
|
signal XOR8MEG_3_u_0_bm: Std_logic;
|
|
signal XOR8MEG: Std_logic;
|
|
signal XOR8MEG_3: Std_logic;
|
|
signal wb_dato_0: Std_logic;
|
|
signal n8MEGEN_6: Std_logic;
|
|
signal wb_rst10: Std_logic;
|
|
signal CASr3: Std_logic;
|
|
signal N_265: Std_logic;
|
|
signal nRowColSel_0_0: Std_logic;
|
|
signal nRRAS_0_sqmuxa: Std_logic;
|
|
signal wb_rst11: Std_logic;
|
|
signal wb_adr_0: Std_logic;
|
|
signal N_181: Std_logic;
|
|
signal wb_dati_7: Std_logic;
|
|
signal wb_adr_cnst_m2_0: Std_logic;
|
|
signal wb_adr_5_1: Std_logic;
|
|
signal wb_adr_5_0: Std_logic;
|
|
signal un1_wb_rst14_i: Std_logic;
|
|
signal wb_adr_1: Std_logic;
|
|
signal wb_adr_2: Std_logic;
|
|
signal wb_adr_5_3: Std_logic;
|
|
signal wb_adr_5_2: Std_logic;
|
|
signal wb_adr_3: Std_logic;
|
|
signal wb_adr_4: Std_logic;
|
|
signal wb_adr_5_5: Std_logic;
|
|
signal wb_adr_5_4: Std_logic;
|
|
signal wb_adr_5: Std_logic;
|
|
signal wb_adr_6: Std_logic;
|
|
signal wb_adr_5_7: Std_logic;
|
|
signal wb_adr_5_6: Std_logic;
|
|
signal wb_adr_7: Std_logic;
|
|
signal un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1: Std_logic;
|
|
signal N_245: Std_logic;
|
|
signal N_102_2: Std_logic;
|
|
signal un1_wb_cyc_stb_1_sqmuxa_0: Std_logic;
|
|
signal un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: Std_logic;
|
|
signal wb_cyc_stb: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_0_0_1: Std_logic;
|
|
signal wb_dati_5_1_iv_0_0_1: Std_logic;
|
|
signal N_128: Std_logic;
|
|
signal N_94: Std_logic;
|
|
signal wb_we: Std_logic;
|
|
signal wb_dati_5_0_iv_0_a3_1_0: Std_logic;
|
|
signal N_119: Std_logic;
|
|
signal wb_dati_5_1: Std_logic;
|
|
signal wb_dati_5_0: Std_logic;
|
|
signal wb_dati_0: Std_logic;
|
|
signal wb_dati_1: Std_logic;
|
|
signal un1_wb_we95_1: Std_logic;
|
|
signal wb_dati_5_1_iv_0_0_3: Std_logic;
|
|
signal N_240: Std_logic;
|
|
signal N_49: Std_logic;
|
|
signal wb_dati_5_3: Std_logic;
|
|
signal wb_dati_5_2: Std_logic;
|
|
signal wb_dati_2: Std_logic;
|
|
signal wb_dati_3: Std_logic;
|
|
signal wb_dati_4: Std_logic;
|
|
signal wb_dati_5_1_iv_0_1_4: Std_logic;
|
|
signal un1_wb_rst11_1_s6_1: Std_logic;
|
|
signal wb_dati_5_5: Std_logic;
|
|
signal wb_dati_5_4: Std_logic;
|
|
signal wb_dati_5: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_0_0_7: Std_logic;
|
|
signal wb_dati_5_1_iv_0_1_7: Std_logic;
|
|
signal N_89: Std_logic;
|
|
signal wb_dati_5_1_iv_0_1_6: Std_logic;
|
|
signal wb_dati_5_7: Std_logic;
|
|
signal wb_dati_5_6: Std_logic;
|
|
signal wb_dati_6: Std_logic;
|
|
signal wb_req: Std_logic;
|
|
signal un1_FS_37_i_0: Std_logic;
|
|
signal N_78_i: Std_logic;
|
|
signal wb_reqe_0: Std_logic;
|
|
signal PHI2r3: Std_logic;
|
|
signal wb_rst: Std_logic;
|
|
signal wb_rste_0: Std_logic;
|
|
signal wb_we95: Std_logic;
|
|
signal un1_FS_29: Std_logic;
|
|
signal un1_wb_adr_0_sqmuxa_3: Std_logic;
|
|
signal un1_wb_adr_0_sqmuxa_2: Std_logic;
|
|
signal CmdUFMData: Std_logic;
|
|
signal wb_we_0: Std_logic;
|
|
signal un1_PHI2r3_0: Std_logic;
|
|
signal N_102: Std_logic;
|
|
signal un1_FS_11: Std_logic;
|
|
signal wb_ack: Std_logic;
|
|
signal d_N_5_mux: Std_logic;
|
|
signal N_254: Std_logic;
|
|
signal N_39: Std_logic;
|
|
signal nRCAS_0_sqmuxa_1: Std_logic;
|
|
signal nRWE_0io_RNO_1: Std_logic;
|
|
signal N_37_i_1: Std_logic;
|
|
signal CBR_fast: Std_logic;
|
|
signal N_37_i: Std_logic;
|
|
signal un1_FS_40_1_0_1: Std_logic;
|
|
signal un1_FS_40_1_0: Std_logic;
|
|
signal nRCAS_0io_RNO_0: Std_logic;
|
|
signal N_28_i_1: Std_logic;
|
|
signal N_249_i: Std_logic;
|
|
signal N_230: Std_logic;
|
|
signal nRWE_0io_RNO_4: Std_logic;
|
|
signal nRWE_0io_RNO_3: Std_logic;
|
|
signal N_131: Std_logic;
|
|
signal N_85: Std_logic;
|
|
signal N_248: Std_logic;
|
|
signal XOR8MEG14_1: Std_logic;
|
|
signal Din_c_3: Std_logic;
|
|
signal CmdUFMData_1_sqmuxa: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_0_6: Std_logic;
|
|
signal N_246: Std_logic;
|
|
signal N_98: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_0_3: Std_logic;
|
|
signal N_25: Std_logic;
|
|
signal N_59: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_2_0_1: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_1_1_4: Std_logic;
|
|
signal wb_dati_5_1_iv_0_a3_3_0_7: Std_logic;
|
|
signal N_242: Std_logic;
|
|
signal N_91: Std_logic;
|
|
signal wb_we95_0_tz_tz_tz: Std_logic;
|
|
signal un1_FS_20_3: Std_logic;
|
|
signal N_120: Std_logic;
|
|
signal N_228: Std_logic;
|
|
signal wb_we113_i: Std_logic;
|
|
signal un1_FS_40_1_1_1: Std_logic;
|
|
signal un1_FS_40_1_1_tz: Std_logic;
|
|
signal N_139: Std_logic;
|
|
signal N_136: Std_logic;
|
|
signal N_28_i_sn: Std_logic;
|
|
signal N_25_i: Std_logic;
|
|
signal FWEr_fast: Std_logic;
|
|
signal N_28_i: Std_logic;
|
|
signal N_233: Std_logic;
|
|
signal N_102_1: Std_logic;
|
|
signal ADWR_5: Std_logic;
|
|
signal ADWR_4: Std_logic;
|
|
signal C1WR_0: Std_logic;
|
|
signal Bank_1: Std_logic;
|
|
signal Bank_0: Std_logic;
|
|
signal un1_Bank_1_3: Std_logic;
|
|
signal Bank_4: Std_logic;
|
|
signal Bank_3: Std_logic;
|
|
signal G_8_0_a3_0_0: Std_logic;
|
|
signal nRWE_0io_RNO_2: Std_logic;
|
|
signal Din_c_2: Std_logic;
|
|
signal RA_c_9: Std_logic;
|
|
signal RDQMH_c: Std_logic;
|
|
signal RA_c_7: Std_logic;
|
|
signal RA_c_0: Std_logic;
|
|
signal RDQML_c: Std_logic;
|
|
signal RA_c_1: Std_logic;
|
|
signal RA_c_8: Std_logic;
|
|
signal RA_c_2: Std_logic;
|
|
signal RA_c_6: Std_logic;
|
|
signal RA_c_3: Std_logic;
|
|
signal RA_c_5: Std_logic;
|
|
signal RA11d_0: Std_logic;
|
|
signal CROW_c_0: Std_logic;
|
|
signal CROW_c_1: Std_logic;
|
|
signal RBAd_0_1: Std_logic;
|
|
signal RBAd_0_0: Std_logic;
|
|
signal RD_in_0: Std_logic;
|
|
signal WRD_0: Std_logic;
|
|
signal nRCAS_c: Std_logic;
|
|
signal nRRAS_c: Std_logic;
|
|
signal nRWE_c: Std_logic;
|
|
signal nRCS_c: Std_logic;
|
|
signal RD_in_7: Std_logic;
|
|
signal WRD_7: Std_logic;
|
|
signal RD_in_6: Std_logic;
|
|
signal WRD_6: Std_logic;
|
|
signal RD_in_5: Std_logic;
|
|
signal WRD_5: Std_logic;
|
|
signal RD_in_4: Std_logic;
|
|
signal WRD_4: Std_logic;
|
|
signal RD_in_3: Std_logic;
|
|
signal WRD_3: Std_logic;
|
|
signal RD_in_2: Std_logic;
|
|
signal WRD_2: Std_logic;
|
|
signal RD_in_1: Std_logic;
|
|
signal WRD_1: Std_logic;
|
|
signal RA_c_11: Std_logic;
|
|
signal RA_c_10: Std_logic;
|
|
signal RBA_c_1: Std_logic;
|
|
signal RBA_c_0: Std_logic;
|
|
signal VCCI: Std_logic;
|
|
component SLICE_0
|
|
port (A1: in Std_logic; DI1: in Std_logic; CLK: in Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_1
|
|
port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_2
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_3
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_4
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_5
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_6
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_7
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_8
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_9
|
|
port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic; FCO: out Std_logic);
|
|
end component;
|
|
component SLICE_10
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_11
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_12
|
|
port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_16
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_17
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
OFX0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_18
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_20
|
|
port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_21
|
|
port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_22
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_23
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_24
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_25
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_26
|
|
port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_28
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_29
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_30
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_31
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_32
|
|
port (C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic);
|
|
end component;
|
|
component SLICE_34
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_35
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M1: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_36
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_37
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_38
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_39
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_40
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_41
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_42
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_43
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_44
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_45
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_46
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_47
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_48
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_49
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_50
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_51
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_52
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_53
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_54
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_55
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_56
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic;
|
|
Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_57
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_58
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_59
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_60
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
DI0: in Std_logic; CE: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component wb_cyc_stb_RNO_SLICE_61
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic);
|
|
end component;
|
|
component SLICE_62
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_63
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_64
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_65
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_66
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_67
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_68
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_69
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_70
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_71
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_72
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_73
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; M0: in Std_logic;
|
|
CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_74
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_75
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_76
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_77
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_78
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_79
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_80
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_81
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_82
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_83
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_84
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_85
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_86
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_87
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_88
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_89
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_90
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_91
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_92
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_93
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_94
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_95
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_96
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_97
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_98
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_99
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_100
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_101
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_102
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_103
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_104
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; D0: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_105
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M1: in Std_logic; M0: in Std_logic;
|
|
CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic;
|
|
F1: out Std_logic; Q1: out Std_logic);
|
|
end component;
|
|
component SLICE_106
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_107
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_108
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic;
|
|
Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_109
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_110
|
|
port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_111
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_112
|
|
port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic;
|
|
B0: in Std_logic; A0: in Std_logic; F0: out Std_logic;
|
|
F1: out Std_logic);
|
|
end component;
|
|
component SLICE_113
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_114
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_115
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
C0: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_116
|
|
port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic;
|
|
A1: in Std_logic; B0: in Std_logic; A0: in Std_logic;
|
|
F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_117
|
|
port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic;
|
|
D0: in Std_logic; C0: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; F0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component SLICE_118
|
|
port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic;
|
|
A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic;
|
|
F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic);
|
|
end component;
|
|
component RD_0_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD0: inout Std_logic);
|
|
end component;
|
|
component RD_0_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component Dout_0_B
|
|
port (PADDO: in Std_logic; Dout0: out Std_logic);
|
|
end component;
|
|
component PHI2B
|
|
port (PADDI: out Std_logic; PHI2S: in Std_logic);
|
|
end component;
|
|
component PHI2_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component RDQMLB
|
|
port (PADDO: in Std_logic; RDQMLS: out Std_logic);
|
|
end component;
|
|
component RDQMHB
|
|
port (PADDO: in Std_logic; RDQMHS: out Std_logic);
|
|
end component;
|
|
component nRCASB
|
|
port (IOLDO: in Std_logic; nRCASS: out Std_logic);
|
|
end component;
|
|
component nRCAS_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component nRRASB
|
|
port (IOLDO: in Std_logic; nRRASS: out Std_logic);
|
|
end component;
|
|
component nRRAS_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component nRWEB
|
|
port (IOLDO: in Std_logic; nRWES: out Std_logic);
|
|
end component;
|
|
component nRWE_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RCKEB
|
|
port (PADDO: in Std_logic; RCKES: out Std_logic);
|
|
end component;
|
|
component RCLKB
|
|
port (PADDI: out Std_logic; RCLKS: in Std_logic);
|
|
end component;
|
|
component nRCSB
|
|
port (IOLDO: in Std_logic; nRCSS: out Std_logic);
|
|
end component;
|
|
component nRCS_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_7_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD7: inout Std_logic);
|
|
end component;
|
|
component RD_7_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_6_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD6: inout Std_logic);
|
|
end component;
|
|
component RD_6_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_5_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD5: inout Std_logic);
|
|
end component;
|
|
component RD_5_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_4_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD4: inout Std_logic);
|
|
end component;
|
|
component RD_4_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_3_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD3: inout Std_logic);
|
|
end component;
|
|
component RD_3_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_2_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD2: inout Std_logic);
|
|
end component;
|
|
component RD_2_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RD_1_B
|
|
port (PADDI: out Std_logic; IOLDO: in Std_logic; PADDT: in Std_logic;
|
|
RD1: inout Std_logic);
|
|
end component;
|
|
component RD_1_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RA_11_B
|
|
port (IOLDO: in Std_logic; RA11: out Std_logic);
|
|
end component;
|
|
component RA_11_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RA_10_B
|
|
port (IOLDO: in Std_logic; RA10: out Std_logic);
|
|
end component;
|
|
component RA_10_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; LSR: in Std_logic;
|
|
CLK: in Std_logic);
|
|
end component;
|
|
component RA_9_B
|
|
port (PADDO: in Std_logic; RA9: out Std_logic);
|
|
end component;
|
|
component RA_8_B
|
|
port (PADDO: in Std_logic; RA8: out Std_logic);
|
|
end component;
|
|
component RA_7_B
|
|
port (PADDO: in Std_logic; RA7: out Std_logic);
|
|
end component;
|
|
component RA_6_B
|
|
port (PADDO: in Std_logic; RA6: out Std_logic);
|
|
end component;
|
|
component RA_5_B
|
|
port (PADDO: in Std_logic; RA5: out Std_logic);
|
|
end component;
|
|
component RA_4_B
|
|
port (PADDO: in Std_logic; RA4: out Std_logic);
|
|
end component;
|
|
component RA_3_B
|
|
port (PADDO: in Std_logic; RA3: out Std_logic);
|
|
end component;
|
|
component RA_2_B
|
|
port (PADDO: in Std_logic; RA2: out Std_logic);
|
|
end component;
|
|
component RA_1_B
|
|
port (PADDO: in Std_logic; RA1: out Std_logic);
|
|
end component;
|
|
component RA_0_B
|
|
port (PADDO: in Std_logic; RA0: out Std_logic);
|
|
end component;
|
|
component RBA_1_B
|
|
port (IOLDO: in Std_logic; RBA1: out Std_logic);
|
|
end component;
|
|
component RBA_1_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component RBA_0_B
|
|
port (IOLDO: in Std_logic; RBA0: out Std_logic);
|
|
end component;
|
|
component RBA_0_MGIOL
|
|
port (IOLDO: out Std_logic; OPOS: in Std_logic; CLK: in Std_logic);
|
|
end component;
|
|
component LEDB
|
|
port (PADDO: in Std_logic; LEDS: out Std_logic);
|
|
end component;
|
|
component nFWEB
|
|
port (PADDI: out Std_logic; nFWES: in Std_logic);
|
|
end component;
|
|
component nCRASB
|
|
port (PADDI: out Std_logic; nCRASS: in Std_logic);
|
|
end component;
|
|
component nCCASB
|
|
port (PADDI: out Std_logic; nCCASS: in Std_logic);
|
|
end component;
|
|
component Dout_7_B
|
|
port (PADDO: in Std_logic; Dout7: out Std_logic);
|
|
end component;
|
|
component Dout_6_B
|
|
port (PADDO: in Std_logic; Dout6: out Std_logic);
|
|
end component;
|
|
component Dout_5_B
|
|
port (PADDO: in Std_logic; Dout5: out Std_logic);
|
|
end component;
|
|
component Dout_4_B
|
|
port (PADDO: in Std_logic; Dout4: out Std_logic);
|
|
end component;
|
|
component Dout_3_B
|
|
port (PADDO: in Std_logic; Dout3: out Std_logic);
|
|
end component;
|
|
component Dout_2_B
|
|
port (PADDO: in Std_logic; Dout2: out Std_logic);
|
|
end component;
|
|
component Dout_1_B
|
|
port (PADDO: in Std_logic; Dout1: out Std_logic);
|
|
end component;
|
|
component Din_7_B
|
|
port (PADDI: out Std_logic; Din7: in Std_logic);
|
|
end component;
|
|
component Din_7_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_6_B
|
|
port (PADDI: out Std_logic; Din6: in Std_logic);
|
|
end component;
|
|
component Din_6_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_5_B
|
|
port (PADDI: out Std_logic; Din5: in Std_logic);
|
|
end component;
|
|
component Din_5_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_4_B
|
|
port (PADDI: out Std_logic; Din4: in Std_logic);
|
|
end component;
|
|
component Din_4_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_3_B
|
|
port (PADDI: out Std_logic; Din3: in Std_logic);
|
|
end component;
|
|
component Din_3_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_2_B
|
|
port (PADDI: out Std_logic; Din2: in Std_logic);
|
|
end component;
|
|
component Din_2_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_1_B
|
|
port (PADDI: out Std_logic; Din1: in Std_logic);
|
|
end component;
|
|
component Din_1_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component Din_0_B
|
|
port (PADDI: out Std_logic; Din0: in Std_logic);
|
|
end component;
|
|
component Din_0_MGIOL
|
|
port (DI: in Std_logic; CLK: in Std_logic; INP: out Std_logic);
|
|
end component;
|
|
component CROW_1_B
|
|
port (PADDI: out Std_logic; CROW1: in Std_logic);
|
|
end component;
|
|
component CROW_0_B
|
|
port (PADDI: out Std_logic; CROW0: in Std_logic);
|
|
end component;
|
|
component MAin_9_B
|
|
port (PADDI: out Std_logic; MAin9: in Std_logic);
|
|
end component;
|
|
component MAin_8_B
|
|
port (PADDI: out Std_logic; MAin8: in Std_logic);
|
|
end component;
|
|
component MAin_7_B
|
|
port (PADDI: out Std_logic; MAin7: in Std_logic);
|
|
end component;
|
|
component MAin_6_B
|
|
port (PADDI: out Std_logic; MAin6: in Std_logic);
|
|
end component;
|
|
component MAin_5_B
|
|
port (PADDI: out Std_logic; MAin5: in Std_logic);
|
|
end component;
|
|
component MAin_4_B
|
|
port (PADDI: out Std_logic; MAin4: in Std_logic);
|
|
end component;
|
|
component MAin_3_B
|
|
port (PADDI: out Std_logic; MAin3: in Std_logic);
|
|
end component;
|
|
component MAin_2_B
|
|
port (PADDI: out Std_logic; MAin2: in Std_logic);
|
|
end component;
|
|
component MAin_1_B
|
|
port (PADDI: out Std_logic; MAin1: in Std_logic);
|
|
end component;
|
|
component MAin_0_B
|
|
port (PADDI: out Std_logic; MAin0: in Std_logic);
|
|
end component;
|
|
component ufmefb_EFBInst_0
|
|
port (WBCLKI: in Std_logic; WBRSTI: in Std_logic; WBCYCI: in Std_logic;
|
|
WBSTBI: in Std_logic; WBWEI: in Std_logic; WBADRI0: in Std_logic;
|
|
WBADRI1: in Std_logic; WBADRI2: in Std_logic;
|
|
WBADRI3: in Std_logic; WBADRI4: in Std_logic;
|
|
WBADRI5: in Std_logic; WBADRI6: in Std_logic;
|
|
WBADRI7: in Std_logic; WBDATI0: in Std_logic;
|
|
WBDATI1: in Std_logic; WBDATI2: in Std_logic;
|
|
WBDATI3: in Std_logic; WBDATI4: in Std_logic;
|
|
WBDATI5: in Std_logic; WBDATI6: in Std_logic;
|
|
WBDATI7: in Std_logic; WBDATO0: out Std_logic;
|
|
WBDATO1: out Std_logic; WBACKO: out Std_logic);
|
|
end component;
|
|
begin
|
|
SLICE_0I: SLICE_0
|
|
port map (A1=>FS_0, DI1=>FS_s_0, CLK=>RCLK_c, F1=>FS_s_0, Q1=>FS_0,
|
|
FCO=>FS_cry_0);
|
|
SLICE_1I: SLICE_1
|
|
port map (A0=>FS_17, DI0=>FS_s_17, CLK=>RCLK_c, FCI=>FS_cry_16,
|
|
F0=>FS_s_17, Q0=>FS_17);
|
|
SLICE_2I: SLICE_2
|
|
port map (A1=>FS_16, A0=>FS_15, DI1=>FS_s_16, DI0=>FS_s_15, CLK=>RCLK_c,
|
|
FCI=>FS_cry_14, F0=>FS_s_15, Q0=>FS_15, F1=>FS_s_16, Q1=>FS_16,
|
|
FCO=>FS_cry_16);
|
|
SLICE_3I: SLICE_3
|
|
port map (A1=>FS_14, A0=>FS_13, DI1=>FS_s_14, DI0=>FS_s_13, CLK=>RCLK_c,
|
|
FCI=>FS_cry_12, F0=>FS_s_13, Q0=>FS_13, F1=>FS_s_14, Q1=>FS_14,
|
|
FCO=>FS_cry_14);
|
|
SLICE_4I: SLICE_4
|
|
port map (A1=>FS_12, A0=>FS_11, DI1=>FS_s_12, DI0=>FS_s_11, CLK=>RCLK_c,
|
|
FCI=>FS_cry_10, F0=>FS_s_11, Q0=>FS_11, F1=>FS_s_12, Q1=>FS_12,
|
|
FCO=>FS_cry_12);
|
|
SLICE_5I: SLICE_5
|
|
port map (A1=>FS_10, A0=>FS_9, DI1=>FS_s_10, DI0=>FS_s_9, CLK=>RCLK_c,
|
|
FCI=>FS_cry_8, F0=>FS_s_9, Q0=>FS_9, F1=>FS_s_10, Q1=>FS_10,
|
|
FCO=>FS_cry_10);
|
|
SLICE_6I: SLICE_6
|
|
port map (A1=>FS_8, A0=>FS_7, DI1=>FS_s_8, DI0=>FS_s_7, CLK=>RCLK_c,
|
|
FCI=>FS_cry_6, F0=>FS_s_7, Q0=>FS_7, F1=>FS_s_8, Q1=>FS_8,
|
|
FCO=>FS_cry_8);
|
|
SLICE_7I: SLICE_7
|
|
port map (A1=>FS_6, A0=>FS_5, DI1=>FS_s_6, DI0=>FS_s_5, CLK=>RCLK_c,
|
|
FCI=>FS_cry_4, F0=>FS_s_5, Q0=>FS_5, F1=>FS_s_6, Q1=>FS_6,
|
|
FCO=>FS_cry_6);
|
|
SLICE_8I: SLICE_8
|
|
port map (A1=>FS_4, A0=>FS_3, DI1=>FS_s_4, DI0=>FS_s_3, CLK=>RCLK_c,
|
|
FCI=>FS_cry_2, F0=>FS_s_3, Q0=>FS_3, F1=>FS_s_4, Q1=>FS_4,
|
|
FCO=>FS_cry_4);
|
|
SLICE_9I: SLICE_9
|
|
port map (A1=>FS_2, A0=>FS_1, DI1=>FS_s_2, DI0=>FS_s_1, CLK=>RCLK_c,
|
|
FCI=>FS_cry_0, F0=>FS_s_1, Q0=>FS_1, F1=>FS_s_2, Q1=>FS_2,
|
|
FCO=>FS_cry_2);
|
|
SLICE_10I: SLICE_10
|
|
port map (D1=>N_304, C1=>CmdEnable17_5, B1=>CmdEnable17_4, A1=>ADWR_7,
|
|
D0=>CmdEnable16, C0=>CmdEnable17, B0=>un1_ADWR,
|
|
A0=>ADSubmitted, DI0=>ADSubmitted_r, CLK=>PHI2_c,
|
|
F0=>ADSubmitted_r, Q0=>ADSubmitted, F1=>CmdEnable17);
|
|
SLICE_11I: SLICE_11
|
|
port map (D1=>CmdEnable16_5, C1=>CmdEnable16_4, B1=>C1WR_7, A1=>C1WR_2,
|
|
C0=>CmdEnable16, B0=>un1_ADWR, A0=>C1Submitted,
|
|
DI0=>C1Submitted_s, CLK=>PHI2_c, F0=>C1Submitted_s,
|
|
Q0=>C1Submitted, F1=>CmdEnable16);
|
|
SLICE_12I: SLICE_12
|
|
port map (A0=>nCCAS_c, DI0=>nCCAS_c_i, M1=>CASr, CLK=>RCLK_c,
|
|
F0=>nCCAS_c_i, Q0=>CASr, Q1=>CASr2);
|
|
SLICE_16I: SLICE_16
|
|
port map (D1=>S_1, C1=>RASr2, B1=>IS_3, A1=>CO0, B0=>S_1, A0=>CO0,
|
|
DI0=>N_79_i, LSR=>RASr2, CLK=>RCLK_c, F0=>N_79_i, Q0=>CO0,
|
|
F1=>Ready_0_sqmuxa_0_a3_2);
|
|
SLICE_17I: SLICE_17
|
|
port map (B1=>ADSubmitted, A1=>CmdEnable, D0=>C1Submitted, C0=>un1_CMDWR,
|
|
B0=>CmdEnable, A0=>CmdEnable17, DI0=>CmdEnable_s,
|
|
M0=>CmdEnable16, CLK=>PHI2_c, OFX0=>CmdEnable_s, Q0=>CmdEnable);
|
|
SLICE_18I: SLICE_18
|
|
port map (C1=>XOR8MEG11, B1=>Din_c_1, A1=>CmdLEDEN, C0=>XOR8MEG14,
|
|
B0=>N_75, A0=>LEDEN, DI0=>CmdLEDEN_4, CE=>XOR8MEG18,
|
|
CLK=>PHI2_c, F0=>CmdLEDEN_4, Q0=>CmdLEDEN, F1=>N_75);
|
|
SLICE_20I: SLICE_20
|
|
port map (D0=>XOR8MEG14, C0=>XOR8MEG11, B0=>Din_c_1, A0=>CmdUFMShift,
|
|
DI0=>CmdUFMShift_3, CE=>XOR8MEG18, CLK=>PHI2_c,
|
|
F0=>CmdUFMShift_3, Q0=>CmdUFMShift);
|
|
SLICE_21I: SLICE_21
|
|
port map (D0=>XOR8MEG14, C0=>XOR8MEG11, B0=>Din_c_1,
|
|
A0=>CmdUFMShift_fast, DI0=>CmdUFMShift_3_fast, CE=>XOR8MEG18,
|
|
CLK=>PHI2_c, F0=>CmdUFMShift_3_fast, Q0=>CmdUFMShift_fast);
|
|
SLICE_22I: SLICE_22
|
|
port map (B1=>Din_c_1, A1=>Din_c_0, D0=>XOR8MEG14, C0=>XOR8MEG11,
|
|
B0=>CmdUFMWrite_2, A0=>CmdUFMWrite, DI0=>CmdUFMWrite_3,
|
|
CE=>XOR8MEG18, CLK=>PHI2_c, F0=>CmdUFMWrite_3, Q0=>CmdUFMWrite,
|
|
F1=>CmdUFMWrite_2);
|
|
SLICE_23I: SLICE_23
|
|
port map (D1=>Din_c_7, C1=>Din_c_6, B1=>Din_c_5, A1=>Din_c_4,
|
|
C0=>XOR8MEG14, B0=>XOR8MEG11, A0=>XOR8MEG18, DI0=>CmdValid_r,
|
|
CLK=>PHI2_c, F0=>CmdValid_r, Q0=>CmdValid, F1=>XOR8MEG11);
|
|
SLICE_24I: SLICE_24
|
|
port map (C1=>CmdEnable, B1=>CMDWR_2, A1=>C1WR_7, C0=>XOR8MEG14,
|
|
B0=>XOR8MEG11, A0=>XOR8MEG18, DI0=>N_36_fast, CLK=>PHI2_c,
|
|
F0=>N_36_fast, Q0=>CmdValid_fast, F1=>XOR8MEG18);
|
|
SLICE_25I: SLICE_25
|
|
port map (C1=>XOR8MEG11, B1=>Din_c_0, A1=>Cmdn8MEGEN, C0=>n8MEGEN,
|
|
B0=>XOR8MEG14, A0=>N_93, DI0=>Cmdn8MEGEN_4, CE=>XOR8MEG18,
|
|
CLK=>PHI2_c, F0=>Cmdn8MEGEN_4, Q0=>Cmdn8MEGEN, F1=>N_93);
|
|
SLICE_26I: SLICE_26
|
|
port map (B1=>nFWE_c, A1=>nCCAS_c, A0=>nFWE_c, DI0=>nFWE_c_i,
|
|
CLK=>nCRAS_c, F0=>nFWE_c_i, Q0=>FWEr, F1=>RD_1_i);
|
|
SLICE_28I: SLICE_28
|
|
port map (D1=>Ready, C1=>N_250, B1=>IS_3, A1=>IS_0, C0=>Ready, B0=>N_250,
|
|
A0=>IS_0, DI0=>N_60_i_i, CLK=>RCLK_c, F0=>N_60_i_i, Q0=>IS_0,
|
|
F1=>RA10s_i);
|
|
SLICE_29I: SLICE_29
|
|
port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, B0=>IS_1, A0=>IS_0,
|
|
DI1=>N_57_i_i, DI0=>IS_n1_0_x2, CE=>N_253_i, CLK=>RCLK_c,
|
|
F0=>IS_n1_0_x2, Q0=>IS_1, F1=>N_57_i_i, Q1=>IS_2);
|
|
SLICE_30I: SLICE_30
|
|
port map (B1=>IS_2, A1=>IS_1, D0=>IS_0, C0=>IS_1, B0=>IS_2, A0=>IS_3,
|
|
DI0=>N_58_i_i, CE=>N_253_i, CLK=>RCLK_c, F0=>N_58_i_i,
|
|
Q0=>IS_3, F1=>N_45);
|
|
SLICE_31I: SLICE_31
|
|
port map (D1=>N_116, C1=>InitReady3_0_a3_2, B1=>FS_14, A1=>FS_13,
|
|
B0=>InitReady, A0=>InitReady3, DI0=>N_487_0, CLK=>RCLK_c,
|
|
F0=>N_487_0, Q0=>InitReady, F1=>InitReady3);
|
|
SLICE_32I: SLICE_32
|
|
port map (C0=>wb_dato_1, B0=>InitReady, A0=>CmdLEDEN, DI0=>LEDEN_6,
|
|
CE=>un1_FS_38_i, CLK=>RCLK_c, F0=>LEDEN_6, Q0=>LEDEN);
|
|
SLICE_34I: SLICE_34
|
|
port map (C1=>nCRAS_c, B1=>LEDEN, A1=>CBR, A0=>nCRAS_c, DI0=>nCRAS_c_i_0,
|
|
M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_i_0, Q0=>RASr, F1=>LED_c,
|
|
Q1=>RASr2);
|
|
SLICE_35I: SLICE_35
|
|
port map (B1=>FS_7, A1=>FS_3, C0=>nRowColSel, B0=>RowA_4, A0=>MAin_c_4,
|
|
M1=>PHI2r, M0=>RASr2, CLK=>RCLK_c, F0=>RA_c_4, Q0=>RASr3,
|
|
F1=>un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, Q1=>PHI2r2);
|
|
SLICE_36I: SLICE_36
|
|
port map (D1=>N_41, C1=>InitReady, B1=>RASr2, A1=>Ready, D0=>Ready,
|
|
C0=>RCKEEN_8_u_1_0, B0=>RCKEEN_8_u_0_0, A0=>CBR, DI0=>RCKEEN_8,
|
|
CLK=>RCLK_c, F0=>RCKEEN_8, Q0=>RCKEEN, F1=>RCKEEN_8_u_0_0);
|
|
SLICE_37I: SLICE_37
|
|
port map (D1=>Bank_7, C1=>Bank_6, B1=>Bank_5, A1=>Bank_2, D0=>RCKEEN,
|
|
C0=>RASr3, B0=>RASr2, A0=>RASr, DI0=>RCKE_2, CLK=>RCLK_c,
|
|
F0=>RCKE_2, Q0=>RCKE_c, F1=>un1_Bank_1_4);
|
|
SLICE_38I: SLICE_38
|
|
port map (C1=>IS_2, B1=>IS_1, A1=>IS_0, D0=>InitReady, C0=>N_258,
|
|
B0=>Ready_0_sqmuxa_0_a3_2, A0=>Ready, DI0=>N_486_0,
|
|
CLK=>RCLK_c, F0=>N_486_0, Q0=>Ready, F1=>N_258);
|
|
SLICE_39I: SLICE_39
|
|
port map (D1=>Ready_0_sqmuxa_0_a3_2, C1=>Ready, B1=>N_258, A1=>InitReady,
|
|
B0=>Ready_fast, A0=>Ready_0_sqmuxa, DI0=>N_489_0, CLK=>RCLK_c,
|
|
F0=>N_489_0, Q0=>Ready_fast, F1=>Ready_0_sqmuxa);
|
|
SLICE_40I: SLICE_40
|
|
port map (B1=>Ready_fast, A1=>MAin_c_1, B0=>Ready_fast, A0=>MAin_c_0,
|
|
DI1=>RowAd_0_1, DI0=>RowAd_0_0, CLK=>nCRAS_c, F0=>RowAd_0_0,
|
|
Q0=>RowA_0, F1=>RowAd_0_1, Q1=>RowA_1);
|
|
SLICE_41I: SLICE_41
|
|
port map (B1=>Ready_fast, A1=>MAin_c_3, B0=>Ready_fast, A0=>MAin_c_2,
|
|
DI1=>RowAd_0_3, DI0=>RowAd_0_2, CLK=>nCRAS_c, F0=>RowAd_0_2,
|
|
Q0=>RowA_2, F1=>RowAd_0_3, Q1=>RowA_3);
|
|
SLICE_42I: SLICE_42
|
|
port map (B1=>Ready_fast, A1=>MAin_c_5, B0=>Ready_fast, A0=>MAin_c_4,
|
|
DI1=>RowAd_0_5, DI0=>RowAd_0_4, CLK=>nCRAS_c, F0=>RowAd_0_4,
|
|
Q0=>RowA_4, F1=>RowAd_0_5, Q1=>RowA_5);
|
|
SLICE_43I: SLICE_43
|
|
port map (B1=>Ready_fast, A1=>MAin_c_7, B0=>Ready_fast, A0=>MAin_c_6,
|
|
DI1=>RowAd_0_7, DI0=>RowAd_0_6, CLK=>nCRAS_c, F0=>RowAd_0_6,
|
|
Q0=>RowA_6, F1=>RowAd_0_7, Q1=>RowA_7);
|
|
SLICE_44I: SLICE_44
|
|
port map (B1=>Ready_fast, A1=>MAin_c_9, B0=>Ready_fast, A0=>MAin_c_8,
|
|
DI1=>RowAd_0_9, DI0=>RowAd_0_8, CLK=>nCRAS_c, F0=>RowAd_0_8,
|
|
Q0=>RowA_8, F1=>RowAd_0_9, Q1=>RowA_9);
|
|
SLICE_45I: SLICE_45
|
|
port map (D1=>Ready, C1=>RCKE_c, B1=>RASr2, A1=>N_41, B0=>S_1, A0=>CO0,
|
|
DI0=>N_41, LSR=>RASr2, CLK=>RCLK_c, F0=>N_41, Q0=>S_1,
|
|
F1=>nRRAS_5_u_i_0);
|
|
SLICE_46I: SLICE_46
|
|
port map (D1=>Din_c_1, C1=>Din_c_0, B1=>XOR8MEG9_1, A1=>LEDEN,
|
|
C0=>un1_Din_2, B0=>XOR8MEG_3_u_0_bm, A0=>XOR8MEG,
|
|
DI0=>XOR8MEG_3, CE=>XOR8MEG18, CLK=>PHI2_c, F0=>XOR8MEG_3,
|
|
Q0=>XOR8MEG, F1=>XOR8MEG_3_u_0_bm);
|
|
SLICE_47I: SLICE_47
|
|
port map (D1=>InitReady, C1=>FS_17, B1=>FS_16, A1=>FS_15, C0=>wb_dato_0,
|
|
B0=>InitReady, A0=>Cmdn8MEGEN, DI0=>n8MEGEN_6, CE=>un1_FS_38_i,
|
|
CLK=>RCLK_c, F0=>n8MEGEN_6, Q0=>n8MEGEN, F1=>wb_rst10);
|
|
SLICE_48I: SLICE_48
|
|
port map (D1=>Ready, C1=>FWEr, B1=>CBR, A1=>CASr3, D0=>S_1, C0=>Ready,
|
|
B0=>N_265, A0=>CO0, DI0=>nRowColSel_0_0, LSR=>nRRAS_0_sqmuxa,
|
|
CLK=>RCLK_c, F0=>nRowColSel_0_0, Q0=>nRowColSel, F1=>N_265);
|
|
SLICE_49I: SLICE_49
|
|
port map (D1=>wb_rst11, C1=>wb_adr_0, B1=>N_181, A1=>InitReady,
|
|
C0=>wb_dati_7, B0=>wb_adr_cnst_m2_0, A0=>InitReady,
|
|
DI1=>wb_adr_5_1, DI0=>wb_adr_5_0, CE=>un1_wb_rst14_i,
|
|
CLK=>RCLK_c, F0=>wb_adr_5_0, Q0=>wb_adr_0, F1=>wb_adr_5_1,
|
|
Q1=>wb_adr_1);
|
|
SLICE_50I: SLICE_50
|
|
port map (B1=>wb_adr_2, A1=>InitReady, B0=>wb_adr_1, A0=>InitReady,
|
|
DI1=>wb_adr_5_3, DI0=>wb_adr_5_2, CE=>un1_wb_rst14_i,
|
|
CLK=>RCLK_c, F0=>wb_adr_5_2, Q0=>wb_adr_2, F1=>wb_adr_5_3,
|
|
Q1=>wb_adr_3);
|
|
SLICE_51I: SLICE_51
|
|
port map (C1=>wb_rst11, B1=>wb_adr_4, A1=>InitReady, C0=>wb_rst11,
|
|
B0=>wb_adr_3, A0=>InitReady, DI1=>wb_adr_5_5, DI0=>wb_adr_5_4,
|
|
CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_adr_5_4, Q0=>wb_adr_4,
|
|
F1=>wb_adr_5_5, Q1=>wb_adr_5);
|
|
SLICE_52I: SLICE_52
|
|
port map (B1=>wb_adr_6, A1=>InitReady, C0=>wb_rst11, B0=>wb_adr_5,
|
|
A0=>InitReady, DI1=>wb_adr_5_7, DI0=>wb_adr_5_6,
|
|
CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_adr_5_6, Q0=>wb_adr_6,
|
|
F1=>wb_adr_5_7, Q1=>wb_adr_7);
|
|
SLICE_53I: SLICE_53
|
|
port map (D1=>un1_wb_cyc_stb_2_sqmuxa_i_a3_2_1, C1=>FS_5, B1=>FS_4,
|
|
A1=>FS_2, D0=>wb_rst11, C0=>un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1,
|
|
B0=>N_245, A0=>N_102_2, DI0=>un1_wb_cyc_stb_1_sqmuxa_0,
|
|
CE=>un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i, LSR=>wb_rst10,
|
|
CLK=>RCLK_c, F0=>un1_wb_cyc_stb_1_sqmuxa_0, Q0=>wb_cyc_stb,
|
|
F1=>N_102_2);
|
|
SLICE_54I: SLICE_54
|
|
port map (D1=>wb_dati_5_1_iv_0_a3_0_0_1, C1=>wb_dati_5_1_iv_0_0_1,
|
|
B1=>N_128, A1=>N_94, D0=>wb_we, C0=>wb_dati_5_0_iv_0_a3_1_0,
|
|
B0=>N_119, A0=>InitReady, DI1=>wb_dati_5_1, DI0=>wb_dati_5_0,
|
|
CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_dati_5_0,
|
|
Q0=>wb_dati_0, F1=>wb_dati_5_1, Q1=>wb_dati_1);
|
|
SLICE_55I: SLICE_55
|
|
port map (D1=>N_94, C1=>wb_rst11, B1=>un1_wb_we95_1,
|
|
A1=>wb_dati_5_1_iv_0_0_3, D0=>wb_dati_1, C0=>N_240, B0=>N_49,
|
|
A0=>InitReady, DI1=>wb_dati_5_3, DI0=>wb_dati_5_2,
|
|
CE=>un1_wb_rst14_i, CLK=>RCLK_c, F0=>wb_dati_5_2,
|
|
Q0=>wb_dati_2, F1=>wb_dati_5_3, Q1=>wb_dati_3);
|
|
SLICE_56I: SLICE_56
|
|
port map (D1=>wb_dati_4, C1=>N_240, B1=>N_49, A1=>InitReady,
|
|
D0=>wb_dati_5_1_iv_0_1_4, C0=>wb_dati_3,
|
|
B0=>un1_wb_rst11_1_s6_1, A0=>InitReady, DI1=>wb_dati_5_5,
|
|
DI0=>wb_dati_5_4, CE=>un1_wb_rst14_i, CLK=>RCLK_c,
|
|
F0=>wb_dati_5_4, Q0=>wb_dati_4, F1=>wb_dati_5_5, Q1=>wb_dati_5);
|
|
SLICE_57I: SLICE_57
|
|
port map (D1=>wb_dati_5_1_iv_0_a3_0_0_7, C1=>wb_dati_5_1_iv_0_1_7,
|
|
B1=>N_119, A1=>N_89, C0=>wb_dati_5_1_iv_0_a3_0_0_1,
|
|
B0=>wb_dati_5_1_iv_0_1_6, A0=>N_128, DI1=>wb_dati_5_7,
|
|
DI0=>wb_dati_5_6, CE=>un1_wb_rst14_i, CLK=>RCLK_c,
|
|
F0=>wb_dati_5_6, Q0=>wb_dati_6, F1=>wb_dati_5_7, Q1=>wb_dati_7);
|
|
SLICE_58I: SLICE_58
|
|
port map (C1=>FS_14, B1=>FS_13, A1=>FS_12, D0=>wb_rst11, C0=>wb_req,
|
|
B0=>un1_FS_37_i_0, A0=>N_78_i, DI0=>wb_reqe_0, LSR=>wb_rst10,
|
|
CLK=>RCLK_c, F0=>wb_reqe_0, Q0=>wb_req, F1=>un1_FS_37_i_0);
|
|
SLICE_59I: SLICE_59
|
|
port map (D1=>PHI2r3, C1=>PHI2r2, B1=>InitReady, A1=>CmdValid,
|
|
D0=>wb_rst10, C0=>wb_rst, B0=>N_78_i, A0=>FS_14,
|
|
DI0=>wb_rste_0, CLK=>RCLK_c, F0=>wb_rste_0, Q0=>wb_rst,
|
|
F1=>N_78_i);
|
|
SLICE_60I: SLICE_60
|
|
port map (B1=>wb_we95, A1=>un1_FS_29, D0=>un1_wb_adr_0_sqmuxa_3,
|
|
C0=>un1_wb_adr_0_sqmuxa_2, B0=>InitReady, A0=>CmdUFMData,
|
|
DI0=>wb_we_0, CE=>un1_wb_rst14_i, LSR=>wb_rst10, CLK=>RCLK_c,
|
|
F0=>wb_we_0, Q0=>wb_we, F1=>un1_wb_adr_0_sqmuxa_2);
|
|
wb_cyc_stb_RNO_SLICE_61I: wb_cyc_stb_RNO_SLICE_61
|
|
port map (D1=>CmdUFMWrite, C1=>un1_PHI2r3_0, B1=>CmdUFMShift,
|
|
A1=>CmdValid, C0=>N_102, B0=>un1_FS_11, A0=>wb_ack,
|
|
M0=>InitReady, OFX0=>un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i);
|
|
SLICE_62I: SLICE_62
|
|
port map (D1=>un1_PHI2r3_0, C1=>d_N_5_mux, B1=>InitReady,
|
|
A1=>CmdValid_fast, D0=>wb_ack, C0=>un1_FS_29, B0=>un1_FS_11,
|
|
A0=>InitReady, F0=>d_N_5_mux, F1=>un1_FS_38_i);
|
|
SLICE_63I: SLICE_63
|
|
port map (D1=>CO0, C1=>S_1, B1=>InitReady, A1=>RASr2, D0=>S_1, C0=>Ready,
|
|
B0=>N_254, A0=>N_250, F0=>N_39, F1=>N_250);
|
|
SLICE_64I: SLICE_64
|
|
port map (D1=>Ready, C1=>nRCAS_0_sqmuxa_1, B1=>nRWE_0io_RNO_1,
|
|
A1=>N_37_i_1, D0=>Ready, C0=>RASr2, B0=>N_41, A0=>CBR_fast,
|
|
F0=>nRCAS_0_sqmuxa_1, F1=>N_37_i);
|
|
SLICE_65I: SLICE_65
|
|
port map (D1=>un1_FS_40_1_0_1, C1=>FS_13, B1=>FS_10, A1=>FS_9, D0=>FS_14,
|
|
C0=>FS_12, B0=>FS_11, A0=>FS_9, F0=>un1_FS_40_1_0_1,
|
|
F1=>un1_FS_40_1_0);
|
|
SLICE_66I: SLICE_66
|
|
port map (C1=>S_1, B1=>N_39, A1=>CBR, D0=>S_1, C0=>nRCAS_0io_RNO_0,
|
|
B0=>nRCAS_0_sqmuxa_1, A0=>N_28_i_1, F0=>N_249_i,
|
|
F1=>nRCAS_0io_RNO_0);
|
|
SLICE_67I: SLICE_67
|
|
port map (D1=>FS_9, C1=>wb_rst11, B1=>FS_13, A1=>N_230,
|
|
C0=>un1_wb_we95_1, B0=>wb_rst11, A0=>N_94, F0=>N_49, F1=>N_94);
|
|
SLICE_68I: SLICE_68
|
|
port map (C1=>Ready, B1=>nRWE_0io_RNO_4, A1=>nRWE_0io_RNO_3, D0=>IS_1,
|
|
C0=>IS_2, B0=>IS_0, A0=>N_250, F0=>nRWE_0io_RNO_4,
|
|
F1=>nRWE_0io_RNO_1);
|
|
SLICE_69I: SLICE_69
|
|
port map (C1=>nRRAS_0_sqmuxa, B1=>RCKE_c, A1=>RASr2, C0=>CO0, B0=>S_1,
|
|
A0=>Ready, F0=>nRRAS_0_sqmuxa, F1=>nRWE_0io_RNO_3);
|
|
SLICE_70I: SLICE_70
|
|
port map (D1=>N_131, C1=>N_119, B1=>FS_14, A1=>FS_13, C0=>FS_10,
|
|
B0=>FS_11, A0=>FS_12, F0=>N_131, F1=>N_85);
|
|
SLICE_71I: SLICE_71
|
|
port map (B1=>FS_11, A1=>FS_10, D0=>FS_12, C0=>N_116, B0=>FS_13,
|
|
A0=>FS_14, F0=>wb_dati_5_1_iv_0_a3_0_0_7, F1=>N_116);
|
|
SLICE_72I: SLICE_72
|
|
port map (D1=>wb_rst11, C1=>N_248, B1=>FS_14, A1=>FS_13, D0=>FS_10,
|
|
C0=>FS_11, B0=>FS_12, A0=>FS_9, F0=>N_248, F1=>N_240);
|
|
SLICE_73I: SLICE_73
|
|
port map (D1=>XOR8MEG14_1, C1=>Din_c_7, B1=>Din_c_5, A1=>Din_c_3,
|
|
D0=>C1WR_7, C0=>CMDWR_2, B0=>CmdEnable, A0=>XOR8MEG14,
|
|
M0=>Din_c_0, CE=>CmdUFMData_1_sqmuxa, CLK=>PHI2_c,
|
|
F0=>CmdUFMData_1_sqmuxa, Q0=>CmdUFMData, F1=>XOR8MEG14);
|
|
SLICE_74I: SLICE_74
|
|
port map (D1=>wb_dati_5_1_iv_0_a3_0_6, C1=>N_246, B1=>FS_12, A1=>FS_10,
|
|
D0=>wb_dati_5, C0=>N_98, B0=>N_85, A0=>InitReady,
|
|
F0=>wb_dati_5_1_iv_0_1_6, F1=>N_98);
|
|
SLICE_75I: SLICE_75
|
|
port map (C1=>FS_14, B1=>wb_rst11, A1=>FS_11,
|
|
D0=>wb_dati_5_1_iv_0_a3_0_3, C0=>wb_dati_2, B0=>N_128,
|
|
A0=>InitReady, F0=>wb_dati_5_1_iv_0_0_3, F1=>N_128);
|
|
SLICE_76I: SLICE_76
|
|
port map (D1=>FS_15, C1=>FS_16, B1=>FS_17, A1=>InitReady, B0=>wb_rst11,
|
|
A0=>un1_wb_we95_1, F0=>un1_wb_rst11_1_s6_1, F1=>wb_rst11);
|
|
SLICE_77I: SLICE_77
|
|
port map (C1=>IS_1, B1=>IS_2, A1=>IS_3, D0=>nRRAS_5_u_i_0, C0=>N_254,
|
|
B0=>N_250, A0=>IS_0, F0=>N_25, F1=>N_254);
|
|
SLICE_78I: SLICE_78
|
|
port map (C1=>FS_12, B1=>FS_10, A1=>FS_9, C0=>N_128, B0=>N_59, A0=>FS_13,
|
|
F0=>N_89, F1=>N_59);
|
|
SLICE_79I: SLICE_79
|
|
port map (C1=>wb_rst11, B1=>FS_14, A1=>FS_13,
|
|
D0=>wb_dati_5_1_iv_0_a3_2_0_1, C0=>wb_dati_0, B0=>N_248,
|
|
A0=>InitReady, F0=>wb_dati_5_1_iv_0_0_1,
|
|
F1=>wb_dati_5_1_iv_0_a3_2_0_1);
|
|
SLICE_80I: SLICE_80
|
|
port map (D1=>FS_13, C1=>FS_12, B1=>FS_10, A1=>FS_9,
|
|
D0=>wb_dati_5_1_iv_0_a3_1_1_4, C0=>N_248, B0=>N_246, A0=>N_85,
|
|
F0=>wb_dati_5_1_iv_0_1_4, F1=>wb_dati_5_1_iv_0_a3_1_1_4);
|
|
SLICE_81I: SLICE_81
|
|
port map (D1=>wb_rst11, C1=>wb_dati_5_1_iv_0_a3_3_0_7, B1=>FS_12,
|
|
A1=>FS_10, D0=>wb_dati_6, C0=>N_242, B0=>N_91, A0=>InitReady,
|
|
F0=>wb_dati_5_1_iv_0_1_7, F1=>N_242);
|
|
SLICE_82I: SLICE_82
|
|
port map (B1=>FS_14, A1=>FS_13, D0=>wb_we95_0_tz_tz_tz, C0=>un1_FS_20_3,
|
|
B0=>FS_12, A0=>FS_11, F0=>un1_wb_we95_1, F1=>un1_FS_20_3);
|
|
SLICE_83I: SLICE_83
|
|
port map (C1=>FS_12, B1=>FS_11, A1=>FS_10, D0=>N_120, C0=>N_119,
|
|
B0=>FS_14, A0=>FS_13, F0=>N_91, F1=>N_120);
|
|
SLICE_84I: SLICE_84
|
|
port map (D1=>wb_we95_0_tz_tz_tz, C1=>N_228, B1=>FS_14, A1=>FS_13,
|
|
C0=>wb_we113_i, B0=>wb_we95, A0=>un1_FS_29, F0=>N_181,
|
|
F1=>un1_FS_29);
|
|
SLICE_85I: SLICE_85
|
|
port map (C1=>wb_rst11, B1=>un1_FS_40_1_1_1, A1=>un1_FS_40_1_0,
|
|
D0=>un1_FS_40_1_1_tz, C0=>N_139, B0=>FS_10, A0=>FS_9,
|
|
F0=>un1_FS_40_1_1_1, F1=>wb_adr_cnst_m2_0);
|
|
SLICE_86I: SLICE_86
|
|
port map (D1=>FS_12, C1=>FS_11, B1=>FS_10, A1=>FS_9, C0=>N_136,
|
|
B0=>FS_14, A0=>FS_13, F0=>N_139, F1=>N_136);
|
|
SLICE_87I: SLICE_87
|
|
port map (B1=>FS_10, A1=>FS_9, D0=>wb_we95_0_tz_tz_tz, C0=>un1_FS_20_3,
|
|
B0=>FS_12, A0=>FS_11, F0=>wb_we95, F1=>wb_we95_0_tz_tz_tz);
|
|
SLICE_88I: SLICE_88
|
|
port map (D1=>Ready, C1=>N_28_i_sn, B1=>N_28_i_1, A1=>N_25_i,
|
|
D0=>FWEr_fast, C0=>CO0, B0=>CASr3, A0=>CASr2, F0=>N_28_i_1,
|
|
F1=>N_28_i);
|
|
SLICE_89I: SLICE_89
|
|
port map (B1=>wb_req, A1=>FS_0, D0=>N_233, C0=>N_102_2, B0=>N_102_1,
|
|
A0=>InitReady, F0=>N_102, F1=>N_233);
|
|
SLICE_90I: SLICE_90
|
|
port map (D1=>ADWR_7, C1=>C1WR_2, B1=>C1WR_7, A1=>CMDWR_2, D0=>N_304,
|
|
C0=>MAin_c_7, B0=>MAin_c_6, A0=>MAin_c_5, F0=>C1WR_7,
|
|
F1=>un1_CMDWR);
|
|
SLICE_91I: SLICE_91
|
|
port map (C1=>C1WR_7, B1=>C1WR_2, A1=>ADWR_7, D0=>MAin_c_3, C0=>MAin_c_1,
|
|
B0=>ADWR_5, A0=>ADWR_4, F0=>ADWR_7, F1=>un1_ADWR);
|
|
SLICE_92I: SLICE_92
|
|
port map (C1=>MAin_c_4, B1=>MAin_c_3, A1=>MAin_c_2, D0=>nFWE_c,
|
|
C0=>MAin_c_1, B0=>MAin_c_0, A0=>C1WR_0, F0=>C1WR_2, F1=>C1WR_0);
|
|
SLICE_93I: SLICE_93
|
|
port map (C1=>wb_we113_i, B1=>wb_rst11, A1=>un1_FS_37_i_0,
|
|
D0=>wb_we95_0_tz_tz_tz, C0=>N_228, B0=>FS_14, A0=>FS_13,
|
|
F0=>wb_we113_i, F1=>un1_wb_adr_0_sqmuxa_3);
|
|
SLICE_94I: SLICE_94
|
|
port map (B1=>Bank_1, A1=>Bank_0, D0=>un1_Bank_1_4, C0=>un1_Bank_1_3,
|
|
B0=>Bank_4, A0=>Bank_3, F0=>N_304, F1=>un1_Bank_1_3);
|
|
SLICE_95I: SLICE_95
|
|
port map (B1=>PHI2r3, A1=>PHI2r2, D0=>un1_PHI2r3_0, C0=>InitReady,
|
|
B0=>CmdValid, A0=>CmdUFMShift, F0=>N_245, F1=>un1_PHI2r3_0);
|
|
SLICE_96I: SLICE_96
|
|
port map (C1=>FS_8, B1=>FS_6, A1=>FS_1, C0=>wb_req, B0=>N_102_1,
|
|
A0=>FS_0, F0=>un1_wb_cyc_stb_1_sqmuxa_0_a3_0_1, F1=>N_102_1);
|
|
SLICE_97I: SLICE_97
|
|
port map (B1=>PHI2r3, A1=>PHI2r2, D0=>InitReady, C0=>G_8_0_a3_0_0,
|
|
B0=>CmdValid_fast, A0=>CmdUFMShift_fast, F0=>un1_wb_rst14_i,
|
|
F1=>G_8_0_a3_0_0);
|
|
SLICE_98I: SLICE_98
|
|
port map (D1=>S_1, C1=>CO0, B1=>CASr3, A1=>CASr2, C0=>nRWE_0io_RNO_2,
|
|
B0=>FWEr, A0=>CBR_fast, F0=>N_37_i_1, F1=>nRWE_0io_RNO_2);
|
|
SLICE_99I: SLICE_99
|
|
port map (D1=>FS_13, C1=>FS_12, B1=>FS_10, A1=>FS_9, D0=>FS_13,
|
|
C0=>FS_12, B0=>FS_10, A0=>FS_9, F0=>wb_dati_5_1_iv_0_a3_0_3,
|
|
F1=>wb_dati_5_1_iv_0_a3_0_0_1);
|
|
SLICE_100I: SLICE_100
|
|
port map (D1=>FS_14, C1=>FS_13, B1=>FS_12, A1=>FS_11, D0=>FS_14,
|
|
C0=>FS_12, B0=>FS_11, A0=>FS_10, F0=>N_230,
|
|
F1=>un1_FS_40_1_1_tz);
|
|
SLICE_101I: SLICE_101
|
|
port map (D1=>Din_c_7, C1=>Din_c_5, B1=>Din_c_4, A1=>Din_c_3,
|
|
D0=>Din_c_7, C0=>Din_c_6, B0=>Din_c_5, A0=>Din_c_4,
|
|
F0=>un1_Din_2, F1=>CmdEnable17_5);
|
|
SLICE_102I: SLICE_102
|
|
port map (D1=>FS_17, C1=>FS_16, B1=>FS_15, A1=>FS_12, C0=>FS_17,
|
|
B0=>FS_16, A0=>FS_15, F0=>un1_FS_11, F1=>InitReady3_0_a3_2);
|
|
SLICE_103I: SLICE_103
|
|
port map (C1=>FS_13, B1=>FS_11, A1=>FS_9, D0=>FS_14, C0=>FS_13,
|
|
B0=>FS_11, A0=>FS_9, F0=>wb_dati_5_1_iv_0_a3_3_0_7,
|
|
F1=>wb_dati_5_1_iv_0_a3_0_6);
|
|
SLICE_104I: SLICE_104
|
|
port map (D1=>Din_c_6, C1=>Din_c_5, B1=>Din_c_1, A1=>Din_c_0,
|
|
D0=>Din_c_6, C0=>Din_c_2, B0=>Din_c_1, A0=>Din_c_0,
|
|
F0=>CmdEnable17_4, F1=>CmdEnable16_4);
|
|
SLICE_105I: SLICE_105
|
|
port map (C1=>nFWE_c, B1=>MAin_c_6, A1=>MAin_c_0, D0=>nFWE_c,
|
|
C0=>MAin_c_1, B0=>MAin_c_0, A0=>C1WR_0, M1=>nCCAS_c_i,
|
|
M0=>nCCAS_c_i, CLK=>nCRAS_c, F0=>CMDWR_2, Q0=>CBR, F1=>ADWR_4,
|
|
Q1=>CBR_fast);
|
|
SLICE_106I: SLICE_106
|
|
port map (B1=>Din_c_3, A1=>Din_c_2, D0=>Din_c_7, C0=>Din_c_4,
|
|
B0=>Din_c_3, A0=>Din_c_2, M0=>CASr2, CLK=>RCLK_c,
|
|
F0=>CmdEnable16_5, Q0=>CASr3, F1=>XOR8MEG9_1);
|
|
SLICE_107I: SLICE_107
|
|
port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_9,
|
|
A0=>MAin_c_9, F0=>RA_c_9, F1=>RDQMH_c);
|
|
SLICE_108I: SLICE_108
|
|
port map (D1=>IS_0, C1=>N_250, B1=>N_254, A1=>nRRAS_5_u_i_0, B0=>Ready,
|
|
A0=>N_250, M0=>nFWE_c_i, CLK=>nCRAS_c, F0=>N_253_i,
|
|
Q0=>FWEr_fast, F1=>N_25_i);
|
|
SLICE_109I: SLICE_109
|
|
port map (B1=>wb_rst11, A1=>FS_14, B0=>wb_rst11, A0=>FS_9, F0=>N_119,
|
|
F1=>N_246);
|
|
SLICE_110I: SLICE_110
|
|
port map (B1=>FS_12, A1=>FS_11, D0=>N_116, C0=>FS_14, B0=>FS_13,
|
|
A0=>FS_12, F0=>wb_dati_5_0_iv_0_a3_1_0, F1=>N_228);
|
|
SLICE_111I: SLICE_111
|
|
port map (C1=>nRowColSel, B1=>RowA_7, A1=>MAin_c_7, D0=>MAin_c_7,
|
|
C0=>MAin_c_5, B0=>MAin_c_4, A0=>MAin_c_2, F0=>ADWR_5,
|
|
F1=>RA_c_7);
|
|
SLICE_112I: SLICE_112
|
|
port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>RowA_0,
|
|
A0=>MAin_c_0, F0=>RA_c_0, F1=>RDQML_c);
|
|
SLICE_113I: SLICE_113
|
|
port map (C1=>nRowColSel, B1=>RowA_8, A1=>MAin_c_8, C0=>nRowColSel,
|
|
B0=>RowA_1, A0=>MAin_c_1, F0=>RA_c_1, F1=>RA_c_8);
|
|
SLICE_114I: SLICE_114
|
|
port map (C1=>nRowColSel, B1=>RowA_6, A1=>MAin_c_6, C0=>nRowColSel,
|
|
B0=>RowA_2, A0=>MAin_c_2, F0=>RA_c_2, F1=>RA_c_6);
|
|
SLICE_115I: SLICE_115
|
|
port map (C1=>nRowColSel, B1=>RowA_5, A1=>MAin_c_5, C0=>nRowColSel,
|
|
B0=>RowA_3, A0=>MAin_c_3, F0=>RA_c_3, F1=>RA_c_5);
|
|
SLICE_116I: SLICE_116
|
|
port map (D1=>n8MEGEN, C1=>XOR8MEG, B1=>Ready_fast, A1=>Din_c_6,
|
|
B0=>Din_c_6, A0=>Din_c_4, F0=>XOR8MEG14_1, F1=>RA11d_0);
|
|
SLICE_117I: SLICE_117
|
|
port map (C1=>S_1, B1=>N_25, A1=>CBR_fast, D0=>S_1, C0=>FWEr, B0=>CO0,
|
|
A0=>CASr2, F0=>RCKEEN_8_u_1_0, F1=>N_28_i_sn);
|
|
SLICE_118I: SLICE_118
|
|
port map (B1=>Ready_fast, A1=>CROW_c_0, B0=>Ready_fast, A0=>CROW_c_1,
|
|
M0=>PHI2r2, CLK=>RCLK_c, F0=>RBAd_0_1, Q0=>PHI2r3,
|
|
F1=>RBAd_0_0);
|
|
RD_0_I: RD_0_B
|
|
port map (PADDI=>RD_in_0, IOLDO=>WRD_0, PADDT=>RD_1_i, RD0=>RD(0));
|
|
RD_0_MGIOLI: RD_0_MGIOL
|
|
port map (IOLDO=>WRD_0, OPOS=>Din_c_0, CLK=>nCCAS_c);
|
|
Dout_0_I: Dout_0_B
|
|
port map (PADDO=>RD_in_0, Dout0=>Dout(0));
|
|
PHI2I: PHI2B
|
|
port map (PADDI=>PHI2_c, PHI2S=>PHI2);
|
|
PHI2_MGIOLI: PHI2_MGIOL
|
|
port map (DI=>PHI2_c, CLK=>RCLK_c, INP=>PHI2r);
|
|
RDQMLI: RDQMLB
|
|
port map (PADDO=>RDQML_c, RDQMLS=>RDQML);
|
|
RDQMHI: RDQMHB
|
|
port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH);
|
|
nRCASI: nRCASB
|
|
port map (IOLDO=>nRCAS_c, nRCASS=>nRCAS);
|
|
nRCAS_MGIOLI: nRCAS_MGIOL
|
|
port map (IOLDO=>nRCAS_c, OPOS=>N_249_i, CLK=>RCLK_c);
|
|
nRRASI: nRRASB
|
|
port map (IOLDO=>nRRAS_c, nRRASS=>nRRAS);
|
|
nRRAS_MGIOLI: nRRAS_MGIOL
|
|
port map (IOLDO=>nRRAS_c, OPOS=>N_25_i, CLK=>RCLK_c);
|
|
nRWEI: nRWEB
|
|
port map (IOLDO=>nRWE_c, nRWES=>nRWE);
|
|
nRWE_MGIOLI: nRWE_MGIOL
|
|
port map (IOLDO=>nRWE_c, OPOS=>N_37_i, CLK=>RCLK_c);
|
|
RCKEI: RCKEB
|
|
port map (PADDO=>RCKE_c, RCKES=>RCKE);
|
|
RCLKI: RCLKB
|
|
port map (PADDI=>RCLK_c, RCLKS=>RCLK);
|
|
nRCSI: nRCSB
|
|
port map (IOLDO=>nRCS_c, nRCSS=>nRCS);
|
|
nRCS_MGIOLI: nRCS_MGIOL
|
|
port map (IOLDO=>nRCS_c, OPOS=>N_28_i, CLK=>RCLK_c);
|
|
RD_7_I: RD_7_B
|
|
port map (PADDI=>RD_in_7, IOLDO=>WRD_7, PADDT=>RD_1_i, RD7=>RD(7));
|
|
RD_7_MGIOLI: RD_7_MGIOL
|
|
port map (IOLDO=>WRD_7, OPOS=>Din_c_7, CLK=>nCCAS_c);
|
|
RD_6_I: RD_6_B
|
|
port map (PADDI=>RD_in_6, IOLDO=>WRD_6, PADDT=>RD_1_i, RD6=>RD(6));
|
|
RD_6_MGIOLI: RD_6_MGIOL
|
|
port map (IOLDO=>WRD_6, OPOS=>Din_c_6, CLK=>nCCAS_c);
|
|
RD_5_I: RD_5_B
|
|
port map (PADDI=>RD_in_5, IOLDO=>WRD_5, PADDT=>RD_1_i, RD5=>RD(5));
|
|
RD_5_MGIOLI: RD_5_MGIOL
|
|
port map (IOLDO=>WRD_5, OPOS=>Din_c_5, CLK=>nCCAS_c);
|
|
RD_4_I: RD_4_B
|
|
port map (PADDI=>RD_in_4, IOLDO=>WRD_4, PADDT=>RD_1_i, RD4=>RD(4));
|
|
RD_4_MGIOLI: RD_4_MGIOL
|
|
port map (IOLDO=>WRD_4, OPOS=>Din_c_4, CLK=>nCCAS_c);
|
|
RD_3_I: RD_3_B
|
|
port map (PADDI=>RD_in_3, IOLDO=>WRD_3, PADDT=>RD_1_i, RD3=>RD(3));
|
|
RD_3_MGIOLI: RD_3_MGIOL
|
|
port map (IOLDO=>WRD_3, OPOS=>Din_c_3, CLK=>nCCAS_c);
|
|
RD_2_I: RD_2_B
|
|
port map (PADDI=>RD_in_2, IOLDO=>WRD_2, PADDT=>RD_1_i, RD2=>RD(2));
|
|
RD_2_MGIOLI: RD_2_MGIOL
|
|
port map (IOLDO=>WRD_2, OPOS=>Din_c_2, CLK=>nCCAS_c);
|
|
RD_1_I0: RD_1_B
|
|
port map (PADDI=>RD_in_1, IOLDO=>WRD_1, PADDT=>RD_1_i, RD1=>RD(1));
|
|
RD_1_MGIOLI: RD_1_MGIOL
|
|
port map (IOLDO=>WRD_1, OPOS=>Din_c_1, CLK=>nCCAS_c);
|
|
RA_11_I: RA_11_B
|
|
port map (IOLDO=>RA_c_11, RA11=>RA(11));
|
|
RA_11_MGIOLI: RA_11_MGIOL
|
|
port map (IOLDO=>RA_c_11, OPOS=>RA11d_0, CLK=>PHI2_c);
|
|
RA_10_I: RA_10_B
|
|
port map (IOLDO=>RA_c_10, RA10=>RA(10));
|
|
RA_10_MGIOLI: RA_10_MGIOL
|
|
port map (IOLDO=>RA_c_10, OPOS=>N_45, LSR=>RA10s_i, CLK=>RCLK_c);
|
|
RA_9_I: RA_9_B
|
|
port map (PADDO=>RA_c_9, RA9=>RA(9));
|
|
RA_8_I: RA_8_B
|
|
port map (PADDO=>RA_c_8, RA8=>RA(8));
|
|
RA_7_I: RA_7_B
|
|
port map (PADDO=>RA_c_7, RA7=>RA(7));
|
|
RA_6_I: RA_6_B
|
|
port map (PADDO=>RA_c_6, RA6=>RA(6));
|
|
RA_5_I: RA_5_B
|
|
port map (PADDO=>RA_c_5, RA5=>RA(5));
|
|
RA_4_I: RA_4_B
|
|
port map (PADDO=>RA_c_4, RA4=>RA(4));
|
|
RA_3_I: RA_3_B
|
|
port map (PADDO=>RA_c_3, RA3=>RA(3));
|
|
RA_2_I: RA_2_B
|
|
port map (PADDO=>RA_c_2, RA2=>RA(2));
|
|
RA_1_I: RA_1_B
|
|
port map (PADDO=>RA_c_1, RA1=>RA(1));
|
|
RA_0_I: RA_0_B
|
|
port map (PADDO=>RA_c_0, RA0=>RA(0));
|
|
RBA_1_I: RBA_1_B
|
|
port map (IOLDO=>RBA_c_1, RBA1=>RBA(1));
|
|
RBA_1_MGIOLI: RBA_1_MGIOL
|
|
port map (IOLDO=>RBA_c_1, OPOS=>RBAd_0_1, CLK=>nCRAS_c);
|
|
RBA_0_I: RBA_0_B
|
|
port map (IOLDO=>RBA_c_0, RBA0=>RBA(0));
|
|
RBA_0_MGIOLI: RBA_0_MGIOL
|
|
port map (IOLDO=>RBA_c_0, OPOS=>RBAd_0_0, CLK=>nCRAS_c);
|
|
LEDI: LEDB
|
|
port map (PADDO=>LED_c, LEDS=>LED);
|
|
nFWEI: nFWEB
|
|
port map (PADDI=>nFWE_c, nFWES=>nFWE);
|
|
nCRASI: nCRASB
|
|
port map (PADDI=>nCRAS_c, nCRASS=>nCRAS);
|
|
nCCASI: nCCASB
|
|
port map (PADDI=>nCCAS_c, nCCASS=>nCCAS);
|
|
Dout_7_I: Dout_7_B
|
|
port map (PADDO=>RD_in_7, Dout7=>Dout(7));
|
|
Dout_6_I: Dout_6_B
|
|
port map (PADDO=>RD_in_6, Dout6=>Dout(6));
|
|
Dout_5_I: Dout_5_B
|
|
port map (PADDO=>RD_in_5, Dout5=>Dout(5));
|
|
Dout_4_I: Dout_4_B
|
|
port map (PADDO=>RD_in_4, Dout4=>Dout(4));
|
|
Dout_3_I: Dout_3_B
|
|
port map (PADDO=>RD_in_3, Dout3=>Dout(3));
|
|
Dout_2_I: Dout_2_B
|
|
port map (PADDO=>RD_in_2, Dout2=>Dout(2));
|
|
Dout_1_I: Dout_1_B
|
|
port map (PADDO=>RD_in_1, Dout1=>Dout(1));
|
|
Din_7_I: Din_7_B
|
|
port map (PADDI=>Din_c_7, Din7=>Din(7));
|
|
Din_7_MGIOLI: Din_7_MGIOL
|
|
port map (DI=>Din_c_7, CLK=>PHI2_c, INP=>Bank_7);
|
|
Din_6_I: Din_6_B
|
|
port map (PADDI=>Din_c_6, Din6=>Din(6));
|
|
Din_6_MGIOLI: Din_6_MGIOL
|
|
port map (DI=>Din_c_6, CLK=>PHI2_c, INP=>Bank_6);
|
|
Din_5_I: Din_5_B
|
|
port map (PADDI=>Din_c_5, Din5=>Din(5));
|
|
Din_5_MGIOLI: Din_5_MGIOL
|
|
port map (DI=>Din_c_5, CLK=>PHI2_c, INP=>Bank_5);
|
|
Din_4_I: Din_4_B
|
|
port map (PADDI=>Din_c_4, Din4=>Din(4));
|
|
Din_4_MGIOLI: Din_4_MGIOL
|
|
port map (DI=>Din_c_4, CLK=>PHI2_c, INP=>Bank_4);
|
|
Din_3_I: Din_3_B
|
|
port map (PADDI=>Din_c_3, Din3=>Din(3));
|
|
Din_3_MGIOLI: Din_3_MGIOL
|
|
port map (DI=>Din_c_3, CLK=>PHI2_c, INP=>Bank_3);
|
|
Din_2_I: Din_2_B
|
|
port map (PADDI=>Din_c_2, Din2=>Din(2));
|
|
Din_2_MGIOLI: Din_2_MGIOL
|
|
port map (DI=>Din_c_2, CLK=>PHI2_c, INP=>Bank_2);
|
|
Din_1_I: Din_1_B
|
|
port map (PADDI=>Din_c_1, Din1=>Din(1));
|
|
Din_1_MGIOLI: Din_1_MGIOL
|
|
port map (DI=>Din_c_1, CLK=>PHI2_c, INP=>Bank_1);
|
|
Din_0_I: Din_0_B
|
|
port map (PADDI=>Din_c_0, Din0=>Din(0));
|
|
Din_0_MGIOLI: Din_0_MGIOL
|
|
port map (DI=>Din_c_0, CLK=>PHI2_c, INP=>Bank_0);
|
|
CROW_1_I: CROW_1_B
|
|
port map (PADDI=>CROW_c_1, CROW1=>CROW(1));
|
|
CROW_0_I: CROW_0_B
|
|
port map (PADDI=>CROW_c_0, CROW0=>CROW(0));
|
|
MAin_9_I: MAin_9_B
|
|
port map (PADDI=>MAin_c_9, MAin9=>MAin(9));
|
|
MAin_8_I: MAin_8_B
|
|
port map (PADDI=>MAin_c_8, MAin8=>MAin(8));
|
|
MAin_7_I: MAin_7_B
|
|
port map (PADDI=>MAin_c_7, MAin7=>MAin(7));
|
|
MAin_6_I: MAin_6_B
|
|
port map (PADDI=>MAin_c_6, MAin6=>MAin(6));
|
|
MAin_5_I: MAin_5_B
|
|
port map (PADDI=>MAin_c_5, MAin5=>MAin(5));
|
|
MAin_4_I: MAin_4_B
|
|
port map (PADDI=>MAin_c_4, MAin4=>MAin(4));
|
|
MAin_3_I: MAin_3_B
|
|
port map (PADDI=>MAin_c_3, MAin3=>MAin(3));
|
|
MAin_2_I: MAin_2_B
|
|
port map (PADDI=>MAin_c_2, MAin2=>MAin(2));
|
|
MAin_1_I: MAin_1_B
|
|
port map (PADDI=>MAin_c_1, MAin1=>MAin(1));
|
|
MAin_0_I: MAin_0_B
|
|
port map (PADDI=>MAin_c_0, MAin0=>MAin(0));
|
|
ufmefb_EFBInst_0I: ufmefb_EFBInst_0
|
|
port map (WBCLKI=>RCLK_c, WBRSTI=>wb_rst, WBCYCI=>wb_cyc_stb,
|
|
WBSTBI=>wb_cyc_stb, WBWEI=>wb_we, WBADRI0=>wb_adr_0,
|
|
WBADRI1=>wb_adr_1, WBADRI2=>wb_adr_2, WBADRI3=>wb_adr_3,
|
|
WBADRI4=>wb_adr_4, WBADRI5=>wb_adr_5, WBADRI6=>wb_adr_6,
|
|
WBADRI7=>wb_adr_7, WBDATI0=>wb_dati_0, WBDATI1=>wb_dati_1,
|
|
WBDATI2=>wb_dati_2, WBDATI3=>wb_dati_3, WBDATI4=>wb_dati_4,
|
|
WBDATI5=>wb_dati_5, WBDATI6=>wb_dati_6, WBDATI7=>wb_dati_7,
|
|
WBDATO0=>wb_dato_0, WBDATO1=>wb_dato_1, WBACKO=>wb_ack);
|
|
VHI_INST: VHI
|
|
port map (Z=>VCCI);
|
|
PUR_INST: PUR
|
|
port map (PUR=>VCCI);
|
|
GSR_INST: GSR
|
|
port map (GSR=>VCCI);
|
|
end Structure;
|
|
|
|
|
|
|
|
library IEEE, vital2000, MACHXO2;
|
|
configuration Structure_CON of RAM2GS is
|
|
for Structure
|
|
end for;
|
|
end Structure_CON;
|
|
|
|
|