mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-12-01 10:49:51 +00:00
156 lines
4.5 KiB
Plaintext
156 lines
4.5 KiB
Plaintext
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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# Written on Sat Aug 19 20:53:13 2023
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##### DESIGN INFO #######################################################
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Top View: "RAM2GS"
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Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
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##### SUMMARY ############################################################
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Found 0 issues in 0 out of 4 constraints
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##### DETAILS ############################################################
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Clock Relationships
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*******************
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Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
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-----------------------------------------------------------------------------------------------------------------------------------
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RCLK RCLK | 16.000 | No paths | No paths | No paths
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RCLK PHI2 | 2.000 | No paths | 1.000 | No paths
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RCLK nCRAS | No paths | No paths | 1.000 | No paths
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PHI2 RCLK | No paths | No paths | No paths | 1.000
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PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000
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nCRAS RCLK | No paths | No paths | No paths | 1.000
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===================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
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@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
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@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
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@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
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@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
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Unconstrained Start/End Points
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******************************
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p:CROW[0]
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p:CROW[1]
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p:Din[0]
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p:Din[1]
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p:Din[2]
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p:Din[3]
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p:Din[4]
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p:Din[5]
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p:Din[6]
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p:Din[7]
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p:Dout[0]
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p:Dout[1]
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p:Dout[2]
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p:Dout[3]
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p:Dout[4]
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p:Dout[5]
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p:Dout[6]
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p:Dout[7]
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p:MAin[0]
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p:MAin[1]
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p:MAin[2]
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p:MAin[3]
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p:MAin[4]
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p:MAin[5]
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p:MAin[6]
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p:MAin[7]
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p:MAin[8]
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p:MAin[9]
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p:RA[0]
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p:RA[1]
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p:RA[2]
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p:RA[3]
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p:RA[4]
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p:RA[5]
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p:RA[6]
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p:RA[7]
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p:RA[8]
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p:RA[9]
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p:RA[10]
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p:RA[11]
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p:RBA[0]
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p:RBA[1]
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p:RCKE
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p:RDQMH
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p:RDQML
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p:RD[0] (bidir end point)
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p:RD[0] (bidir start point)
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p:RD[1] (bidir end point)
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p:RD[1] (bidir start point)
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p:RD[2] (bidir end point)
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p:RD[2] (bidir start point)
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p:RD[3] (bidir end point)
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p:RD[3] (bidir start point)
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p:RD[4] (bidir end point)
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p:RD[4] (bidir start point)
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p:RD[5] (bidir end point)
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p:RD[5] (bidir start point)
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p:RD[6] (bidir end point)
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p:RD[6] (bidir start point)
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p:RD[7] (bidir end point)
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p:RD[7] (bidir start point)
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p:UFMCLK
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p:UFMSDI
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p:UFMSDO
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p:nFWE
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p:nRCAS
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p:nRCS
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p:nRRAS
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p:nRWE
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p:nUFMCS
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Inapplicable constraints
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************************
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(none)
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Applicable constraints with issues
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**********************************
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(none)
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Constraints with matching wildcard expressions
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**********************************************
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(none)
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Library Report
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**************
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# End of Constraint Checker Report
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