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RAM2GS/CPLD/MAXII/db/RAM4GS.fit.qmsg
Zane Kaminski 64a083dcbb Move stuff around
2021-04-29 19:44:34 -04:00

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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""}
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