401 lines
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401 lines
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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Sat Oct 09 01:19:14 2021
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: RAM2GS
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
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130 items scored, 125 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 10.606ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
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Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
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Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
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Constraint Details:
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12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
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2.500ns delay constraint less
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0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
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Path Details: Bank_i4 to CmdLEDEN_545
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
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Route 1 e 0.941 Bank[4]
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LUT4 --- 0.493 C to Z i3734_4_lut
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Route 1 e 0.941 n4610
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LUT4 --- 0.493 B to Z i3751_4_lut
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Route 2 e 1.141 n4628
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LUT4 --- 0.493 B to Z i13_4_lut_adj_13
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Route 4 e 1.340 n2384
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LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
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Route 2 e 1.141 n4889
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LUT4 --- 0.493 D to Z i3_4_lut_adj_23
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Route 4 e 1.340 XOR8MEG_N_149
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LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
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Route 1 e 0.941 n4882
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LUT4 --- 0.493 A to Z i1_3_lut_adj_21
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Route 2 e 1.141 PHI2_N_151_enable_5
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--------
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12.821 (30.4% logic, 69.6% route), 8 logic levels.
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Error: The following path violates requirements by 10.606ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
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Destination: FD1P3AX SP Cmdn8MEGEN_546 (to PHI2_c -)
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Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
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Constraint Details:
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12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
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2.500ns delay constraint less
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0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
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Path Details: Bank_i4 to Cmdn8MEGEN_546
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
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Route 1 e 0.941 Bank[4]
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LUT4 --- 0.493 C to Z i3734_4_lut
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Route 1 e 0.941 n4610
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LUT4 --- 0.493 B to Z i3751_4_lut
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Route 2 e 1.141 n4628
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LUT4 --- 0.493 B to Z i13_4_lut_adj_13
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Route 4 e 1.340 n2384
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LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
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Route 2 e 1.141 n4889
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LUT4 --- 0.493 D to Z i3_4_lut_adj_23
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Route 4 e 1.340 XOR8MEG_N_149
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LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
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Route 1 e 0.941 n4882
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LUT4 --- 0.493 A to Z i1_3_lut_adj_21
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Route 2 e 1.141 PHI2_N_151_enable_5
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--------
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12.821 (30.4% logic, 69.6% route), 8 logic levels.
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Error: The following path violates requirements by 10.606ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
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Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
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Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
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Constraint Details:
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12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
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2.500ns delay constraint less
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0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
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Path Details: Bank_i5 to CmdLEDEN_545
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q Bank_i5 (from PHI2_c)
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Route 1 e 0.941 Bank[5]
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LUT4 --- 0.493 B to Z i3734_4_lut
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Route 1 e 0.941 n4610
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LUT4 --- 0.493 B to Z i3751_4_lut
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Route 2 e 1.141 n4628
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LUT4 --- 0.493 B to Z i13_4_lut_adj_13
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Route 4 e 1.340 n2384
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LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
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Route 2 e 1.141 n4889
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LUT4 --- 0.493 D to Z i3_4_lut_adj_23
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Route 4 e 1.340 XOR8MEG_N_149
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LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
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Route 1 e 0.941 n4882
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LUT4 --- 0.493 A to Z i1_3_lut_adj_21
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Route 2 e 1.141 PHI2_N_151_enable_5
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--------
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12.821 (30.4% logic, 69.6% route), 8 logic levels.
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Warning: 13.106 ns is the maximum delay for this constraint.
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
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1392 items scored, 1147 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path violates requirements by 10.222ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
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Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
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Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
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Constraint Details:
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15.062ns data_path FS_972__i8 to wb_adr_i4 violates
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5.000ns delay constraint less
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0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
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Path Details: FS_972__i8 to wb_adr_i4
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
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Route 23 e 1.894 FS[8]
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LUT4 --- 0.493 B to Z i1_2_lut_rep_75
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Route 4 e 1.340 n4924
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LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
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Route 1 e 0.941 n98
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LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
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Route 2 e 1.141 n2199
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LUT4 --- 0.493 B to Z i92_4_lut
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Route 1 e 0.941 n53
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LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
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Route 1 e 0.020 n1_adj_6
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MUXL5 --- 0.233 ALUT to Z i29
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Route 1 e 0.941 n14_adj_3
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LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
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Route 2 e 1.141 n12_adj_8
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LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
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Route 2 e 1.141 n14_adj_7
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LUT4 --- 0.493 A to Z i28_3_lut
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Route 1 e 0.941 wb_adr_7__N_60[4]
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--------
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15.062 (30.7% logic, 69.3% route), 10 logic levels.
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Error: The following path violates requirements by 10.222ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
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Destination: FD1S3AX D wb_adr_i6 (to RCLK_c +)
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Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
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Constraint Details:
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15.062ns data_path FS_972__i8 to wb_adr_i6 violates
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5.000ns delay constraint less
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0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
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Path Details: FS_972__i8 to wb_adr_i6
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
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Route 23 e 1.894 FS[8]
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LUT4 --- 0.493 B to Z i1_2_lut_rep_75
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Route 4 e 1.340 n4924
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LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
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Route 1 e 0.941 n98
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LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
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Route 2 e 1.141 n2199
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LUT4 --- 0.493 B to Z i92_4_lut
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Route 1 e 0.941 n53
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LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
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Route 1 e 0.020 n1_adj_6
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MUXL5 --- 0.233 ALUT to Z i29
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Route 1 e 0.941 n14_adj_3
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LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
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Route 2 e 1.141 n12_adj_8
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LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
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Route 2 e 1.141 n14_adj_7
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LUT4 --- 0.493 A to Z i29_3_lut
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Route 1 e 0.941 wb_adr_7__N_60[6]
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--------
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15.062 (30.7% logic, 69.3% route), 10 logic levels.
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Error: The following path violates requirements by 10.216ns
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Logical Details: Cell type Pin type Cell name (clock net +/-)
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Source: FD1S3AX CK FS_972__i6 (from RCLK_c +)
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Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
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Delay: 15.056ns (30.7% logic, 69.3% route), 10 logic levels.
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Constraint Details:
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15.056ns data_path FS_972__i6 to wb_adr_i4 violates
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5.000ns delay constraint less
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0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
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Path Details: FS_972__i6 to wb_adr_i4
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Name Fanout Delay (ns) Pins Resource(Cell.Net)
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L_CO --- 0.444 CK to Q FS_972__i6 (from RCLK_c)
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Route 21 e 1.888 FS[6]
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LUT4 --- 0.493 A to Z i1_2_lut_rep_75
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Route 4 e 1.340 n4924
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LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
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Route 1 e 0.941 n98
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LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
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Route 2 e 1.141 n2199
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LUT4 --- 0.493 B to Z i92_4_lut
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Route 1 e 0.941 n53
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LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
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Route 1 e 0.020 n1_adj_6
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MUXL5 --- 0.233 ALUT to Z i29
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Route 1 e 0.941 n14_adj_3
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LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
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Route 2 e 1.141 n12_adj_8
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LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
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Route 2 e 1.141 n14_adj_7
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LUT4 --- 0.493 A to Z i28_3_lut
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Route 1 e 0.941 wb_adr_7__N_60[4]
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--------
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15.056 (30.7% logic, 69.3% route), 10 logic levels.
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Warning: 15.222 ns is the maximum delay for this constraint.
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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create_clock -period 5.000000 -name | | |
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clk3 [get_nets PHI2_c] | 5.000 ns| 26.212 ns| 8 *
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create_clock -period 5.000000 -name | | |
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clk2 [get_nets nCCAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk1 [get_nets nCRAS_c] | -| -| 0
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create_clock -period 5.000000 -name | | |
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clk0 [get_nets RCLK_c] | 5.000 ns| 15.222 ns| 10 *
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--------------------------------------------------------------------------------
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2 constraints not met.
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--------------------------------------------------------------------------------
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Critical Nets | Loads| Errors| % of total
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--------------------------------------------------------------------------------
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n14 | 16| 200| 15.72%
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n12_adj_8 | 2| 198| 15.57%
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n14_adj_3 | 1| 183| 14.39%
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n14_adj_7 | 2| 176| 13.84%
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--------------------------------------------------------------------------------
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 1272 Score: 5951146
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Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage)
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Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
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CPU_TIME_REPORT: 0 secs
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