Apple-2-HW
/
RAM2GS
mirror of https://github.com/garrettsworkshop/RAM2GS.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log

983 lines
36 KiB
Plaintext
Raw Blame History

synthesis -f "RAM2GS_LCMXO2_640HC_impl1_lattice.synproj"
synthesis: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Sat Oct 09 01:19:13 2021
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
<postMsg mid="35002000" type="Info" dynamic="0" navigation="0" />
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP100.
The -d option is LCMXO2-640HC.
Using package TQFP100.
Using performance grade 4.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-640HC
### Package : TQFP100
### Speed : 4
##########################################################
<postMsg mid="35001781" type="Info" dynamic="0" navigation="0" />
Optimization goal = Balanced
Top-level module name = RAM2GS.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): RAM2GS
<postMsg mid="35901018" type="Info" dynamic="2" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): " arg1="RAM2GS" arg2="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg3="1" />
<postMsg mid="35901209" type="Warning" dynamic="3" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): " arg1="32" arg2="2" arg3="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg4="123" />
<postMsg mid="35901209" type="Warning" dynamic="3" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): " arg1="32" arg2="18" arg3="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg4="128" />
<postMsg mid="35901209" type="Warning" dynamic="3" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): " arg1="32" arg2="4" arg3="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg4="255" />
<postMsg mid="35901018" type="Info" dynamic="2" navigation="2" arg0="C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): " arg1="EFB" arg2="C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v" arg3="1800" />
<postMsg mid="35931013" type="Warning" dynamic="2" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): " arg1="PLL0DATI7" arg2="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg3="348" />
Last elaborated design is RAM2GS()
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Top-level module name = RAM2GS.
######## Missing driver on net n1128. Patching with GND.
######## Missing driver on net n1132. Patching with GND.
######## Missing driver on net n1133. Patching with GND.
######## Missing driver on net n1134. Patching with GND.
######## Missing driver on net n1135. Patching with GND.
######## Missing driver on net n1131. Patching with GND.
######## Missing driver on net n1130. Patching with GND.
######## Missing driver on net n1136. Patching with GND.
######## Missing driver on net n1137. Patching with GND.
######## Missing driver on net n1138. Patching with GND.
######## Missing driver on net n1139. Patching with GND.
######## Missing driver on net n1140. Patching with GND.
######## Missing driver on net n1141. Patching with GND.
######## Missing driver on net n1142. Patching with GND.
######## Missing driver on net n1143. Patching with GND.
######## Missing driver on net n1144. Patching with GND.
######## Missing driver on net n1145. Patching with GND.
######## Missing driver on net n1146. Patching with GND.
######## Missing driver on net n1147. Patching with GND.
######## Missing driver on net n1148. Patching with GND.
######## Missing driver on net n1129. Patching with GND.
######## Missing driver on net n1149. Patching with GND.
######## Missing driver on net n1150. Patching with GND.
######## Missing driver on net n1151. Patching with GND.
######## Missing driver on net n1152. Patching with GND.
######## Missing driver on net n1153. Patching with GND.
######## Missing driver on net n1154. Patching with GND.
######## Missing driver on net n1155. Patching with GND.
######## Missing driver on net n1156. Patching with GND.
######## Missing driver on net n1157. Patching with GND.
<postMsg mid="35001774" type="Info" dynamic="2" navigation="0" arg0="IS" arg1="one-hot" />
original encoding -> new encoding (one-hot encoding)
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
<postMsg mid="35001774" type="Info" dynamic="2" navigation="0" arg0="S" arg1="one-hot" />
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
GSR will not be inferred because no asynchronous signal was found in the netlist.
<postMsg mid="35001779" type="Warning" dynamic="1" navigation="0" arg0="C1Submitted_542" />
Applying 200.000000 MHz constraint to all clocks
<postMsg mid="35001611" type="Warning" dynamic="0" navigation="0" />
Results of NGD DRC are available in RAM2GS_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Running DRC...
DRC complete with no errors or warnings
Design Results:
452 blocks expanded
completed the first expansion
All blocks are expanded and NGD expansion is successful.
Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
################### Begin Area Report (RAM2GS)######################
Number of register bits => 119 of 877 (13 % )
BB => 8
CCU2D => 10
EFB => 1
FD1P3AX => 30
FD1P3AY => 4
FD1P3IX => 3
FD1S3AX => 64
FD1S3IX => 14
FD1S3JX => 4
GSR => 1
IB => 25
INV => 3
LUT4 => 236
OB => 30
PFUMX => 16
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 5
Net : RCLK_c, loads : 79
Net : PHI2_c, loads : 11
Net : nCRAS_c, loads : 2
Net : nCCAS_c, loads : 2
Net : wb_clk, loads : 1
Clock Enable Nets
Number of Clock Enables: 14
Top 10 highest fanout Clock Enables:
Net : RCLK_c_enable_27, loads : 16
Net : RCLK_c_enable_20, loads : 4
Net : RCLK_c_enable_25, loads : 2
Net : RCLK_c_enable_24, loads : 2
Net : RCLK_c_enable_29, loads : 2
Net : PHI2_N_151_enable_5, loads : 2
Net : PHI2_N_151_enable_3, loads : 2
Net : PHI2_N_151_enable_1, loads : 1
Net : Ready_N_280, loads : 1
Net : PHI2_N_151_enable_6, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : InitReady, loads : 36
Net : FS_11, loads : 32
Net : FS_10, loads : 32
Net : FS_9, loads : 26
Net : FS_7, loads : 25
Net : FS_8, loads : 23
Net : FS_6, loads : 21
Net : FS_5, loads : 21
Net : FS_12, loads : 20
Net : CmdUFMShift, loads : 16
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 *
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
Peak Memory Usage: 58.262 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.813 secs
--------------------------------------------------------------
map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0
map: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd
Picdevice="LCMXO2-640HC"
Pictype="TQFP100"
Picspeed=4
Remove unused logic
Do not produce over sized NCDs.
Part used: LCMXO2-640HCTQFP100, Performance used: 4.
Loading device for application baspr from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Running general design DRC...
Removing unused logic...
Optimizing...
Design Summary:
Number of registers: 119 out of 877 (14%)
PFU registers: 119 out of 640 (19%)
PIO registers: 0 out of 237 (0%)
Number of SLICEs: 131 out of 320 (41%)
SLICEs as Logic/ROM: 131 out of 320 (41%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 10 out of 320 (3%)
Number of LUT4s: 255 out of 640 (40%)
Number used as logic LUTs: 235
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 5
Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
Number of Clock Enables: 14
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
Net InitReady: 1 loads, 1 LSLICEs
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
Net Ready_N_280: 1 loads, 1 LSLICEs
Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
Number of LSRs: 8
Net RASr2: 1 loads, 1 LSLICEs
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
Net wb_rst: 1 loads, 0 LSLICEs
Net nRWE_N_210: 1 loads, 1 LSLICEs
Net C1Submitted_N_232: 2 loads, 2 LSLICEs
Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
Net Ready: 7 loads, 7 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 36 loads
Net FS_10: 32 loads
Net FS_11: 32 loads
Net FS_9: 26 loads
Net FS_7: 25 loads
Net FS_8: 23 loads
Net FS_5: 21 loads
Net FS_6: 21 loads
Net FS_12: 20 loads
Net Ready: 18 loads
Number of warnings: 0
Number of errors: 0
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 37 MB
Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb"
Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
trce: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Sat Oct 09 01:19:15 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
VCCIO Voltage:
3.135 V (Bank 0)
3.135 V (Bank 1)
3.135 V (Bank 2)
3.135 V (Bank 3)
2.375 V (Bank 4)
2.375 V (Bank 5)
2.375 V (Bank 6)
2.375 V (Bank 7)
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Sat Oct 09 01:19:15 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
VCCIO Voltage:
3.135 V (Bank 0)
3.135 V (Bank 1)
3.135 V (Bank 2)
3.135 V (Bank 3)
2.375 V (Bank 4)
2.375 V (Bank 5)
2.375 V (Bank 6)
2.375 V (Bank 7)
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 42 MB
mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd"
---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
Running par. Please wait . . .
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
Sat Oct 09 01:19:16 2021
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 63+4(JTAG)/80 84% used
63+4(JTAG)/79 85% bonded
SLICE 131/320 40% used
EFB 1/1 100% used
Number of Signals: 401
Number of Connections: 1131
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
The following 4 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 52)
PHI2_c (driver: PHI2, clk load #: 13)
nCRAS_c (driver: nCRAS, clk load #: 7)
nCCAS_c (driver: nCCAS, clk load #: 4)
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="PHI2_c" arg1="Primary" arg2="PHI2" arg3="8" arg4="Primary" />
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCRAS_c" arg1="Primary" arg2="nCRAS" arg3="17" arg4="Primary" />
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCCAS_c" arg1="Primary" arg2="nCCAS" arg3="9" arg4="Primary" />
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
............
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
....................
Placer score = 65362.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 65089
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
General PIO: 3 out of 80 (3%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
PRIMARY : 4 out of 8 (50%)
SECONDARY: 0 out of 8 (0%)
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
Number of PIO comps: 63; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
| 2 | 12 / 20 ( 60%) | 3.3V | - |
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 4 secs
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1131 unrouted.
Starting router resource preassignment
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="PHI2_c" />
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="nCRAS_c" />
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="nCCAS_c" />
<postMsg mid="66011008" type="Warning" dynamic="1" navigation="0" arg0="&#xA; Signal=wb_clk loads=1 clock_loads=1" />
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 01:19:22 10/09/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 01:19:22 10/09/21
Start NBR section for initial routing at 01:19:22 10/09/21
Level 1, iteration 1
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
Level 3, iteration 1
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 4, iteration 1
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 01:19:22 10/09/21
Level 1, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 3, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 1
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 2
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
Start NBR section for re-routing at 01:19:23 10/09/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 01:19:23 10/09/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 1.135ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
<postMsg mid="66011008" type="Warning" dynamic="1" navigation="0" arg0="&#xA; Signal=wb_clk loads=1 clock_loads=1" />
Total CPU time 7 secs
Total REAL time: 7 secs
Completely routed.
End of route. 1131 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 1.135
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 7 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Exiting par with exit code 0
Exiting mpartrce with exit code 0
trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
trce: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Sat Oct 09 01:19:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
VCCIO Voltage:
3.135 V (Bank 0)
3.135 V (Bank 1)
3.135 V (Bank 2)
3.135 V (Bank 3)
2.375 V (Bank 4)
2.375 V (Bank 5)
2.375 V (Bank 6)
2.375 V (Bank 7)
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Sat Oct 09 01:19:24 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
VCCIO Voltage:
3.135 V (Bank 0)
3.135 V (Bank 1)
3.135 V (Bank 2)
3.135 V (Bank 3)
2.375 V (Bank 4)
2.375 V (Bank 5)
2.375 V (Bank 6)
2.375 V (Bank 7)
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 42 MB
iotiming "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
I/O Timing Report:
: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: 4
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 5
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: 5
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 6
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: 6
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: M
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running Performance Grade: M
Computing Setup Time ...
Computing Max Clock to Output Delay ...
Computing Hold Time ...
Computing Min Clock to Output Delay ...
Done.
Reference in New Issue View Git Blame Copy Permalink